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Electronics III
Rahman Z
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Image extracted from internet PDF file (common lead-lag circuit) Above is the example of a lead and lag circuit, Vo is used at the positive input to the Op-Amp used for amplification. The RC combination causes a sine wave output. An example circuit of a Wien bridge is shown in the following figure
Image captured from Proteus simulation As shown above, the lead and lag circuit comprises of resistors R2 and R3 combined with capacitors C1 and C2. The lead and lag circuit is accompanied with a voltage divider circuit, the voltage gain of the lead lag circuit has an attenuating value of 1/3, this has to be balanced by the voltage divider circuit with a gain of 3 so that the combined gain will yield unity gain. By calculations, the default gain of the lead lag circuit will always lead to 1/3 regardless of resistor or capacitor values as long as the resistors and capacitors are identical. But the voltage divider circuit has to be physically made with resistors Rahman Z Page 3
Theoretical calculations The following calculations are adapted from a power point slide and are relative to the following image:
Formulas adapted from the circuit From the above formulas, the following general formulas can be found yielding calculations for frequency which is generated by the values in the lead lag circuit
Rahman Z
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General formula adapted from the lead and lag circuit Project specs In the design specs of the project, we are required to build a Wien Bridge oscillator with selectable frequencies, namely 20 Hz, 200Hz, 2 kHz and 20 kHz. These frequencies are attained by the use of the following values of resistors and a set value capacitor of 10 nF Resistor value 820 8.2 k 82 k 820 k Capacitor Value 10 nF 10 nF 10 nF 10 nF Output frequency 19.4 kHz 1.94 kHz 194 Hz 19.4 Hz
Selecting between these resistors in the circuit will ensure the selected frequencies. The output voltage has to be between 0.1Vp-p and 2Vp-p, in my circuit, the output voltage is controlled by a variable resistor in the voltage divider circuit which is not recommended under usual circumstances but since required voltages are so low compared to the input supply voltage of 18Vp-p by the use of a split supply, the controlling of the output voltage using the variable resistor at the voltage divider is also a usable method since the combination of two diodes in parallel with R1 in the circuit will cause a short circuit every time the gain is too high. What must be controlled on the other hand is that the closed loop gain does not go below 3, this will cause the signal to attenuate and eventually die out but it is an unlikely scenario.
Image captured from Proteus, actual circuit of vera-board Due to limitations, no Gerber file has been generated and the circuit has had to be adapted on veraboard for presentation. All values in the above circuit have been implemented on the actual circuit Rahman Z Page 5
Rahman Z
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