Analysis and Design of Power Electronic Transformer for Medium Voltage Levels

H. Iman-Eini University of Tehran Department of Electrical and Computer Engineering himan@ut.ac.ir

Abstract- One key component of the future automation is replacement of conventional distribution transformers by an all-solid-state (power-electronic) alternative. In this paper, the optimum design of a Power Electronic Transformer (PET) will be investigated. In the design process, the PFC and DCDC converters have been integrated to achieve higher efficiency. The proposed PET performs typical functions and has advantages such as power factor correction, voltage regulation, voltage sag and swell elimination, voltage flicker reduction and protection capability in fault situations. In addition, it has other benefits such as light weight, low volume and no toxic dielectric coolants.

S. Farhangi University of Tehran Department of Electrical and Computer Engineering farhangi@ut.ac.ir topology contains three cascaded converters which are Power Factor Controller, isolated DC-DC converter and voltage source inverter. These converters are used for programming input current waveform, electrical isolation and output voltage regulation, respectively. In this topology, for operating properly in medium voltage levels, the series to parallel connection of converters has been used. The number of series converters depends on voltage levels and the type of semiconductors. This paper presents a new topology of PET that improves the Sudhoff topology and enhances its performance. In the proposed topology, the PFC and DC-DC converters have been integrated to reduce the power losses and increase the efficiency. The topology is insensitive to the harmonics, performs input power factor correction, has zero regulation, eliminates voltage sag and swells, reduces the voltage flicker, prevents user faults from affecting the power distribution system, and does not utilize mineral oil or other liquid dielectrics.
PFC 1 Full bridge 1

I.

INTRODUCTION

Distribution transformers are fundamental components in power distribution systems. They are relatively inexpensive, highly reliable, and fairly efficient. However, they have some disadvantages such as heavy weight, large size, sensitivity to harmonics, voltage drop under load, (required) protection from system disruptions and overload, protection of the system from problems arising at or beyond the transformer and environmental concerns regarding mineral oil. These disadvantages are becoming increasingly important as power quality becomes more of a concern. In this case, power electronic based transformer is a good option for solving above problems [1-4]. For the first time, the idea of a solid-state transformer has been introduced by Navy researchers [5]. They proposed a power-electronic transformer that consisted of an ac/ac buck converter to reduce the input voltage to a lower one. This was followed in 1995 by a similar EPRI sponsored effort [6]. The drawbacks of this approach include the use of series tied devices, which are often difficult to control, the lack of magnetic isolation, inability to correct load power factor, and inability to prevent load harmonics from propagating into the primary-voltage system. The next approach for realization of a PET is to use high frequency modulated Ac/Ac transformer [7-8]. This design has the benefit of reducing the transformer size and weight and the stress factor is more reasonable, but it does not provide any benefits in terms of control or power-factor improvement. The previous methods use diode rectifiers in input section of PET's and they have no control on input current waveform and produce undesired current harmonics. For solving this problem a new structure of PET was introduced by Sudhoff shown in Fig. 1. The Sudhoff

PFC 2

A
AC Medium Voltage

Voltage Source Inverter

N
PFC n Full bridge n

Fig. 1: The Sudhoffs PET structure [1]

II.

PROPOSED TOPOLOGY

In Fig. 2, the proposed topology is shown in block diagram form. As can be seen, it is a two stage converter. In the input stage, the primary voltage is divided equally between the input stage modules. Each module should have abilities such as power factor correction, high efficiency and high electrical isolation. For achieving these goals, the PFC converter and isolated DC-DC converter should be integrated. This

idea leads to the loss reduction, by processing the power in one stage instead of two stages. Also the electrical isolation will be gained by high frequency transformers (HF) in the proposed IFBPFC converters. The dc outputs of the proposed IFBPFC modules connected in parallel to supply the output stage. The series to parallel connection provides the task of voltage reduction. The output state converts the resulting bipolar low-voltage dc into three-phase ac. The two-stage topology described herein has many attractive features. First, the integration of PFC and isolated DC-DC converters leads to lower losses and consequently improved efficiency. Second, series-tied semiconductor devices are eliminated because the voltage on the individual modules is reduced to the point where series tying of devices is not necessary. Third, Because of the two-stage topology and the unique capabilities of each stage, the total stress factor is much lower than it would be for the ac/ac chopper. In particular, input-stage devices see high voltage but low current, while output-stage devices see high current but low voltage. Advantages of this solid-state transformer over its more traditional counterparts include the fact that the output voltages are sinusoidal regardless of the input power quality or the output current wave shape. This is due to the controls on the output stage actively suppress output voltage harmonics. Conversely, by suitable control of the input stage the input current is sinusoidal and of unity power factor, regardless of the output current wave shape. In addition, limiting the current at the output and input stages is readily used to prevent secondary faults from propagating through the transformer. Another important point which should be considered to improve the input stage efficiency is the use of BoostFollower idea. In this method the dc bus voltage will be changed proportionally to the changes of input ac voltage. Due to this technique, the efficiency of input stage reach to 95% and the switch stresses become lower [9].
IFBPFC 1

III. ANALYSIS AND DESIGN OF ISOLATED FULL BRIDGE POWER FACTOR COTROLLER The input stage of PET has been made of series connection of isolated full bridge PFC converters or IFBPFC's. This module integrates the PFC and DCDC converter functions. The PFC converter programs the input current waveform and makes the power factor near to one. The DC-DC converter regulates the output DC voltage and makes the electrical isolation using HF transformer. For performing power factor correction, there are different methods such as variable hysteresis control, peak current control and average current control [10]. The main disadvantage of variable hysteresis control is that it operates at variable switching frequency and the disadvantage of peak current control is that it generates some distortion in the input current inherently. So to avoid the mentioned problems, the average current control is chosen for PFC application (see Fig. 3). After choosing the control method for PFC, the integration mechanism of PFC converter with DCDC converter should be defined. For achieving this goal, the single-switch in boost converter is replaced by an isolated-switch and the PWM output is modified by some additional logics shown in Fig. 4. By these corrections, the IFBPFC converter is achieved (see Fig. 5). The operation principle of this approach will be similar to boost converter which is controlled by average current control method. For instance, when the single switch in boost converter is on, all switches in IFBPFC will be on and the boost inductor will be energized. In this case, the transformer primary voltage will be zero. Also, when the single switch in PFC converter is off, the diagonal switch pairs in IFBPFC will be on and off alternatively. By this switching state, the transformer primary voltage will be positive and negative symmetrically. In fact when the switch pair (S1,S4) is on and the switch pair (S2,S3) is off, the inductor current will be conducted through HF transformer and makes the diode pair (D1,D4) be on. So the primary voltage becomes nVo. Similarly when the switch pair (S2,S3) is on and the switch pair (S1,S4) is off, the diode pair (D2,D3) become on and voltage becomes -nVo.
Vin
Single-Switch

HF Transformer

IFBPFC 2 Voltage Source Inverter AC Medium Voltage

DC BUS
R S T

Id

Vout C

IL
Load

LPF

IFBPFC n

Ii IP PWM
AB C2

PI
controller

Vref

Series Isolated AC-DC converters

Fig. 2: The proposed topology of PET

LP
filter

Fig. 3: PFC with average current control method

Single-Switch
S1

Isolated-Switch
S2 HF D1 D2

Vout 1.0KV

0.5KV

S3

S4

D3

D4
0V 0s V(D12:2) Time

Fig. 4.a: Replacement of Single-Switch with proposed Isolated-Switch

50ms

100ms

150ms

200ms

Vout Vin Ii PWM

J CLK K

Q Q

G1 G2 G3 G4
P W M

Fig. 6.a: The output DC voltage of IFBPFC

100 Vin/15 50 Iin

Average current controller

JK Flip-Flop

Driver

Fig. 4.b: Modified circuit for PWM output in IFBPFC

-50

Vin

L Id
S1 S2 S3 S4 n:1
D1 D3

Vout
C

-100 100ms 125ms V(V4:+,V4:-)/15

150ms -I(V4) Time

175ms

200ms

Fig. 6.b: The input voltage and current waveforms of IFBPFC

P W M Transformer voltage 1.0KV

HF
transformer

D2

D4

0V

Corected PWM Ii Vi Vo Vref

-1.0KV

Average current controller

134.41ms V(T1,T2)

134.60ms Time

134.80ms

135.00ms

Fig. 5: The proposed IFBPFC module scheme

Fig. 6.c: The HF transformer primary voltage waveform

To validate the performance of IFBPFC module, it is implemented in SPICE and the simulation results are shown in Fig. 6. In simulations, the IFBPFC power is 10 KW, the input peak voltage is 1000 V and the output DC voltage is 700 V. The parameters value used for simulations has been shown in table 1. As it can be seen in Fig. 6.a, the output DC voltage is 700 V and its voltage ripple is calculated by Equation (1).

Fig. 6.c shows the transformer primary voltage. As it can be seen, the primary voltage in positive and negative alternations is symmetrical. Additionally in our simulations, the switching frequency is 16 kHz, so the weight and volume of transformer becomes lower

IV.

SIMULATION RESULTS OF PET

Vrip

1 I ic (t )dt = L sin(2 wt ) C 2wC

(1)

In Equation (1), C is the output capacitor, w is the mains frequency and IL is the Load current. Despite of the voltage ripple on the DC bus, the PET will operate properly. Because the next block of PET, voltage source inverter, will eliminate the voltage ripple by proper variation of modulation index. Fig. 6.b depicts the input voltage and input current simultaneously. Although, the input circuit is nonlinear (due to diode rectifier), the input voltage and current are in phase and the power factor is near to one. Also the THD of input current is 3.3% and it is compatible with IEEE and IEC standards. .

By connecting the voltage source inverter to DC bus of series to parallel IFBPFC modules, the PET structure is achieved. As it can be seen in Fig. 7, the voltage source inverter is controlled by SPWM method. In this case, the direct axis, quadratic axis, and zero sequence quantities for three-phase sinusoidal signal is computed by Park transformation. Then the dq voltage terms are compared by reference signals Vdref=1 and Vqref=0 and error signals enter to PI controllers. Next the PI controller outputs are transformed to three-phase sinusoidal abc voltage terms and used to generate appropriate inverter gate pulses. To evaluate the expected performance of the powerelectronic based transformer, the design was simulated to predict steady state and transient performance. In these simulations the Phase-Neutral voltage is 3 kV and the PET power is 30 kVA. Also the parameters value used for simulations has been shown in table 1.

4000 2000

VB

Vin (V)

Load

0 -2000 -4000

0.1

0.2

0.3

0.4

0.5

0.6

Time (S)

500

Vdref=1 p.u.
PI controller

V abc

PWM pulse generator

Vab (V)

Vabc,ref
dq0 to abc transformation PI controller

Vd Vq
Vqref=0 p.u.
abc to dq0 transformation

-500 0 0.1 0.2 0.3 0.4 0.5 0.6

Time (S)

Fig. 10: PET response to voltage flicker

input voltage & current
40 Vin/100 Input current

Fig. 7: The SPWM voltage source inverter diagram

Vin & Iin
4000 2000

20 0 -20 -40 0.1

Vin (V)

0 -2000 -4000

0.12

0.14

0.16

0.18

0.2

0.22

0.1

0.2

0.3

0.4

0.5

0.6

Time (S)

Time (S) output phase voltage & current

100 Va/4 Phase current

500

Va & Ia

50 0 -50 -100 0.1

Vab (V)

-500 0 0.1 0.2 0.3 0.4 0.5 0.6

0.12

0.14

0.16

0.18

0.2

0.22

Time (S)

Time (S)

Fig. 11: PET current and voltage waveforms in reactive load

input voltage & current
40

Fig. 8: PET response to voltage sag condition

4000
20 0 -20 -40 0.1 Vin/100 Input current

Vin (V)

2000 0 -2000 -4000 0 0.1 0.2 0.3 0.4 0.5 0.6

Vin & Iin

0.12

0.14

0.16

0.18

0.2

0.22

time (S)

Time (S) output phase voltage & current

100 Va/4 Phase current

Vab (V)

Va & Ia

500 0 -500 0 0.1 0.2 0.3 0.4 0.5 0.6

50 0 -50 -100 0.1

0.12

0.14

0.16

0.18

0.2

0.22

Time (S)

time (S)

Fig. 12: PET waveforms in capacitive load Fig. 9: PET response to voltage swell condition

Fig. 8 and Fig. 9 show how the power electronic transformer handles the voltage sag and voltage swell conditions, respectively. In these simulations the PET load is 30 kW and the mains voltage is 3 kV. In Fig. 8, mains voltage reduces 30 percent from t=200 ms till t=300 ms and in Fig. 9, the mains voltage is increased 30 percent for 10 time cycles. As it can be seen, in Figures 8 and 9, the power electronic transformer manages these situations properly and adjusts the output voltage to desired level (380 V) without any dip or surge in output signal.

Another simulation depicts the voltage flicker elimination. In this simulation, the mains voltage has been modulated by a sinusoidal waveform which its frequency is 8 Hz and its modulation index is 5 %. As it can be seen in Fig. 10, the power electronic transformer has eliminated the mains voltage flicker. So the PETs output is clear and doesnt have any voltage flicker. Fig. 11 and Fig. 12 show the PET input power factor correction ability. In these simulations the active load is assumed to be 20 kW and the reactive power is assumed to be 10 kVAR inductive and capacitive, respectively. As

it can be seen, in Figures 11 and 12, the input current and the input voltages are in phase and have sinusoidal wave shapes despite the load current is lead or lag. V. CONCLUSION

Table 1: The parameters value used for PET

PET parameters Series modules No. Input inductor IFBPFCs switch No. IFBPFCs diode No. IFBPFCs capacitor Switching frequency HF Transformer ratio Inverters switch No. Symbol IFBPFC. No. L SKiiP 592GB170 IGBT 1700V SKR 47F Diode 1700V C f n SKiiP 232GD120 IGBT 1200V200A fi Lf Cf Unit 3 3.5 mH 4 4 2 mF 16 kHz 1.7:1 4

In this paper, the optimum design of a PET has been investigated. To obtain higher efficiency, the PFC and DC-DC converters have been integrated. The series to parallel connection of proposed IFBPFC modules provide the task of voltage reduction. The twostage topology described in this paper has many advantages such as power factor correction, voltage regulation, voltage sag and swell elimination, voltage flicker reduction. In addition, it has other benefits such as light weight, low volume and no toxic dielectric coolants. REFERENCES
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Inverter frequency Output filter inductor Output filter capacitor

5 kHz 2 mH 5 mF

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]