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Reconfiguration
Isolation (Bypassing)
Normal Test functional block 1 Test functional block 2
Analog function
sel1
Analog function
sel2
Reconfiguration
Loop Around
Loop around for back-to-back testing
voice
sel2
Modulator
RF
voice
Demodulator
Downconverter
sel1
RF
Example
CODEC, RF/IF Test
Reconfiguration
Reconfiguration
In test mode
Reconfiguration
Phase
Carefully design for embedded switches is needed to maintain the opamp performance (offset, frequency response, SR, CMRR, )
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12
Reconfiguration
Example
C1 C2 C3 =111 C1 C2 C3 =100 C1 C2 C3 =000
Reconfiguration
V-
M1
M2
V+
Cc
Vo
M6 5uA
M3 VSS
M4
M9
Reconfiguration
In test model
Partitioning CUT into functional building blocks Converting each building block to an oscillator
Shift poles on the imaginary axis Adding a feedback loop to the CUT Combine various building blocks to form an oscillator
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Reconfiguration
Challenges
No universal rules to transfer DUT into oscillator No trivial relationship between the oscillation frequency and the specification under test
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12
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SO
+
Scan Path
PI
+ +
CUT
+
PO
SI
+
SO
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Shift In Gnd
Shift Out
Scan Path
PI V-I Converter Vdd CUT V-I Converter Vdd V-I Converter Vdd PO
Challenges
Resistance in Vdd Path Aliasing
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Summing or weighted-summing the internal node voltage or branch current During Testing
C=0, output is initialized to 0 C=1, performs the integration function The analog signature provided by the =RC of the integrator
Challenge -- Aliasing
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Checksum
X (t + t ) = AX (t ) + Bu (t )
x1 (t + t ) + x2 (t + t ) = a11 x1 (t ) + a12 x2 (t ) + a21 x1 (t ) + a22 x2 (t ) + b1u (t ) + b2u (t ) = (a11 + a21 )x1 (t ) + (a12 + a22 )x2 (t ) + (b1 + b2 )u (t )
a12 + a22 x1 (t ) u 0] x2 (t ) + [b1 + b2 ]u (t ) b1+b2 x3 (t )
Let
x1
x2
-1 -1
y
a12+a22
x3 (t + t ) = x1 (t + t ) + x2 (t + t )
a11+a21
1/s
x3
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Checksum
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Checksum
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Sub-Band Filtering
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Sub-Band Filtering
Filtering Example
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Sub-Band Filtering
Pros -- More immune from fault aliasing problems Cons -- Requires on-chip ADC
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TDI TMS
TAP controller
TDO TCK
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The introduction of analog components to 1149.1 compliant The introduction of analog components to 1149.1 compliant chip, the ability to isolate faulty interconnects on the analog chip, the ability to isolate faulty interconnects on the analog I/O pins does not exist!! I/O pins does not exist!!
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12
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Core
Circuit
VH VL VG
Analog Test Access Port (ATAP = AT1 + AT2) Digital Test Access Port (TAP ) as in IEEE1149.1
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TDI TMS
VTH
CD
Analog core
Input value can be sensed, digitized (against VTH), and captured in the register Ability to disconnect the receiving core from the pin using CD and drive either a 1 or a 0 ABMs can be implemented with actual switches or can be integral in the analog circuit
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S1
VH
S2
Vclamp S9 S10
S3
VL
S4 S5 S8 S7 S6
+ -
VTH
- +
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Example
Histogram
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Example
Differential signals, IEEE1149.4 metrology
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Example
e.g. convert a delay into an oscillation whose frequency is counted e.g. compare Vin to voltage from RC, and measure delay
Known Delay
Reference (1/2)
1.
2.
3.
4.
5.
6.
7.
8.
M. Soma & V. Kolarik A Design-for-Test Technique for Switched-Capacitors Filters,, IEEE European Design & Test Conference, pp.42-47, Paris, March 1994 D. Vazquez, J. L. Huertas, A. Rueda, Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design, VLSI Test Symposium, pp.42-47, 1996 M. Renovell, F. Azais, Y. Bertrand, Optimized implementations of the multi-configuration DFT technique for analog circuits, Design, Automation and Test in Europe, pp.815-821, 1998 J. Crols, M. Steyaert, Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages, IEEE Journal of Solid-State Circuits, vol.29 Issue 8, pp.936-942, Aug. 1994 K. Arabi, B. Kaminska, Oscillation-Test Strategy for Analog and Mixed-Signal Integrated Circuits, VLSI Test Symposium, pp.476-482, 1996 K. Arabi, B. Kaminska, Testing Analog and Mixed-Signal Integrated Circuits Using Oscillation-Test Method, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, Issue 7, pp.745-753, July 1997 C. L. Wey, Built-in self-test (BIST) structure for analog circuit fault diagnosis, IEEE Transactions on Instrumentation and Measurement, vol.39, Issue 3, pp.517-521, June 1990 M. Soma, Structure and concepts for current-based analog scan, IEEE Custom Integrated Circuits Conference, pp.517-520, 1995
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12
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Reference (2/2)
9.
10.
11.
12.
13.
14.
M. Sidiropulos, V. Stopjakova, H. Manhaeve, Implementation of a BIC monitor in a new analog BIST structure, IEEE International Workshop on IDDQ Testing, pp.59-63, 1996 S. Siskos, A. A. Hatzopoulos, A simple built-in current sensor for current monitoring in mixed-signal circuits, IEEE Transactions on Instrumentation and Measurement, vol.46, Issue 6, pp.1301-1304, Dec. 1997 M. Renovell, F. Azais, Y. Bertrand, On-chip analog output response compaction, European Design and Test Conference, pp.568-572, 1997 A. Chatterjee, B. C. Kim, N. Nagi, DC built-in self-test for linear analog circuits, IEEE Design & Test of Computers, vol.13, Issue 2, pp.26-33, Summer 1996 J. Roh, J. A. Abraham, Subband filtering scheme for analog and mixed-signal circuit testing, International Test Conference, pp.221-229, 1999 http://grouper.ieee.org/groups/1149/4/index.html
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