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  • BISC Support in GCC: Zbigniew Chamski

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    This document summarizes a discussion about providing GCC compiler support for BISC (Binary Instruction Set Computers). It notes that BISC architectures have explicit instruction-level parallelism constraints that current GCC scheduling and register allocation methods do not directly address. The document outlines possible approaches for improving GCC support, such as incorporating BISC features into existing compiler infrastructure or providing new infrastructure specifically for scheduling and register allocation. It acknowledges challenges like large schedule representations but argues infrastructure improvements could help both BISC and CISC targets with resource awareness. Overall it advocates obtaining funding and collaboration to further develop GCC support for BISC architectures.

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    This document summarizes a discussion about providing GCC compiler support for BISC (Binary Instruction Set Computers). It notes that BISC architectures have explicit instruction-level parallelism constraints that current GCC scheduling and register allocation methods do not directly address. The document outlines possible approaches for improving GCC support, such as incorporating BISC features into existing compiler infrastructure or providing new infrastructure specifically for scheduling and register allocation. It acknowledges challenges like large schedule representations but argues infrastructure improvements could help both BISC and CISC targets with resource awareness. Overall it advocates obtaining funding and collaboration to further develop GCC support for BISC architectures.

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    15 visualizzazioni9 pagine

    BISC Support in GCC: Zbigniew Chamski

    Caricato da

    openid_AePkLAJc
    This document summarizes a discussion about providing GCC compiler support for BISC (Binary Instruction Set Computers). It notes that BISC architectures have explicit instruction-level parallelism constraints that current GCC scheduling and register allocation methods do not directly address. The document outlines possible approaches for improving GCC support, such as incorporating BISC features into existing compiler infrastructure or providing new infrastructure specifically for scheduling and register allocation. It acknowledges challenges like large schedule representations but argues infrastructure improvements could help both BISC and CISC targets with resource awareness. Overall it advocates obtaining funding and collaboration to further develop GCC support for BISC architectures.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Scarica in formato PDF, TXT o leggi online su Scribd
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    BISC support in GCC

    Zbigniew Chamski zbigniew.chamski@gmail.com

    GCC Developers Gathering, London, June 19, 2011

    Why bother at all?

    According to Ken Zadeck (2009 Summit)


    BISC = Bull*it Instruction Set Computer not RISC, not CISC thus, irrelevevant to GCC HW folks do look at power/energy consumption some don't want to put a compiler backend in HW they keep designing lower-power cores... ... and asking for effective compiler support
    GCC Developers Gathering, London, June 19, 2011 2

    Challenge: VLIW, DSP, EPIC...


    Why should we bother?

    GCC support now a must for manufacturers


    end-customer requirement marketing

    some RISC targets have BISC-ish features


    delay slots, partial interlocks pipeline/architecture constraints visible in SW

    CISC could possibly get power reductions


    GCC Developers Gathering, London, June 19, 2011 3

    BISC features

    explicit ILP and scheduling constraints


    simultaneous operations: must be in same cycle fixed delays between ops: must be X cycles apart delay slots: X cycles x Y issue units (!) lookup-based VLIW: compiler-defined microcode clustered register files, constrained datapath issue slot usage rules

    resource bottlenecks

    weird ops: saturated arithmetic, auto-incr/decr


    GCC Developers Gathering, London, June 19, 2011 4

    Current limitations

    no general time-centric view of the schedule scheduling: DFA


    complexity explodes if target has few constraints peephole optimization of the schedule difficult decoupled from scheduling non-reg resource allocation on the scheduling side solutions available, just plain development
    GCC Developers Gathering, London, June 19, 2011 5

    register allocation

    weird ops: non-blocking

    Possible directions

    Squeeze features into existing infrastructure


    C6x other targets? insn reservation patterns (cycles x resources) cycle-oriented intra-/inter-BB reservation tables replicated resources (need just one extra RTX) list/superblock scheduling, tail duplication, ...
    GCC Developers Gathering, London, June 19, 2011 6

    Provide infrastructure for explicit scheduling/RA


    Provide strategies based on the infrastructure

    Issues (& ancillary benefits)

    Size of explicit schedule representations


    #cycles x #resources x sizeof (single_use_descr) order of magnitude: 1k x 1k x 4words = 16-32MB need to implement algorithms/strategies there are quite some published research results potential power/energy impact on OOO execution

    Infrastructure is a stepping store


    Resource awareness can help CISC targets

    GCC Developers Gathering, London, June 19, 2011

    Going forward

    There's GPLed, RTL-based proof it works


    Salto package (Inria, ~1999-2000) support for C6x, TriMedia; MIPS/Sparc peephole contains basic scheduling and RA implementations no compiler support vs. no industry drive drive the design + promote the approach (int/ext) get funding/support to make & complete the move
    GCC Developers Gathering, London, June 19, 2011 8

    Chicken-and-egg problem

    We'd need champions and sponsors ;-)


    Thanks!

    GCC Developers Gathering, London, June 19, 2011

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