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[4]

[51
[6]

[7]

[81
[9] [10]
[11]

[12]

combinational circuit," in Proc. Symp. Math. Theory of Automata, Apr. 1963, pp. 484-528. D. B. Armstrong, "On finding a nearly minimal set of fault detection tests for combinational logic nets," IEEE Trans. Electron. Comput., vol. EC-15, pp. 66-73, Feb. 1966. F. J. 0. Dias, "Fault masking in combinational logic circuits," IEEE Trans. Comput., vol. C-24, pp. 476-482, May 1975. W. Kautz, "Testing for faults in cellular logic arrays," in Proc. IEEE Symp. Automata Theory and Logic Design, 1967, pp. 161-174. P. R. Menon and A. D. Friedman, "Fault detection in iterative logic arrays," IEEE Trans. Comput., vol. C-20, pp. 524-535, May 1971. R. W. Landgraff and S. S. Yau, "Design of diagnosable iterative arrays," IEEE Trans. Comput., vol. C-20, pp. 867-877, Aug. 1971. A. D. Friedman, "Easily testable iterative systems," IEEE Trans. Comput., vol. C-22, pp. 1061-1064, Dec. 1973. F. J. 0. Dias, "Multiple-fault analysis in combinational logic circuit," Ph.D. dissertation, Stanford University, Stanford, CA, July 1975. F. C. Hennie, "Fault detecting experiments for sequential circuits," in Proc. 5th Ann. Symp. Switching Theory and Logical Design, 1964, pp. 95-110. --, Finite-State Models for Logical Machines. New York: Wiley, 1968.

[13] H. W. Gschwind and E. J. McCluskey, Design of Digital Computers. Amsterdam, The Netherlands: Springer, 1975.

Francisco J. 0. Dias (S'72-M'75) was born in Sao Paulo, Brazil, on December 5, 1945. He received the B.S. degree in electrical engineering from the Escola Politecnica, University of Sao Paulo, Sao Paulo, Brazil in 1969 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1972 and 1975, respectively. From 1970 to 1971 he was an Instructor at Escola Politecnica and from 1972 to 1975 a Research Assistant at Digital Systems Laboratory while working towards the Ph.D. degree at Stanford University. Presently he is an Assistant Professor at University of SAo Paulo, where he has been involved in research projects of testing and reliability evaluation. His present interests include fail-safe systems, cellular arrays, and reliability calculations. Dr. Dias is a member of Sigma Xi.

Transition Count Testing of Combinational Logic Circuits

JOHN P. HAYES, MEMBER, IEEE

Abstract-Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. It is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one- and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for' this purpose.
Index Terms-Combinational logic circuits, fault detection, fault diagnosis, minimal test sets, test generation, transition count (TC) testing. Manuscript received July 9, 1975; revised December 2, 1975. This research was supported by the Office of Naval Research under Contract N00014-67-A-0269-0019, and by the Joint Services Electronics Program through the Air Force Office of Scientific Research/AFSC under Contract F44620-71-C-0067. The author is with the Department of Electrical Engineering and the Computer Science Program, University of Southern California, Los Angeles, CA 90007.

I. INTRODUCTION

SEVERAL commercially available testers for digital logic circuits employ the following technique for fault diagnosis. A predetermined sequence of test patterns is applied to the unit under test (UUT). The response sequence R appearing at some selected test point P of the UUT is monitored. Rather than recording the entire sequence R at point P as is done in conventional testing, only the transition count (TC) c(R) of R is recorded, i.e., the number of times the signal at P changes value (from 0 to 1 or from 1 to 0). The TC c(R) is then compared to the TC c (Ro) that should appear at P if the UUT is fault-free. If c(R) and c(Ro) differ, it can be concluded that a fault has occurred in some part of the UUT having P as a primary output line. By repeating this procedure for other test points in the UUT a high degree of fault detection and isolation may be possible. We will refer to this test method as transition count testing or TC testing. Fig. 1 shows the flowchart for a typical TC testing algorithm. Consider the NAND network NA shown in Fig. 2. Fig. 2(a) shows the response sequence appearing on every line of NA resulting from the application of a particular test sequence S of length 5. Fig. 2(b) shows the corresponding TC's on every line. Suppose the fault f = "line

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11010

1976

11110

(a)

zI

z2
(b)

Fig. 2. (a) Response of NA to a test sequence S of length 5. (b) Corresponding TC.

sented. The properties of TC tests and the problem of constructing efficient TC tests for combinational circuits are investigated. The relationship between TC testing and conventional testing is examined in Section II, and a general heuristic rule for designing "good" TC tests is proposed. Sections III and IV consider the genFig. 1. Typical TC testing algorithm. eration of optimal or near-optimal TC tests to detect single and multiple stuck-line faults in combinational a stuck-at-1" is present in NA. This causes the sequence circuits. Fault location using TC testing is examined in on zi, the output of gate G1, to change from 11110 to Section V. 11010. This is reflected in a change in TC from 1 to 3 as II. PROPERTIES OF TRANSITION COUNT TESTS shown in Fig. 2(b). Hence, fault f is detectable by transition counting if S is used as the test sequence and z, is Let R = rlr2*..rm be any mr-bit binary sequence. chosen as the test point. Note that although f also Definition 1: The TC c(R) of R = rlr2**-rm is given by changes the response sequence on output line Z2 (from m -I 00011 to 00111), it does not affect its TC. For the given c(R) = E (ri @ ri+ ), i=l1 test sequence, therefore, Z2 is not a suitable test point for detecting f. where z denotes arithmetic summation and @D denotes TC testing has the advantage that, unlike most con- sum modulo 2. ventional test methods, it is not necessary to record eiIt follows from this definition that 0 < c (R) < m -1. ther the observed test response sequence R or the cor- If R = Fl2-..Pm, the sequence obtained by complementrect response sequence Ro; only their TC's are needed. ing every bit of R, then c(R) = c (R). The number of bits required to represent c(R) is at Let Bn denote the set of all 2n n-bit binary vectors. most rlogl RI], where IRI is the length (number of bits) Bn can be considered as the set of possible test patterns of R, and rxl denotes the smallest integer greater than for an n-input logic circuit N. Let S = S1S2 ...m be a seor equal to x. Thus, by storing TC's instead of entire re- quence of n-bit vectors where si C Bn for 1 < i < m. Let sponse sequences, a substantial reduction in fault dic- F = fF1,F2,.-.,FuJ be a set of possible faults in N. Let Ro tionary size may be possible. TC testing has the addi- be the response observed at some test point when S is tional advantage that the basic test circuitry needed is a applied to the fault-free circuit N, and let Ri be the cortransition detector and counter. Standard easily gener- responding response when fault Fi E F is present. ated test patterns such as Gray-coded or pseudorandom Definition 2: S is a TC test for N with respect to F if sequences are usually employed in TC test systems. c(Ro) M c(RA) for 1 < i < u. S is minimal if for every TC Hence, very simple and inexpensive TC testers can be test S' for N with respect to F, I SI < IS'I, where I SI demade. notes the length of S, i.e., the number of test patterns it In this paper a formal analysis of TC testing is pre- contains.

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It is convenient to assume that N, the circuit under test, is a single-output circuit whose primary output line is the test point used for monitoring TC's. A fault F in N will be said to be TC detectable if some sequence S is a TC test for F. The fact that c(R) = c(R) implies that faults may exist that are detectable in the usual sense but are not TC detectable. An example of such a fault is one causing the function z appearing at the observed output of N to change to its complement z. No input sequence is a TC test for N, although N responds incorrectly to every input combination. Two faults in N are said to be distinguishable if they produce different output sequences in response to some input sequence. Two faults are TC distinguishable if they produce output sequences with different TC's in response to some input sequence. Faults that are distinguishable in the usual sense may not be TC distinguishable. For example, consider the following faults involving the output line z of N: fo = "line z stuck at 0" and fi = "line z stuck at 1." The response to every input sequence applied to N with fo(fl) present is a sequence consisting of all 0's (l's), hence the TC is zero. Thus, fo and f, are distinguishable but not TC distinguishable. We conclude that a fault in N is TC detectable only if it is detectable, while two faults in N are TC distinguishable only if they are distinguishable. In each case the converse is false. When using transition counting for fault detection, it is of interest to find test sequences with the property that as many faults as possible produce incorrect TC's. Let S by an input sequence for N whose correct m-bit output response is Ro. In general some flexibility exists in choosing S and therefore in choosing c(Ro). We now pose the question: what is the "best" value of c(RO) so that as many faulty response sequences as possible have TC's different from c(Ro)? While the exact answer depends on N and the set of faults under consideration, it is possible to formulate a general measure of the "goodness" of c(Ro). Let C(m,i) be the number of binary sequences of length m wfth TC i. It can easily be shown that C(m,i) = 2(ml1). Table I shows all nonzero values of C(m,i) for 1 - m < 10. Each row of this table can be conveniently computed from the row above it using the following relationship (which is essentially Pascal's Formula): C(m + 1,i)= C(m,i) + C(m,i-1). In order to maximize its fault coverage a TC test S should be chosen so that as few potential fault responses as possible have the same TC as the correct response Ro. In other words, C(m,c(Ro)) should be minimized. C(m,c(Ro)) = 2(QOf)), hence to minimize C(m,c(Ro)) we should attempt either to minimize or maximize c(RO). Thus, we can state the following general heuristic rule for the design of TC tests. Rule 1: To maximize the fault coverage of a TC test 5, S should be constructed so that c(Ro) is either as large or as small as possible.

If the UUT is purely combinational, the order in which test patterns are applied does not affect its behavior, and a given set of test patterns may be rearranged in any way to increase or decrease c(RO). If the UUT is sequential then arbitrary reorderings of input patterns are not usually possible. In the following sections we consider the problem of generating TC tests for single-output combinational circuits, where the fault model is the standard stuck-line model.'
III. FAULT DETECTION BY TRANSITION COUNTING In this section we consider the design of TC tests to detect stuck-line faults in combinational circuits. Any line in a circuit may be either stuck at logical 0 (s-a-0) or stuck at logical 1 (s-a-1), while the gate functions remain unchanged. Both single faults (only one line s-a0/1) and multiple faults (one or more lines s-a-O/1) will be considered. To simplify the analysis only irredundant' NAND circuits will be treated; it can be shown that this involves no significant loss of generality [1]. An input sequence S to a single-output circuit N will be called a single (multiple) fault TC test for N if S is a TC test for all single (multiple) stuck-line faults in N when the primary output of N is the test point used for observing TC's. First we examine the problem of TC test generation for a single n-input (NAND) gate Gn. All faults in Gn can be detected in the conventional manner using a unique set of n + 1 test patterns T. T may be conveniently divided into n e-tests and 1 u-test [1] where, in the case of NAND gates, u = (1,1, - ,1,1) el= (0,1,- ,1,1) e2= (1,0, ,1,1)

en= (1,1, * -,0). The correct responses to u and ei are 0 and 1, respectively. T is the unique minimal test set for Gn with respect to both single and multiple faults [1]. Every TC test S for Gn must include every test pattern in T, hence,ISI >n+ 1. For n = 1 and n = 2 it is easily shown that the sequences Si = uel, and S2 = e1ue2, respectively, are minimal TC tests. For n > 2, however, a sequence of length n + 2 is needed. Theorem 1: Let S* = uele2..een-lenel, where n > 2. S* is a minimal TC test with respect to both single and multiple faults for an n-input gate Gn. Proof: If S* is nonminimal there must be a TC test S for Gn of length n + 1 and S must contain every
1 A circuit is irredundant if no lines or gates can be removed from the circuit without altering its output function. This is equivalent to saying that the circuit is irredundant if it contains no undetectable single or multiple stuck-line faults.

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1976

TABLE I
i
0

single and multiple faults. U S* is by no means the only minimal TC test for gn. 2 For example, the sequence S' = e1e2e3au, where a de2 2 notes the complement of u, is a minimal TC test for G3. 3 2 4 2 Although a is an inessential test in the sense that all the 4 2 6 6 faults it detects are detected by other members of S', a 2 2 8 8 12 is essential to making S' a TC test. 6 10 20 20 10 2 S* is an example of a TC test in which an individual 2 12 30 40 30 12 test pattern (ei) is repeated. In some situations it may 14 42 8 70 14 2 70 42 be necessary to repeat test patterns in order to con16 56 112 140 112 56 16 18 72 168 250 250 168 72 struct a TC test. Consider the circuit NB shown in Fig. 3 which realizes the function ZB = XlX2X3 + xlX2X3. All 8 C(m, i), the number of binary sequences of length m with possible input combinations TB are needed to detect all TC i. (single) faults in NB. It can be shown that none of the 8! sequences that are formed by permuting the members member of T exactly once. Since n > 2, the position of u in S is such that it is either preceded or followed by a of TB is a TC test for single faults in NB. Hence, at least one member of TB must be repeated in any TC test for sequence of 2 or more e-tests. Suppose 2 e-tests precede NB. u; then we can write Lemma 1: Let T be any test set for all single faults in S =... eeju... an irredundant single-output combinational network N. Let Ro denote the fault-free response of N to any seRo =***.1 1 0***. quence S containing every member of T. No single fault c(Ro) = 1 if u is the final test in S while c(Ro) = 2 oth- can change the output response of N to S from Ro to Ro. erwise. The fault f/ = "input j of Gn s-a-i" is detected Proof: Suppose fault fi = "line i s-a-d" is present in by ej only. If fj is present in Gn, the resulting output N. S must contain a test ti which detects the fault "line vector is i s-a-d." Hence, ti must place d on line i when N is fault-free. This implies that ti yields the correct reR = 1 0 0... sponse when fi is present. Therefore, the faulty output and c (R) = c (Ro) so S is not a TC test for the single response is not Ro. U fault fj. A similar argument holds if u is followed by a Corollary 1: No single fault can change any output pair of e-tests. Hence, the length of a TC test for Gn is function in an irredundant multioutput combinational at least n + 2. network N from z to z. We now show that S* is a TC test for Gn. Let Ro be It is believed that Lemma 1 also holds for multiple the correct response to S*. We have faults, although a rigorous proof of this has not been found. Corollary 1 cannot, however, be extended to mulS*= u e1e2 en_lenel, tiple faults when N has more than one output. Consider Ro= l *--1 1 19 the circuit Nc in Fig. 4. This is an irredundant realization of Zc = (Zl,Z2,Z3), where Z2 = X2. If the triple fault and c(R*) = 1. There are three cases to consider. F comprising lines a, b, and c all s-a-1 is present, Z2 Case 1: u fails. In this case the output of Gn is effecchanges to x2. This is due to the fact that much of Nc is tively s-a-1, hence, c(R*) = 0 c (R*). c redundant with respect to Z2, although the circuit as a Case 2: u passes and all e-tests fail, i.e., the output of Gn is effectively s-a-0. Again the faulty response R* is whole is not redundant. F cannot be detected by using Z2 as a test point for monitoring TC's; however, F is TC such that c(R*) = c(Ro). Case 3: u passes and j e-tests fail where 1 < j < n -1. detectable if the output z1 of Nc is used as a test point. Theorem 2: Let T be any (possibly minimal) singleThis is the case where j inputs of Gn are s-a-1. Some fault test set for an irredundant single-output combinatest ei passes and some test ek- fails. If e1 fails then the tional circuit N. Let Tr (T1) be all tests in T producing result is output 0 (1) respectively from N. Construct a test seS* = u ele2 ei ... enel, quence S* = tlt2---tm with the following properties. Property 1: S* contains every member of T. R* = O O d .. I ...* dnO, * Property 2: S* is an alternating sequence of tests where di C 10, 1. Clearly c(R*) > 2. If e1 passes, then we from TO and T1. t1 E T0, if I Tj > IT'l, otherwise t Chave T. If ti C Td, then ti+l C Tc for 1 < i < m - 1. S* is a single-fault TC test for N. S* = u e1e2 ek enel, Proof: The correct response Ro to S* is an alternatR * = 0 1d2 ---0 dn 1, ing sequence of O's and l's. R4 has the maximum possi1

and c(R*).> 3. Thus, in all cases c(R*) # c(R ), so SF is a TC test for Gn which is minimal with respect to both

.2
2

10

18

..

...

...

...

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617

x1

x3

x2

x3

X2-

I xIxz~~~~~~~~~~~~

N. The following lemma is a stronger version of Lemma 1 for two-level circuits. Lemma 2: Let T be any test set for a two-level circuit N. Let Ro denote the fault-free response of N to any sequence S containing every member of T. No single or multiple fault can change the response of N to S from

Fig. 3. Network NB realizing ZB = XlX2X3 + lx2xt3

xI

RotoRo.

x1

x2
x2

Fig. 4. Irredundant network NC in which plement Z2.

multiple fault can

com-

ble TC, m - 1, for a sequence of length m. The only other sequence with the same TC as Ro is Ro. In order for Ro to be a faulty response all tests in T must fail which is impossible by Lemma 1. Hence, S* is a singlefault TC test for N. Corollary 2: Let T = rT0,T11 be a minimal single-fault test set for N. Then N has a single-fault TC test of length p < 2 max {l TI, T1I I < 2(171 -1). Corollary 3: Let D be the absolute value of the difference between TI and T'j in a minimal single-fault test set T = IT0,T1} for N. If D < 1, S* is a minimal single fault TC test for N. Theorem 2 proves that every single fault in a singleoutput combinational circuit is TC detectable using less than twice the number of tests required for conventional testing. When D > 1, the TC test S* defined in Theorem 2 may be nonoptimal. The problem of finding a minimal or near-minimal TC test sequence for an arbitrary combinational network N is not easy; it appears to be at least as difficult as the corresponding problem of finding a minimal test set for N. In the following section this problem is examined for the restricted but important class of two-level combinational networks.

'

Proof: Let TO (T') be the subset of T producing output 0 (1). TX > 1 and Tll > 1. If Ro changes to Ro all tests in T' must fail. A failure of one of these tests implies that one or more input lines of the output (NAND) gate Go are effectively s-a-1, or, in functional terms, one or more prime implicants of the function realized by N have "disappeared." The failure of all tests in T1 implies that all inputs to Go are effectively s-a-1 which in turn implies that the output of N is effectively s-a-0. Hence, the responses to S must be all O's which is a contradiction. Theorem 3: Let T = Itlytt, t,t ,t -...,tlJ be a (not necessarily minimal) set of r tests for a two-level circuit N. Then the sequence S* = t] t1 t2 tq _It qtptlt ...* to_ lto of length r + 2 is a TC test for N with respect to both single and multiple faults. Proof: The fault-free response to S* is Ro: Ro=111 l... 1000...0 0, and c(Ro) = 1. We consider 4 cases. Case 1: All tests in T1 fail. Then, as argued in the proof of Lemma 2, the output of N is effectively s-a-0 hence, the response R to S* is a sequence of O's and c(R) = 0. Case 2: All tests in TO fail. Then all tests in T1 must pass, so R is a sequence of l's and again c(R) = 0. Case 3: Some t' C T1 fails and some tJ C T' passes. If t' (a repeated test in S*) fails, then
l S*= t ... ... t,11ttt ... to R =0 d...1.--d Odd...d,

and c(R) > 2. If t 1 passes, then

S* = titi ti ti_l1t0t0o *t, d... R =1 d * * 0... d Idd d
... ...
..

IV. FAULT DETECTION iNI Two-LEVEL CIRCUITS Every combinational function can be realized by a two-level circuit. For simplicity we will only consider sum-of-products realizations such as that shown in Fig. 3; our results can be immediately extended to productof-sums realizations by applying the Duality Principle. Let T be any single-fault test set for a two-level network N. We can partition T into two sets: TO = consisting of the tests jt,t,---,t} and T1 = { producing response 0 and 1, respectively. It has been shown [2] that T also detects all multiple faults in N, hence, we can refer to T unambiguously as a test set for

and again c(R)( 2. Case 4: Some t C TO fails and some to E TO passes. The argument of the preceding case again implies that U c(R) 2. Hence, in all cases c(R) $ c(Ro). Theorem 4: Let T = 1T0,TP) be a minimal set of r tests for a two-level circuit N. Let m be the length of a minimal multiple-fault TC test for N. Let D be the absolute value of 1 - T1l. a) IfD1<,thenm=r.

b) IfD>1,thenr.m<r+2. Proof. For D < 1, the TC test of length r defined in

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Theorem 2 is a minimal single and multiple fault TC test for N. For D > 1, Theorem 3 defines a multiplefault TC test of length r + 2. Thus a TC test for a two-level circuit N requires at most 2 more test patterns than are needed for conventional testing. Theorem 4 also implies that provided D < 1, there is a minimal single-fault TC test for N that also detects all multiple faults. It might be expected that every single-fault TC test for a two-level circuit has this property; we now show that that is not the case. Consider the two-level circuit ND in Fig. 5 which realizes the function ZD = X1X2X3X4 + X1X2X4. Let t1d denote the input pattern to ND representing the binary number i and producing output d. (For example, to denotes the test (X1,X2,X3,X4) = (1,1,0,1) which produces output 0.) The test set T = It2,t7,to1,tl3,tl4,t3,tlt5 is a complete and minimal set of tests for ND. Let
S=t t 73t? 15tllttl4t?ll;

x1
X2
x3 x4

x4

x2
Fig. 5. Two-level circuit ND.

xI

ZD

therefore

Ro = 0 1 0 1 0 0 0 0. It can be shown, e.g., by enumeration, that S is a TC test for each of the 20 possible single faults in ND. Consider the double fault F = "lines a and b s-a-i." This fault is detected by to and t15 and the resulting response
to S is R = 0 1 0 0 0 1 0 0, so that c(Ro) = c(R) = 4 and S is not a TC test for F. Thus, the theorem [2] demonstrating the equivalence of single- and multiple-fault test sets for two-level circuits cannot be extended to TC tests.
V. FAULT LOCATION BY TRANSITION COUNTING We now turn to the problem of using TC tests for fault location (fault diagnosis). S is termed a single (multiple) fault TC location test for N, if S distinguishes all TC distinguishable single (multiple) stuckline faults in N. As noted earlier, the number of TC distinguishable faults is less than the number of faults that are distinguishable by conventional testing. Thus, the fault resolution obtainable by TC testing is inherently less than that obtainable by conventional testing. In order to distinguish m TC distinguishable faults and the fault-free condition, a TC location test of length m + 1 or greater is needed. Using conventional testing, [log2 (m + 1)] is a lower bound on test length, hence it can be expected that fault location by transition counting will require substantially more test patterns. To illustrate this problem we consider the derivation of TC location tests for an n-input NAND gate Gn, where n > 2. The numbers of distinguishable single and multiple fault classes associated with Gn are n + 2 and 2n, respectively [1]. Using TC testing, the number of distinguishable single-fault classes reduces to n + 1 since the faults "output s-a-0" and "output s-a-i" are not TC distinguishable. Similarly the number of multi-

ple-fault classes reduces to 2n - 1. Thus, while n + 1 tests suffice for multiple-fault location in Gn using conventional testing, at least 2n tests are needed using transition counting. Consider first the problem of single-fault location in Gn. Let s (n) be the length of a minimal single-fault TC location test for Gn. Clearly for n > 2, s(n) > n + 2. It can readily he verified that the sequences S2 = eje2eju and S3 = ele2elue3 are minimal TC location tests of length n + 2 for n = 2 and 3, respectively. For n = 4, however, a TC location test of length n + 3 such as S4 = e4eie2eie2ue3 is required. There does not seem to be a simple relationship between s(n) and n. The following theorem provides a lower bound on s(n) which is greater than the lower bound n + 2 for n > 6. Let Lx] denote the greatest integer less than or equal to x. Theorem 5: If s (n) is the minimum length of a singlefault TC location test for Gn, then

s(n)

> ([4J + 1) (n - 2L4) + 1.

Gn. Let ki be the number of occurrences of the test pattern ei in Gi for i = 1,2,...,n. Obviously, ki > 1. Let fi denote the single-fault "input line xi s-a-1." This fault can only be detected by ei. If S is applied to Gn with fi
the TC of R. Hence, Di = c(Ro) equality
-

Proof: Let S be any single-fault TC location test for

present, then the observed response R differs from the correct response Ro in precisely ki bits. Each incorrect

response bit can cause a change of di E f-2,-1,0,1,21 in

c(R) obeys the in-

-2ki < Di

<

2ki.

(1)

In other words, fi can cause the TC of the response to S to increase or decrease by at most 2ki. The inequality (1) implies that, for S to distinguish all single faults in Gn, there can be at most 4 e-tests, say el,e2,e3,e4 such that ki = 1. If in addition k5 = 1, then D5 = Di for some i in the range 1 S i < 4. This implies that f5 is indistinguishable from fi, or else D5 = 0 which means that fi is not TC detectable. Thus, k5 > 2. In the same way it follows that there can be at most 4 e-tests say e5,e6,e5,e8 such that ki = 2, and so on. Hence, it follows that the number of e-tests in S is at least

HAYES: TC TESTING OF COMBINATIONAL LOGIC CIRCUITS

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Now Dj can be represented by the n-bit binary number rFj = an-lan_-2"aO, where, for 1 < i < n, ai-, = 1 if xi s-a-1 is a fault in Fj, and ai-i = 0 otherwise. Hence, for each distinct multiple fault Fj on the input lines of Gn, In addition to e -tests, S must contain at least one occur- there is a distinct (binary) number rF,. Each Fj derence of u. Adding 1 to (2) to account for u yields the recreases c (Ro) by a unique amount; hence all faults in Gn * quired lower bound on s(n). can be distinguished by S*. Corollary 4: s(n) > n2/8 + 1. Theorems 6 and 7 show how a fault location test set T We now present a general method for constructing a for a gate can be used to construct a TC location test. single-fault TC location test for Gn, where n > 3. This is analogous to the approach used for generating Theorem 6: Let S* = S1S2-*-Sr be a sequence of r e- TC detection tests in the preceding sections. The probtests and u-tests for Gn constructed as follows. lem of finding a TC location test S for an arbitrary com1) S* contains one copy of u and en and i copies of binational circuit using a given location test set T is ineach ei for 1 < i < n -1. teresting from a theoretical point of view. It can be 2) No occurrence of ei is immediately preceded or shown that if 171 = m, ISI < m22m2+1. In general, it apfollowed by ei for 1 < i < n. pears that such tests are far too long to be of practical 3) s1s2S3 = enuen-I and Sr = en-li value. A better method of fault location is to apply a seS* is a single-fault TC location test for Gn of length ries of relatively short TC tests and observe the TC's at n(n + 1)/2 + 2. several different test points. Test points can be selected Proof: Let fi = "input line i of Gn s-a-i" which is systematically using a standard signal-tracing approach. detected by ei only. Let Ro denote the correct response Suppose incorrect TC's are observed at k distinct test 1 1 to S*, so thatc(R*) = 2. sequence 1 0 11 points of N when a single fault f is present in N. Let If fn is present the observed response is R = 0 0 1 1 Nl,N2,-..,Nk denote the subnetworks of N that feed the 1 1 with TC c(R) = 1. If &-i is present, c(R) = 2n - 2. k test points in question. The fault f must be located in If any fJ where 1 < i < n - 2 is present, then c(R) = 2i the intersection of Nl,N2,...,Nk. + 1. Finally, a single-fault causing the output of Gn to be s-a-O/1 changes c(R) to 0. Hence, all n + 1 TC distinVI. DISCUSSION guishable single faults result in different values of c(R) The main conclusions that can be drawn from the and so are distinguished by S*. The length r of S* is previous sections are as follows. n-1 1) Most, but not all, faults that can be detected or L distinguished by conventional testing can also be deLi+2=n(n-1)/2+2. i=l tected or distinguished by TC testing. 2) Combinational networks can be TC tested for the = 6. Then a possible To illustrate Theorem 6, let n presence of stuck-type faults with a relatively small inTC location test for G6 is crease in the number of tests needed for conventional testing. = e6ue5e4e3e2ele5e4e3e2e5e4e3e5e4e5. S6 3) A test set T derived using conventional test gener= 17, whereas the lower bound on s (6) given by ation methods forms a convenient source of test patSj terns for the construction of TC tests. Theorem 8 is 9. The length of S* in Theorem 6 is n2/2 4) Very simple rules, e.g., alternate members of TO n/2 + 2 which is less than 4(n2/8 + 1). Hence, by Corollary 4, IS*] is less than 4 times the length of an optimal and T1, can be used to construct efficient TC tests. 5) The fixed test sequences frequently used in comTC test for Gn. As noted earlier at least 2n test patterns are needed in mercial TC testers cannot provide complete fault deteca multiple-fault TC location test for Gn. We now tion in all cases. 6) A TC test must be extremely long in order to propresent a procedure for constructing such a test whose vide significant fault location data, unless multiple test length is less than twice the optimum value. Theorem 7: For i = 1,2,-...n define Si = ueiuei..uei, points are used. where Si is an alternating sequence of u's and ei's and The results presented here illustrate the utility of = 2i. The sequence S* = S1S2...SSn is a multipleRule 1 given in Section II. For example, the TC tests deISil fault TC location test for Gn of length 2n+1 - 2. fined in Theorems 1 and 3 have c (R) = 1, where zero is Proof: The only multiple faults that need be con- the minimum possible value of c(RO), while for the TC sidered are those comprising s-a-1 input lines to the tests in Theorems 2 and 7, c (RO) has the maximum pos(NAND) gate G,. Let Fj be such a fault involving input sible value. The generation of TC tests for a combinational cirlines xb,x2.--.,x If S* is applied to Gn with Fj present, cuit is basically a sequential process. As such it has then the output TC c (Ro) is decreased by
which simplifies to

j+ (l 1

L41)

t Dj = k=1 2k-1

(1+1l)n-2 L1

...

IEEE TRANSACTIONS ON COMPUTERS, VOL. c-25, NO. 6, JUNE 1976

some similarities with conventional test generation for REFERENCES sequential circuits. For example, the order in which the [1] J. P. Hayes, "A NAND model for fault diagnosis in combinational logic networks," IEEE Trans. Comput., vol. C-20, pp. 1496-1506, tests are applied is important, and some test patterns Dec. 1971. may be repeated. [2] D. R. Schertz and G. Metze, "A new representation for faults in The design of TC tests for sequential circuits appears combinational digital circuits," IEEE Trans. Comput., vol. C-21, pp. 858-866, Aug. to be quite difficult. Let S be a TC test for a sequential [3] B. Elspas and R. 1972.Short, "A bound on the run measure of A. switching functions," IEEE Trans. Electron. Comput., vol. ECmachine M whose fault-free response is Ro. Ro must 13, usually contain many different subsequences such as [4] R. pp. 1-4, Feb. 1964. W. Watson, Timesharing System Design Concepts. New York: McGraw-Hill, 1970. state distinguishing sequences and homing sequences that aid in identifying the behavior of the circuit being tested. This structural variety in Ro tends to make c(Ro) take middle-of-the range values, implying the possibility of many faulty machines with the same transition John P. Hayes (S'67-M'70) was born in Newcount as M, cf. Rule 1. bridge, Ireland, on March 3, 1944. He received the B.E. degree from the National University The generation of transition counts can be viewed as of Ireland, Dublin, in 1965 and the M.S. and a technique for encoding test results. It is a type of cod.g| | l< Ph.D. degrees from the University of Illinois, ing that is easily implemented in a tester and results in Urbana, in 1967 and 1970, respectively, all in electrical engineering. a logarithmic compression of the test response data. From 1965 to 1967 he was with the Digital There are some similar coding schemes which may also Computer Laboratory, University of Illinois, be useful for testing logic circuits, and which merit furwhere he participated in the design of the IIliac 3 computer. In 1967 he joined ther investigation. For example, by finding the length of ing Systems Group -at the Coordinated Science Laboratory,the Switchthe longest sequence consisting of all l's or all O's in a of Illinois, where he worked in the area of fault diagnosisUniversity of digital response sequence R, we can determine a "run count" systems. From 1970 to 1972 he was a member of the Operations Rer(R) for R, cf., the definition of run measure in [3]. Like search Group at the Shell Benelux Computing Centre, Royal Dutch/ Hague, The Netherlands, where he was involved c(R), r(R) is very easy to compute. Both c(R) and r(R) Shell Company, The mathematical programming techniques and softin the application of can have m = IRI distinct values, since 0 < c(R) < m - ware development. Since 1972 he has been Assistant Professor of 1 and 1 < r(R) < m. Transition counting is also related Electrical Engineering and Computer Science at the University of research interests into the concept of the check sum, a widely used tech- Southern California, Los Angeles. His current automation, and comclude switching theory and logic design, design nique for detecting errors in data tables [4]. puter architecture.

A Logic System for Fault Test Generation

SHELDON B. AKERS, JR., FELLOW, IEEE
Abstract-This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. As a result of this logic propaggtion, the necessary values of the elements in the network become much more precisely (if not completely) defined. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. If several different tests will suffice, the choices remaining are clearly indicated. In the case of a redundant lead (untestable fault), propagation through the tables automatically results in a logical inconsistency.

The system is sufficiently general to permit its incorporation into almost any of the many fault test generation procedures. Several examples are included.
Index Terms-Fault diagnosis, fault test generation, logic networks, logic systems, stuck-at faults.

I. INTRODUCTION FAULT test generation is a complicated process. One Fmust continually make decisions about how the elements of a network behave not only when a fault is present but also when it is absent. As various logical decisions are made, their effects must not only be propagated forward in the network but often backward as Manuscript received July 9, 1975; revised December 10, 1975. The author is with the Electronics Laboratory, General Electric well. Decisions that seem straightforward when made suddenly result in logical inconsistencies several steps Company, Syracuse, NY 13201.