10.

Architectures for Low Power Ultra-Wideband Radio Receivers in the 3.1-5GHz Band for Data Rates < 10Mbps
Marian Verhelst*, Wim Vereecken**, Michiel Steyaert and Wim Dehaene
Katholieke Universiteit Leuven Dept. Elektrotechniek, afd. ESAT-MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium

mverhels@esat.kuleuven.ac.be
*M. Verhelst is Research Assistant of the Fund for Scientic Research - Flanders (Belgium)(FWO-Vlaanderen) **W. Vereecken is Research Assistant of the IWT Belgium

ABSTRACT
This paper compares dierent receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one. Categories and Subject Descriptors: B.4.1 [INPUT/OUTPUT AND DATA COMMUNICATIONS]: Data Communications Devices Receivers General Terms: Performance, Design. Keywords: Ultra-Wideband, Receiver, Architectures.

tems). In the past years a lot of research has been done on transceiver architectures in the lower frequency band. Almost always a fully digital architecture, which implies exibility, scalability and (in this case) low power, was suggested for these frequencies [9] [15]. Only recently research started exploring the 3.1-10.6GHz band. The question is however whether the fully digital architecture, which seemed optimal for the lower frequency band, can be reused in the higher frequency band? The following paragraphs will prove that, unlike in the 0-960MHz band [9], it is not necessarily true that: the more the operations are carried out in the digital domain, the less power will be consumed. To be able to make a fair comparison between the dierent architectures, some parameters have to be xed. In the following of this paper, we will assume a pulse rate of 100Mpulses/s, an ideal channel, components with ideal noise gures, 1 user and only AWG (additive white Gaussian) noise. These are rst order parameters that allow us to do a quick, but reliable comparison between dierent architectures. The pulse rate of 100Mpulses/s reveals that this paper does not aim high speed UWB receivers. The focus is on low power and exibility and data rates up to no more than 10Mbit/s are targeted. Because of the high interference by WLAN in the 5-6GHz band, the authors choose to use only the 3.1-5GHz frequency band. Figure 4 (left) shows the used pulse form in time and frequency domain. It is modeled by a raised cosine with roll-o factor = 1. We will not utilize pulse position modulation (PPM) to encode the binary information onto the pulses. Instead pulse amplitude modulation (PAM) is used: The waveform plotted in gure 4 (left) represents a logical 1, the negative of this waveform represents a logical 0. A pseudo random sequence will be used for channelization and BER improvement purposes [14].

1.

INTRODUCTION

Wireless communication has never been so popular as it is now. The frequency spectrum is used intensively and bandwidth available for new wireless communication techniques becomes very scarce. The ultra-wideband (UWB) impulse radio technology [16], recently approved by the FCC [7], addresses this problem. This technology is based on transmitting ultrashort (< 1ns) pulses. The energy of these pulses is spread out over a large bandwidth (typically a few GHz) and can therefore be transmitted in already allocated frequency bands, below the noise oor of the other users and without disturbing them. UWB has many advantages compared to other, narrowband, communication techniques, such as robustness against jamming and multipath fading, low probability of detection and high user-capacity. The FCC allows the deployment of UWB in two separate frequency bands: the 0-960MHz band (for imaging applications) and the 3.1-10.6GHz (i.o. for communication sys-

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2. FULLY DIGITAL IMPULSE RADIO RECEIVER 2.1 Architecture and working principle
Figure 1 shows the main components of the fully digital architecture. This architecture resembles very much the baseband architecture, described in [9], with some adjustments to be able to use it in the 3.1-5GHz band.

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@ 10GHz low pass filter 05GHz ADC

@10GHz MF correlator bank

@100MHz PN correlator bank

data recovery

peak detector

CONTROL

TIMING

fectly. Placing an ADC in front of the receiver will add quantization noise. Under the assumption of a Gaussian input signal, analytical computations determined the loss to be 1.25dB for a 2 bit ADC and 2.3dB for a 1 bit ADC. The graphs of gure 2 conrm these numbers.
10
0

Figure 1: Architecture of the fully digital receiver, the numbers above the correlator blocks are the input data rates of these blocks
BER out

10

During normal operation (data reception) data enters the receiver through the broadband antenna, is ltered and afterwards sampled at the Nyquist rate, 10GHz. In the digital domain, a matched lter (MF) bank will correlate the data with the (5 bit) pulse form coecients, stored locally. This matched lter transforms every group of 100 input samples (one pulse period) into one correlation value. As a result the speed degrades by a factor 100 and the matched lter outputs a 100MHz (pulse rate) signal. Because UWB pulses are sent with very low power, the SNR at the outcome of these MF correlators is too low and needs further improvement. Therefore an extra scrambling of the pulses with a pseudo noise (PN) sequence of length Npn is done at the transmitter side. In this way every pulse is replaced by a sequence of Npn pulses. Descrambling these pulses in the receiver by correlating them with the same PN sequence, will increase the SNR by a factor Npn (cfr. DSSS techniques [14]). Timing errors, due to clock oset, are detected by early/latetracking. This is done by correlating the data with slightly (e.g. half of a sample) shifted versions of the pulse template. As a result, during normal operation, 3 MF and 3 PN correlators are always running in parallel. Figure 2 shows the (in Simulink) simulated bit error rate E (BER) at the output of this receiver vs. input pulse for N0 dierent ADCs at the entrance of the digital part. The simulation uses 2-PAM to modulate the data on the pulses and a PN sequence length Npn = 15. Only AWG-noise is considered. Theoretical analysis conrms these simulation results. Processing gain is achieved through two mechanisms: matched ltering and descrambling by PN correlation. The matched lter correlation takes advantage of the low duty cycle of the signal and provides a gain factor [14] 2 Tpulse Win = 2 10e 9 5e9 = 100 = 20dB. (1)

10

10

10

1 bit ADC 2 bit ADC no quantization theoretical 2PAM: Q(sqrt(2Eb/N0)) 35 30 25 20 15 Epulse/N0 in 10 5

Figure 2: Performance of the fully digital receiver with 2-PAM, Npn = 15, simulated 5000 bits

2.2 Drawbacks of the fully digital architecture at 3.1-5GHz

The major drawback when using this architecture in the 3.1-5GHz band is its power consumption. This power consumption will be dominated by the ADC and the matched ltering block in the digital domain. The ADC has to work at the Nyquist frequency, 10GHz, and although its resolution can be very low (e.g. 1 bit), this component will still weigh heavily on the power budget of the receiver. Besides this, the digital logic close to the ADC, the matched lter correlator bank, will also have to work at a very high frequency: Data enters this block at 10GHz, which implies very fast clocking registers. The correlation operation itself has to be executed at 10GHz (sample rate) when the correlation is done fully serial. The speed can be lowered at the expense of more parallelism. Nevertheless this is a second source of huge power consumption. Paragraph 5 will treat the power consumption of this architecture more thoroughly.

2.3 Conclusions
At a rst glance this architecture does not seem to be ideal at all to be used in the 3.1-5GHz band for UWB communication. Next paragraph will introduce some important adjustments to this architecture to get rid of the drawbacks discussed above. From these, one solution will be chosen and worked out in more detail. This allows us to compare our choice of architecture with the fully digital architecture and see whether the changes result in an improvement.

Secondly the PN correlation combines Npn pulses to recover one bit. This results in an extra processing gain by a factor Npn . With this information, it is possible to compute the output Eb /N0 and from this the theoretical 2-PAM under bound for this architecture: r Eb BER = Q( 2 in ), N0 = Q( 2SNRout Rout Wout ), p (2) = Q( 2SNRin Npn Tpulse Win ), with Tpulse the pulse repetition interval, in the receiver input and out the receiver output. Figure 2 shows this bound. As expected, the result of the simulation without an ADC in front of the receiver follows this theoretical bound per-

3. ALTERNATIVE ARCHITECTURES
This section will shortly introduce four possible alternatives for the fully digital architecture and select the most promising alternative among them. 1. Channelized ADC: 10GS/s ADCs are very hard to make and consume very much power. A way to avoid

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this is to use a channelized ADC [13]. These are parallel ADC architectures, with each ADC operating at a fraction of the eective sampling frequency. Channelization can be employed in the time or frequency domain. However, both techniques suer from large problems. Channelization in time still requires ADCs which are able to handle the full bandwidth (5GHz), which causes diculties in the design of the sample/hold circuit. Channelization in frequency on the other hand needs several broadband mixers and lters with sharp roll-os in the analog domain. Besides this, a very accurate clock is necessary to accommodate the dierent channels next to each other. Figure 3(a) shows the resulting architecture when employing frequency domain channelization. This ADC technique is the subject of ongoing research [12]. 2. Down conversion before ADC: [6] suggests to do a quadrature down conversion in the analog domain before sampling the I and Q branch at Nyquist rate (Figure 3(b)). In this case it means converting the 3.1-5GHz band to 0.1-2GHz and then sample at 4GS/s. This solution however requires a QVCO and an extra mixer and ADC, while the ADC speed only degrades from 10GHz to 4GHz. Further research on this topic is still necessary, but at rst glance the decrease in speed and power of the ADC and MF block does not seem to compensate the extra power for the QVCO, the extra mixer and the extra ADC. 3. Subsampling ADC: A third solution (gure 3(c), [2]) abandons the down conversion and does only a bandpass ltering form 3 to 5GHz and a subsampling at 4GHz immediately afterwards. This operation will repeat the frequency contents of the 3-5GHz band and hence convert it to baseband. While the ADC speed is only reduced a little bit, a rather sharp analog bandpass lter is needed. And whats more, the complexity of the digital receiver part has grown intensively to be able deal with this subsampling (e.g. with a Hilbert transform). Further research will have to point out whether these problems can be solved. 4. Move operations to analog domain: The previous adjustments all tried to lower the ADC speed, without touching the digital domain. But they do not seem to be able to lower this speed drastically. To reach this, a totally dierent approach will have to be used. This fourth adjustment (gure 3(d)) will try to move the MF correlation operation to the analog domain. This reduces the specications of the ADC a lot. Since the data rate after the MF operation is equal to the pulse rate, the ADC sampling rate will only be 100MS/s. This is a reduction with a factor 100! Of course this architecture also introduces some new problems. Paragraph 4 will handle it thoroughly. Most of the solutions given above do not seem to solve the problem of the high speed ADC and matched lter block completely. The last one (gure 3(d)) however looks very promising. Next paragraphs reveal whether this architecture really oers a feasible solution. Finally, in paragraph 5, the two architectures of gure 1 and gure 3(d) will be compared against each other.

@10GHz/M

@10GHz MF correlator bank

@100MHz PN correlator bank

data recovery

low pass filter

band pass filter f2 band pass filter fM

ADC

peak detector

...

ADC

...

CONTROL

TIMING

ADC

(a) Channelized ADC

@4GHz filter ADC filter filter ADC @4GHz QVCO @3GHz MF correlator bank @4GHz @100MHz PN correlator bank data recovery

peak detector

CONTROL

TIMING

(b) Down conversion before ADC

@ 4GHz band pass filter 35GHz ADC

@4GHz

@100MHz PN correlator bank

data recovery

MF correlator bank

peak detector

CONTROL

TIMING

(c) Subsampling ADC

@100MHz windowed integrator ADC

@100MHz PN correlator bank

data recovery

peak detector

VCO @4GHz

CONTROL

TIMING

(d) Move operations to analog domain Figure 3: Four alternative architectures, the numbers above the correlator blocks are the input data rates of these blocks

4. PARTIALLY ANALOG IMPULSE RADIO RECEIVER 4.1 Architecture and working principle
Moving the MF operation to the analog domain seems a stupid action. Generating the pulse template in this domain surely is very hard. In [11] it is suggested not to match with the pulse template itself, but with a windowed sine wave. The generation of a sine wave in the analog domain is very straightforward. Moreover when windowed, this sine wave resembles the pulse form very much. So the correlation with the pulse template is now substituted by a multiplication with a sine, followed by a windowed integration. Figure 4 compares the pulse template to the new analog matching form, the windowed sine wave (with a window length W L and frequency equal to the center frequency of the pulse).

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0.1 0.05 ampl ampl 0 0.5 0

10

10
WL 1

0.05 0.1 4
0

0.5

0 2 4 9 time [sec] x 10

0 2 4 9 time [sec] x 10

BER out

10

10 ampl [dB]

10
ampl [dB] 10
0

~1/WL

10

10

10

1 bit ADC 2 bit ADC no quantization theoretical 2PAM: Q(sqrt(2Eb/N0)) 35 30 25 20 15 Epulse/N0 in 10 5

4 6 freq [Hz]

8 x 10
9

4 6 freq [Hz]

8 x 10
9

Figure 4: Comparison of the pulse form, equal to the matching template in the fully digital receiver (left) and the analog matching form (right) in time and frequency domain

Figure 6: Performance of the partially analog receiver with 2-PAM, Npn = 15, 5000 bits simulated

The matched ltering template is designed aiming at a minimal eect of noise while maximizing the signal throughput. As a result, substituting this template by another will inevitably lead to a worse processing gain. The window length of the analog integrator is an important parameter in this. A very small window is good for rejecting noise, but will also reject a major part of the signal energy. With a too large window on the other hand, all signal energy will be captured, but also a lot of noise goes through, which also results in a bad SNR. Figure 5 shows the simulated processing gain of the analog matched lter in function of the integrator window length. Form this graph an optimal WL of 1.2ns can be derived. With this window the loss in processing gain compared to the real matched ltering is only approximately 0.5dB. Figure 3(d) shows the new architecture. So, during normal operation (data reception) the data is rst mixed with a sine wave. The result of this operation is windowed and nally

20 19

18 too little signal energy captured 17 16 15 14 0.5

too much noise energy captured

MF with sine template partially analog receiver perfect MF fully digital receiver 1.0 1.5 2.0 2.5 3.0 3.5 4.0

an integrator collects all energy captured in the window. The ADC samples the outcome of the integrator before the integrator resets again to be ready for the next pulse. Since only one sample per pulse period is taken, the ADC speed can be reduced to 100MS/s. Like in the fully digital receiver, the digital domain executes the PN decorrelation and takes care of data recovery and clock oset tracking. Clock oset is measured by early/late-tracking. To this purpose a second matched lter correlation is necessary. Figure 6 shows the simulated bit error rate (BER) at the E output of this receiver vs. input pulse for dierent ADCs N0 at the entrance of the digital part. The simulation uses 2PAM to modulate the data on the pulses, a window length of 1ns and a PN sequence length Npn = 15. Only AWGnoise is considered. The major dierence between the curves of gure 2 (paragraph 2.1) and gure 6 is an extra loss of approximately 0.8dB (see gure 5 for W L = 1ns) due to imperfect matched ltering with the sine template. The quantization loss on the other hand, is less than in the fully digital receiver. The outcome of the analog correlator, the input of the ADC, ideally is a large positive or negative correlation value and no value in between. Noise will of course trouble this, but because of the ltering in the analog domain, the SNR at the entrance of this ADC is already fairly high (approximately 20dB above the input SNR). The input signal of the ADC will hence not be uniform or Gaussian with zero mean at all. It will be (Gaussian) distributed around the positive and negative correlation value. As a result, the 2 bit and certainly the 1 bit quantizer will introduce less quantization noise and the receiver will perform better. This can also be seen in gure 6, where the quantization loss for the 1 bit ADC-curve is less than the theoretical 2.3dB (see paragraph 2.1). This eect becomes less apparent when the SNR decreases or the ADC resolution increases.

processing gain [dB]

WL of analog integrator [ns]

4.2 Drawbacks of the partially analog architecture

Most of the major drawbacks of the fully digital architecture have vanished by the transfer of the MF operation to the analog domain. Of course this also brought along some new problems. The most important one is the lower

Figure 5: Processing gain of the analog matched ltering operation (with sine template) in function of the window length (WL) of the windowed integrator

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exibility and scalability. In this partially analog receiver architecture it is e.g. not possible anymore to choose the form of the matching template and implementing a RAKEreceiver structure with multiple ngers becomes costly. For every extra nger, not only some digital blocks (as in the fully digital receiver), but also some of the analog components and the ADCs have to be copied. On the other hand, some other degrees of freedom arise. For example the integration window length can be increased to achieve a faster acquisition at the expense of a slightly worse performance. This trade-o is not possible in the fully digital architecture.

4.3 Conclusions
Together with a better power consumption, this architecture realizes a somewhat dierent exibility than the fully digital architecture. Next paragraph will compare both of them and explore which one is to be used in which circumstances.

Spice simulations (for adders and exors), it is possible to compute the power consumption for dierent values of the parameter M. The result can be seen in gure 7(under). For M = 1, fully serial implementation, the power consumption is very high due to the high clocking speed (10GHz) in several components. For M = 100, fully parallel, the power will also be high because of the multiple exors and adders working in parallel and the large input buer. Taking into account that M has to divide 100, M = 20 seems to be optimal. For this value of M one matched lter correlator consumes 273mW. A VCO for this architecture can be taken from [10] and consumes 11mW.
(M1)bit shift register 5bit 5bit exor exor pulse coeff register file 100*5 bits speed = 10GHz/M
power consumption MFblock [Watt]
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 20 40 60 80 100

speed = 10GHz M 5bit exors M 12bit adder speed = 10GHz/M 12bit register speed = 10GHz/M

... ...

5bit exor

+ +

5.

COMPARISON OF THE TWO RECEIVERS IN TERMS OF POWER EFFICIENCY

Suppose a bit error rate of 1e5 is targeted. The input is -10dB. We can reach this goal by a fully digital architecture or with the partially analog architecture. Since both architectures encounter dierent losses, they need a dierent Npn to be able to compensate them and reach the conned goals. Table 1 shows the necessary Npn . The power consumption of every option can now be estimated.
Epulse N0

Table 1: Necessary Npn to reach BER 1e5 with the dierent architectures Architecture fully digital 1 bit ADC fully digital 2 bit ADC partially analog 1 bit ADC partially analog 2 bit ADC Npn 170 122 174 137

degree of parallellism, M

Figure 7: The architecture of the matched lter block in the fully digital receiver (top) and its power consumption in function of the implemented parallelism M (under)

Partially analog architecture Fully digital architecture

We will only consider this receiver with a 1 bit ADC in front. 2 and more bits ADCs at this high speed exist ([3], [5]) but consume several Watts, which is unacceptable. A one bit ADC includes a high speed buer, a 10GS/s sample-andhold circuit and a fast comparator. Based on [5] a power consumption of 290mW can be derived for the ADC (100mW for the buer, 110mW for a 10GHz S/H and 80mW for the comparator). The power consumption of the digital part can in a rst order estimation be presumed equal to the power consumption of a 100MHz DSP processor. The ARM926EJS (0.18m process) consumes 140mW when running at this speed [1]. The timing, control and PN correlation operations can all be assumed to be executed on this DSP. The matched ltering can however not run on this platform, since this would require a too high processor speed and hence power consumption. The matched ltering operation will be a kind of digital front-end, that transforms the high speed data to 100MHz baseband signals and so lowers the DSP input speed. Figure 7(top) shows the architecture of this block. The degree of parallelism in the implementation, M, has to be exploited to reach a minimal power consumption for the block. Based on [8] (high speed M/S-ipop) and Here 1, 2 or more bit ADCs are all possible. For the comparison a 2 bit ADC will be used. The power consumption of such ADC (2 bit, 100MS/s) can from [4] be estimated at 15mW. Also in this architecture the power consumption of the digital part can be represented by the power consumption of the ARM processor. We do not need separate matched lter correlators anymore, since this operation is executed in the analog domain. The power consumption of the broadband mixers and broadband windowed integrators are simulated in-house. Table 2 summarizes the power consumption in the dierent parts of these receivers. They both reach the same BER for the same input Epulse /N0 , but with a dierent data rate, since the number of pulses per bit (Npn ) is different The table shows that the digital receiver consumes much more power than the partially analog one, and this for a lower data rate. As a result, the last line of the table reveals an almost 7 times lower power consumption per received data bit. The partially analog receiver clearly outperforms the fully digital one for the chosen parameters: Epulse = 10dB, BER = 1e5. But is this also true for N0 other values of these parameters?

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Changing the input pulse will not result in a dierent conN0 clusion. The power consumption of both receivers is very insensible to a change in Npn and for both receivers data rate 1 Npn Epulse N0 (3)

(for a constant BER.) As a result, the power consumption N0 per bit of each of them will be linear with Epulse and the relative dierence between them will not change. Also a change in the required BER does not have an inuence on the relative power consumption of the two receiver architectures. Again both receivers encounter the same dependencies: data rate 1 Npn 1 (Q1 (BER))2 (4)

the ADC will be approximately three times lower. However, the superiority of the partially analog to the fully digital receiver in terms of power consumption per received bit is so huge that our conclusion will not change by assuming smarter implementations or more detailed calculations. Finally, it is important to mention that our calculations do not take into account exibility. From previous paragraphs it is clear that certain degrees of freedom have vanished by the transfer of the matched ltering to the analog domain, but on the other hand, some new exibility parameters arose. Our future research will concentrate on solving the problems caused by this decrease in exibility and at the same time explore the new degrees of freedom.

6. CONCLUSIONS
This paper focuses on two very dierent UWB receiver architectures for impulse radio communication in the 3.15GHz band. In the rst one almost all operations are executed in the digital domain, while in the second one the matched ltering is carried out in the analog domain. Advantages and drawbacks of both architectures are discussed and they are compared against each other. The partially analog receiver turned out to perform remarkably better in terms of power consumption per received bit.

Figure 8 shows the power consumption per received bit for E dierent pulse (left), resp. required BER (right). Both N0 graphs reveal a constant 85% improvement for the partially analog receiver compared to the fully digital receiver.
power consumption/bit [W/bit]
power consumption/bit [W/bit]
7 6 5 4 3 2 1 15 10 5 0 x 10
6

fully digital receiver partially analog receiver

5 4 3 2 1

x 10

fully digital receiver partially analog receiver

7. REFERENCES
10 required BER
5

Epulse/N0 in

0 10 10

10

N0 BER ( Epulse = 10dB) (right) for fully digital and partially analog receivers

Figure 8: The power consumption per received bit vs. input E N0 (BER = 1e5) (left), resp. required
pulse

Previous computations and conclusions rely on the numbers given in table 2. These are rough power estimations based on one possible implementation of the two receivers. Other implementations or more detailed calculations can change these power gures. The fully digital receiver can e.g. be implemented so that the ADC only samples the relevant portion of the pulse period, where the pulse is located, and is switched o otherwise. Hence the power consumption of this block and of the matched lter correlator bank following

Table 2: Power consumption of the most consuming components of the fully digital and partially analog receiver Component VCO mixers 2GHz integrators ADC MF correlators other digital logic Total power cons. Data Rate Power cons./bit fully digital 11mW / / 290mW 3*273mW 140mW 1260mW 588kbps 2143nW/bit part. analog 17mW 23mW 2*8mW 2*15mW / 140mW 226mW 730kbps 310nW/bit

[1] ARM. ARM926EJ-S. www.arm.com/products/CPUs/ARM926EJS.html. [2] M. Chen and R. Broderson. A Subsampling Radio Architecture for 3-10 GHz UWB. BWRC Retreat, June 13, 2003. bwrc.eecs.berkeley.edu/Research/UWB/publications/ mchen_retreat03_talk_po.ppt. [3] D. Deschans et al. A 4-Gsample/s, 2-bit SiGe Digitizers for the ALMA Project. Paper II. ALMA Memo no. 426, 2002. [4] J. Vandenbussche et al. Systematic design of a 200MS/s 8bit interpolating/averaging A/D converter. In Design Automation Conference, volume 39, pages 449454, 2002. [5] K. Poulton et al. A 20GS/s 8b ADC with a 1MB Memory in 0.18m CMOS. In International Solid-State Circuits Conference 2003, 2003. paper 18.1. [6] R. Blazquez et al. Digital Architecture for an Ultra-Wideband Radio Receiver. In VTC Fall 03, Orlando, FA, October 2003. [7] FCC. First Report and Order. FCC 02-48, February 14, 2002. [8] Z. Gu and A. Thiede. 18 GHz low-power CMOS static frequency divider. Electronics Letters, 39:14331434, October 2003. [9] I. ODonnell, M. Chen, S. Wang and R. Brodersen. An Integrated, Low-Power, Ultra-Wideband Transceiver Architecture for Low-Rate, Indoor Wireless Systems. IEEE CAS Workshop on Wireless Communications and Networking, September 2002. [10] P. Kinget. A Fully Integrated 2.7V 0.35m CMOS VCO for 5GHz Wireless applications. In International Solid-State Circuits Conference 1998, pages 226227, February 1998. [11] S. Lee. Design and Analysis of Ultra-Wide Bandwidth Impulse Radio Receiver. PhD thesis, University of Southern California, May 2002. [12] W. Namgoong. A Channelized Digital Ultrawideband Receiver. In IEEE Transactions on Wireless Communications, volume 2, pages 502510, May 2003. [13] W. Namgoong. Channelized Digital Receivers for Impulse Radio. In IEEE International Conference on Communications 2003, volume 4, pages 28842888, 2003. [14] J. Proakis. Digital communications. McGraw Hill, New York, 4th edition, 2001. [15] M. Win and R. Scholtz. Comparisons of Analog and Digital Impulse Radio for Wireless Multiple-Access Communications. In IEEE International Conference on Communications: Towards the Knowledge Millennium, volume 1, pages 9195, 1997. [16] M. Win and R. Scholtz. Impulse radio: how it works. IEEE Communications Letters, 2(2):3638, February 1998.

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