8086 ARCHITECTURE

Intel 8086 microprocessor Architecture Signals Instruction Set Addressing Modes Assembler Directives Assembly Language Programming Procedures Macros Interrupts And Interrupt Service Routine BIOS function calls. I6 bit processor Available in 5,8,10MHz 20 bit address, 16 bit data. Memory size: 1Mb It requires +5V power supply. It can support up to 64K I/O ports. It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. Operates in single or multiprocessor configuration Single processor mode (minimum mode) Multiprocessor mode (maximum mode) 8086 signals are categorized in 3 groups Common signal for both modes Minimum mode signals Maximum mode signals It is a 40 pin IC The 8086 signals can be categorized in three groups. The signal having common functions in minimum as well as maximum mode. The signals which have special functions for minimum mode The signals having special functions for maximum mode

COMMON SIGNALS

GND: ground AD15-AD0: Multiplexed memory address and data lines. During T1 state : address is available T2,T3,TW&T4 state: data is available A19/S6,A18/S5,A17/S4,A16/S3: Multiplexed address & status lines. During T1 state: address lines for memory operation. During T2,T3,Tw,T4 state: status information is available S4&S3: Indicates which segment register is used for memory access. S6: Always low, S5: Status of interrupt enable flag bit is updated at each clock cycle.

BHE/S7- BUS HIGH ENABLE/STATUS Signal to indicate the transfer of data over the higher order (D15-D8) data bus. BHE=0, for data transfer over D15-D8, odd address memory bank. BHE =0, for read, write, and interrupt acknowledge cycle, whenever a byte is transferred on the higher byte of data bus during T1 cycle. S7= It is not currently used.

RD Read : This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the clock generator to provide ready input to the 8086. the signal is active high.

INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST : This input is examined by a WAIT instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.

CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. NMI: Non maskable interrupt positive going edge triggered, non maskable interrupt.

RESET: Terminates activity, clears PSW, IP, DS, SS, ES and the instruction queue and sets CS to FFFF. Processing begins at FFFF0 when signal is dropped. Signal must be 1 for at least 4 clk cycles. MN/MX: If high works in minimum mode If low works in maximum mode

Minimum mode signals

M/IO Memory/IO : This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle INTA Interrupt Acknowledge :

This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. ALE Address Latch Enable : This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. DT/R Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. DEN Data Enable : This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during hold acknowledge cycle. HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.

Maximum mode signals

S2, S1, S0 Status Lines : These are the status lines which reflect the type of operation, being carried out by the processor.

LOCK : This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. QS1, QS0 : Reflects the status of the instruction queue

RQ/GT0, RQ/GT1 Request/Grant : These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. RQ/GT0 has highest priority.

ARCHITECTURE

Architecture of 8086 is divided into two separate functional units - bus interface unit (BIU) - Execution unit (EU) These two units work simultaneously for instruction execution Two stage instruction pipeline. It can access 220 = 1Mb memory.

Bus interface unit (BIU) BIU contains - Bus interface logic - segment registers - memory addressing logic - 6 byte instruction object code queue. BIU performs all bus operations for the execution unit. It is responsible for executing all external bus cycles. When EU is busy in instruction execution, BIU continues fetching instructions from memory and stores in instruction queue. If EU executes an instruction, which transfers the control of the program to another location, then the BIU - resets the queue - fetches the instruction from the new address
9

- passes the instruction to the EU and - begins refilling the queue from the new location. This process is called pipeline flushing. Execution unit It contains - Instruction decoder - ALU - General purpose register - Pointers & Index registers - Flag register - Control circuitry. EU is responsible for - Execution of all instructions - Providing address to the BIU for fetching data/instruction - Manipulating various registers & flag register. OVERLAPPED FETCHING AND EXECUTION

10

8086 executes 3 instruction in lesser time and also completes fetching of 4th and 5th in in lesser time and also completes fetching of 4th and 5th instruction

11

Register set It has 14 sixteen bit registers. - Data register group (4 registers) - Segment register group (4 registers) - Pointer and index register group (4 reg) - Instruction register (program counter) - Flag register. The 8086/8088 Microprocessors: Registers

Registers Registers are in the CPU and are referred to by specific names Data registers Hold data for an operation to be performed There are 4 data registers (AX, BX, CX, DX) Address registers Hold the address of an instruction or data element Segment registers (CS, DS, ES, SS) Pointer registers (SP, BP, IP) Index registers (SI, DI) Status register Keeps the current status of the processor On an IBM PC the status register is called the FLAGS register In total there are fourteen 16-bit registers in an 8086/8088

12

13

Data registers

AX, BX, CX and DX are two bytes wide and each byte can be accessed separately AX register: Accumulator Register i/pt & o/pt operations pass data through AX or (AL) Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations Must also be used in I/O operations BX CX DX Base Register while computing data memory address. Also serves as an address register Used in array operations Used in Table Lookup operations (XLAT) Count register Used as a loop counter CL Used as count in shift and rotate operations Data register Used in multiplication and division Also used in I/O operations DX contains address of I/O ports in certain types of I/O instructions. Segment registers In 8086 1Mb memory is divided into four segments.
14

 - code, data, extra, stack Each segment has memory space of 64Kb. Each segment is addressed by a 16-bit segment register. - code segment register - data segment register - stack segment register - extra segment register 8086 address is of 20 bits. Segment register contains higher order 16 bits of 20 bit address. Memory address is computed by summing the contents of the segment register (shifted left by 4 bits) and an offset address.

Segment Registers - CS, DS, SS and ES Are Address registers Store the memory addresses of instructions and data
15

Memory Organization Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg of addressable memory Addresses are expressed as 5 hex digits from 00000 - FFFFF Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers! Solution: Memory Segment Block of 64K (65,536) consecutive memory bytes A segment number is a 16 bit number Segment numbers range from 0000 to FFFF Within a segment, a particular memory location is specified with an offset An offset also ranges from 0000 to FFFF

Segmented Memory
Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset

F0000 E0000 D0000 C0000 B0000 A0000 90000 80000 70000 60000 50000 40000 30000 20000 10000 00000 seg ofs 8000:0000
0250

8000:FFFF

one segment

8000:0250

16

Intel

Memory Address Generation

The BIU has a dedicated adder for determining physical memory addresses
Offset Value (16 bits)

Segment Register (16 bits)

0000

Adder

Physical Address (20 Bits)

Intel

Example Address Calculation

If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data?
2 Offset: Segment: Address: 9
0000000000101001 0001000000000000 0000 0001000000000010 1001

Logical Address is specified as segment: offset

17

 Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address Thus the physical address of the logical address A4FB:4872 is A4FB0 + 4872 A9822
The Code Segment
0H

CS:

0400H IP 0056H

4000H 4056H

CS:IP = 400:56 Logical Address Memory

Segment Register Offset Physical or Absolute Address +

0400 0 0056 04056H

0FFFFFH

The offset is the distance in bytes from the start of the segment. The offset is given by the IP for the Code Segment. Instructions are always fetched with using the CS register.
The physical address is also called the absolute address.

18

The Data Segment

0H

DS:

05C0 EA 0050

05C00H 05C50H DS:EA Memory

Segment Register Offset Physical Address +

05C0 0050 05C50H

0FFFFFH

Data is usually fetched with respect to the DS register. The effective address (EA) is the offset. The EA depends on the addressing mode.

The Stack Segment

0H

SS:

0A00 SP 0100

0A000H 0A100H

SS:SP Memory

Segment Register Offset Physical Address +

0A00 0 0100 0A100H

0FFFFFH

The offset is given by the SP register. The stack is always referenced with respect to the stack segment register. The stack grows toward decreasing memory locations. The SP points to the last or top item on the stack. PUSH - pre-decrement the SP POP - post-increment the SP

19

Pointer and Index Registers

These registers are used as memory pointers. POINTER AND INDEXED REGISTER Contain the offset addresses of memory locations Can also be used in arithmetic and other operations SP: Stack pointer Used with SS to access the stack segment Always points to a location of stack top. BP: Base Pointer Primarily used for indirect access of data on the stack Can be used to access data in other segments

SI: Source Index register DI: Destination Index register It stores offset incase of indexed, base indexed and relative base index addressing mode. The SI and the DI registers may also be used to access data stored in arrays It is also required for some string operations. Instruction pointer (IP): Also referred as program counter.
20

Used for calculation of memory address. It stores the offset of the instruction. IP contents are added to CS register contents after 4 bit left shift.

Flags

Overflow Direction Interrupt enable Trap 6 are status flags 3 are control flag Sign Zero

Carry flag Parity flag Auxiliary flag

FLAG REGISTER Conditional flags: They are set according to some results of arithmetic operation. You do not need to alter the value yourself. Control flags: Used to control some operations of the MPU. These flags are to be set by you in order to achieve some specific purposes.
Flag Bit no. 15 14 13 12 O 11 D 10 I 9 T 8 S 7 Z 6 5 A 4 3 P 2 1 C 0

CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a shift or rotate operation.

21

OF (overflow) Indicates overflow of the leftmost bit during arithmetic. DF (direction) Indicates left or right for moving or comparing string data.

IF (interrupt) Indicates whether external interrupts are being processed or ignored. TF (trap) Permits operation of the processor in single step mode.

22

23

24

25

MINIMUM MODE CONFIGURATION

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R. The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices.

26

Read Cycle timing Diagram for Minimum Mode

The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations.

27

 The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus. The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2. The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state.

The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.

28

Write Cycle timing Diagram for Minimum Mode

Bus Request & Bus Grant Timings in Minimum Mode System

Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given to another requesting master. The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock.

29

MAXIMUM MODE CONFIGURATION

Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.

30

S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.

In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. If reader input is not activated before T3, wait state will be inserted between T3 and T4.

Write Cycle timing Diagram for Maximum Mode

31

Bus Request & Bus Grant Timings in Maximum Mode System

The request/grant response sequence contains a series of three pulses. The request/grant pins are checked at each rising pulse of clock input. When a request is detected and if the condition for HOLD request are satisfied, the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state. When the requesting master receives this pulse, it accepts the control of the bus, it sends a release pulse to the processor using RQ/GT pin.

Instruction set of 8086

32

33

34

LEA Instruction - Load Effective Address

35

Load pointer to DS/ ES

LAHF Instruction - Load Register AH From Flags

36

LAHF instruction copies the value of SF, ZF, AF, PF, and CF, into bits of 7, 6, 4, 2, 0 respectively of AH register. This LAHF instruction was provided to make conversion of assembly language programs written for 8080 and 8085 to 8086 easier. SAHF instruction - Store AH Register into FLAGS SAHF instruction transfers the bits 0-7 of AH of SF, ZF, AF, PF, and CF, into the Flag register. PUSHF Instruction - Push flag register on the stack This instruction decrements the SP by 2 and copies the word in flag register to the memory location pointed to by SP. POPF Instruction - Pop word from top of stack to flag - register. This instruction copies a word from the two memory location at the top of the stack to flag register and increments the stack pointer by 2.

37

ADD Instruction - ADD destination, source

ADC Instruction - Add with carry

38

INC Instruction - Incrment

AAA will adjust the result of the two ASCII characters that were in the range from 30h (0) to 39h(9).This is because the lower 4 bits of those character fall in the range of 0-9.The result of addition is not a ASCII character but it is a BCD digit.

39

DAA Instruction - Decimal Adjust after Addition The contents after addition are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. S, Z, AC, P, CY flags are altered to reflect the results of the operation. If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example: MOV AL, 0Fh ; AL=0Fh(15) DAA ; AL=15h RET

40

SUBTRACTION INSTRUCTIONS

SBB Instruction - Subtract with borrow SBB destination, source

Decrement destination register or memory

41

Negate performs the twos complement subtraction of the operand from zero and sets the flags according to the result.

CMP Instruction - Compare byte or word -CMP destination, source.

If both operands are equal = Z Flag is set. If src > Des ,CY =1 else CY=0

42

43

Example: MUL BL MUL BH MUL CX AX. ;AL = 21h (33 decimal),BL = A1h(161 decimal ) ;AX =14C1h (5313 decimal) since AH0, CF and OF will set to 1. ; AL times BH, result in AX ;AX times CX, result high word in DX,low word in

Example: ; 69 * 14 ; AL = 01000101 = 69 decimal ; BL = 00001110 = 14 decimal IMUL BL ;AX = 03C6H = + 966 decimal ,MSB = 0 because positive result , - 28 * 59 ; AL = 11100100 = - 28 decimal ,BL = 00001110 = 14 decimal IMUL BL ;AX = F98Ch = - 1652 decimal, MSB = 1 because negative result

AAM Instruction - ASCII adjust after Multiplication AAM Instruction - AAM converts the result of the multiplication of two valid unpacked BCD digits into a valid 2-digit unpacked BCD number and takes AX as an implicit operand. To give a valid result the digits that have been multiplied must be in the range of 0 9 and the result should have been placed in the AX register. Because both operands of multiply are required to be 9 or less, the result must be less than 81 and thus is completely contained in AL. AAM unpacks the result by dividing AX by 10, placing the quotient (MSD) in AH and the remainder (LSD) in AL. Example:
44

MOV AL,5 MOV BL, 7 MUL BL AAM

;Multiply AL by BL , result in AX ;After AAM, AX =0305h (BCD 35)

DIV Instruction - Unsigned divide-Div source

Example: DIV CX

; (Quotient) AX= (DX:AX)/CX ; (Reminder) DX=(DX:AX)%CX

IDIV Instruction - Divide by signed byte or word IDIV source This instruction is used to divide a signed word by a signed byte or to divide a signed double word by a signed word. If source is a byte value, AX is divided by register and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by register , and the quotient is stored in AL and the remainder in DX. Example: IDIV BL ;Signed word in AX is divided by signed byte in BL AAD Instruction - ASCII adjust before Division ADD converts unpacked BCD digits in the AH and AL register into a single binary number in the AX register in preparation for a division operation. Before executing AAD, place the Most significant BCD digit in the AH register and Last significant in the AL register.
45

When AAD is executed, the two BCD digits are combined into a single binary number by setting AL=(AH*10)+AL and clearing AH to 0. Example: MOV AX,0205h ;The unpacked BCD number 25 AAD ;After AAD , AH=0 and AL=19h (25). After the division AL will then contain the unpacked BCD quotient and AH will contain the unpacked BCD remainder.
CBW Instruction - Convert signed Byte to signed word CBW converts the signed value in the AL register into an equivalent 16 bit signed value in the AX register by duplicating the sign bit to the left. This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be the sign extension of AL. Example: CBW ; AX = 00000000 10011011 = - 155 decimal ; Convert signed byte in AL to signed word in AX. ; Result in AX = 11111111 10011011 and = - 155 decimal

CWD Instruction - Convert Signed Word to - Signed Double word CWD converts the 16 bit signed value in the AX register into an equivalent 32 bit signed value in DX: AX register pair by duplicating the sign bit to the left. The CWD instruction sets all the bits in the DX register to the same sign bit of the AX register. The effect is to create a 32- bit signed result that has same integer value as the original 16 bit operand. Example: Assume AX contains C435h. If the CWD instruction is executed, DX will contain FFFFh since bit 15 (MSB) of AX was 1.

46

Both the original value of AX (C435h) and resulting value of DX : AX (FFFFC435h) represents the same signed number.

47

Program execution transfer instruction

48

UNIT 1 MICROPROCESSOR 8085 DEFINTION : Micro-processor is programmable integrated device that has computing & decision making capability. A Micro-processor is a multipurpose, programmable, clock driven, register based electronic device that reads binary information from a storage device called memory ,access binary data as input & process data according to those instructions & provide result as output.

It is a CPU on a single chip

Microprocessor
Arithmetic Logic Unit (ALU)

Control Unit

Intel 4004 First single chip 4- bit microprocessor

Register Memory

49

Microprocessor and its Applications

Personal Computers Consumer Electronics Industrial Process Control Automobiles Air Traffic Control System Medical Equipment

What is a CPU?
Central Processing Unit
CPU
Arithmetic Logic Unit (ALU)

Control Unit

Register Memory

Evolution of Microprocessors
Charles Babbage - originated the concept of a programmable computer mechanical computer that eventually led to more complex designs - "father of the computer"
50

Difference Engine A Difference Engine is an automatic, mechanical calculator designed to tabulate polynomial functions. ENIAC - Electronic Numerical Integrator and Computer Decimal (not binary) 20 accumulators of 10 digits Programmed manually by switches 18,000 vacuum tubes 30 tons 15,000 square feet 140 kW power consumption 5,000 additions per second Mainframe Computers UNIVAC Memory: mercury delay lines: 1000 words of 12 alphanumeric characters Secondary storage: metal oxide tape Access time: 222 microseconds (average) Instruction set: 45 operation codes Accumulators: 4 Clock: 2.25 Mhz

Second Generation (1958-1964) 1958 Philco introduces TRANSAC S-2000 first transistorized commercial machine IBM 7070, 7074 (1960), 7072(1961) 1959 IBM 7090, 7040 (1961), 7094 (1962) 1959 IBM 1401, 1410 (1960), 1440 (1962) FORTRAN, ALGOL, and COBOL are first standardized programming languages Third Generation (1964-1971) April 1964 IBM announces the System/360 solid logic technology (integrated circuits) family of compatible computers 1964 Control Data delivers the CDC 6600 nanoseconds
51

 telecommunications BASIC, Beginners All-purpose Symbolic Instruction Code Fourth Generation (1971-1984 ) Large scale integrated circuits (MSI, LSI) Databases (large) Structured languages (Pascal) MS-DOS, Windows 1.0,APPLE Mac OS Osborne 1, was released in 1981. Portable computers like the TRS-80 Model 100 / 102 and IBM 5155 . Cray-1-Supercomputers Fifth generation (1984-1990) superiority and parallel processing, where hundreds of processors could all work on various parts of a single program. Sequent Balance 8000, connected up to 20 processors to one shared memory module. artificial intelligence (AI), interact with the user to perform such functions as speech recognition, machine translation of spoken or written languages, and robotic operations. Two languages developed for computers of the 1990s are C++ and Java. Sixth generation (1990 -till date) This present generation of computer technology is highly related with parallel computing and develop algorithms to make full use of massive parallel architectures. Fujitsu Corporation is planning to build a system with more than 200 vector processors. Another goal of this sixth generation is to attain Teraflops i.e. ten arithmetic operations per second and that can be done by building up a system with more than thousand processors. The 1st P: Intel 4004 Introduced 1971 2250 transistors 108 kHz, 60,000 ops/sec 16 pins Targeted use: Calculators Cost: less than $100
52

Moores Law In 1965, one of the founders of Intel Gordon Moore predicted that the number of transistor on an IC (and therefore the capability of microprocessors) will double every year. Later he modified it to 18-months Evolution of Intel Microprocessors

Evolution of Intel Microprocessors

4-, 8-, 16-, 32-, 64-bit (Word Length) The 4004 dealt with data in words of 4-bits at a time Pentium 4 deals with data in words of 32-bit length The new Itanium processor deals with 64-bit words at a time

Enhancing the capability of a P? The computing capability of a P can be enhanced in many different ways: By increasing the clock frequency By increasing the word-width By having a more effective caching algorithm and the right cache size
53

By adding more functional units (e.g. ALUs, FPUs, etc.) Improving the architecture. 8080 first general purpose microprocessor 8 bit data path Used in first personal computer Altair 8086 much more powerful 16 bit instruction cache, prefetch few instructions 8088 (8 bit external bus) used in first IBM PC 80286 16 Mbyte memory addressable up from 1Mb 80386 32 bit Support for multitasking 80486 sophisticated powerful cache and instruction pipelining built in maths co-processor Pentium Superscalar (Instruction Level Parallelism) Multiple instructions executed in parallel Pentium Pro Increased superscalar organization Aggressive register renaming branch prediction data flow analysis speculative execution Pentium II MMX technology graphics, video & audio processing Pentium III Additional floating point instructions for 3D graphics
54

Pentium 4 Note Arabic rather than Roman numerals Further floating point and multimedia enhancements Itanium 64 bit see chapter 15 Itanium 2 Hardware enhancements to increase speed

New Approach Multiple Cores

Multiple processors on single chip Large shared cache Within a processor, increase in performance proportional to square root of increase in complexity If software can use multiple processors, doubling number of processors almost doubles performance So, use two simpler processors on the chip rather than one more complex processor With two processors, larger caches are justified Power consumption of memory logic less than processing logic Example: IBM POWER4 Two cores based on PowerPC Core First x86 with dual core Core 2 64 bit architecture Core 2 Quad 3GHz 820 million transistors Four processors on chip Name the latest Processors available in market? Core i7 features a better virtualization and digital media experience, which supports photo creation and publishing, video encoding and more complex games. Xeon is a successor to Pentium II, while Core i7 is a successor to the Core 2 family.

55

Two basic Architectures of Microprocessor Von Neumann Harvard

56

57