DESIGNOFLBANDLOWNOISEAMPLIFIER

StudyphasereportbyP.RajKumar Undertheguidanceof DrK.JVinoy

Abstract
A discrete 2-stage L-band low noise amplifier is designed. The amplifier is centered at 1.25 GHz with a noise figure (NF) less than 0.17 dB over a band width of 200 MHz. GaAs HEMTs offer low noise figure compared to MESFETs and silicon FETs. So, Agilent HEMTs, ATF-34143 and ATF-35143 are used in the 1st and 2nd stages respectively to obtain a overall noise figure less than 0.17 dB and gain more than 22dB. Amplifier is designed using ADS. 1st stage is designed to be mounted on the Rogers and 2nd stage on TMM6 substrate. Radial stubs are used in the biasing sections, so that any extra lengths of the micro strip lines in the bias sections does not cause any change in the amplifier characteristics. Matching sections are designed using 10-section impedance tapered line. Fabrication and characterization is yet to be completed.

Introduction
As a part of the literature survey, design of microwave amplifiers and differential amplifiers was studied. In amplifier design, there are a number of design techniques available in the literature depending on the parameter to be optimized. The most important design considerations in a microwave amplifier design are stability, power gain, bandwidth, and noise and DC requirements. General procedure for microwave amplifier design Any MIC amplifier design essentially consists of the following steps. 1. Selection of a proper transistor. 2. Checking the conditional stability. 3. If transistor is unstable at the desired frequency, proper techniques are applied to make it stable. 4. Biasing is done. Bias point is selected depending on the application like low power, low noise, high power, linearity etc. 5. Different techniques are applied to optimize different parameters like noise figure, gain, power dissipation. Two parameters cannot be optimized simultaneously. Matching circuits that provide optimum performance in a microwave amplifier can be easily and quickly designed using a Smith chart. 6. Then lumped components are replaced with distributed transmission lines. In the design of a low noise amplifier, the transistor should have minimum intrinsic noise. Noise sources present in a transistor should be properly modeled.

Design steps of LNA

Entire design steps followed in the LNA design are explained in the following sections. ADS is used in the simulation of the LNA. The design is based on the S-parameters of the transistor.

Selection of the type of the design In ADS there are two types of devices, (1) S-parameter & (2) normal device. S-parameter device is an in-built device with S-parameters loaded from the data sheet. There is no need of applying external bias to it, because it has fixed S-parameters (i.e. fixed biasing). On the other hand normal device is just like any transistor device to which any bias value can be applied. For the LNA design, S-parameter device is chosen in general Selection of the transistor Selection of the transistor is the crucial stage in LNA design. Any transistor has its maximum available gain (MAG) and minimum intrinsic noise figure (NFmin). So after adding the matching and biasing sections, we cannot achieve gain more than MAG and Noise figure less than NFmin. To achieve a gain over 20 dB, a 2-stage LNA is designed. As we know, noise figure of the first stage is very crucial in the overall noise figure, because the noise figure of the next stages is reduced by a factor equal to the total gain till that stage. So ATF-34143 HEMT is selected for the first stage. It has a noise figure of 0.11dB at a bias point of Vds= 3V & Ids = 20mA. In the 2nd stage gain is concentrated, so ATF-35143 @ Vds = 2V & Ids = 10mA is selected. It has an intrinsic gain of 15 dB. Stability check When embarking on any amplifier design it is very important to spend time checking on the stability of the device chosen, otherwise the amplifier may well turn into an oscillator. The main way of determining the stability of a device is to calculate the Rolletts stability factor (K), which is calculated using a set of S-parameters for the device at the frequency of operation.

K & || to give us an indication to whether a device is likely to oscillate or not or whether it is conditionally/unconditionally stable. The parameters must satisfy K > 1 and || < 1 for a transistor to be unconditionally stable. The Calculations are long winded and it is much quicker to simulate under ADS.

fig(1) ADS simulation setup for the calculation of the stability factor

Stability enhancement There are different techniques to enhance the stability. Some of them are listed below (a) Adding a series resistance: A small resistance is added in series with the gate of the transistor. This will improve the stability, but this technique is not used in the LNA design, because resistors are potential sources of thermal noise. This will increase the Noise figure of the amplifier. (b) Adding a source inductance: Another method of improving stability is to add an inductor to the source leg [3]. It can be proven by simple first order approximation that, a source inductor acts like a noise less resistance. But this reduces gain by a small factor. This method is followed in the project and inductors 5.96nH & 3.1nH are added in 1st & 2nd stages respectively to improve the stability. Biasing the transistor RF/Microwave transistors/FET requires some form of circuit to set the correct bias conditions for a particular RF performance. What is required is a low DC resistance but a high RF resistance to ensure that the RF circuit is not loaded and RF signals do not flow onto the supply lines. One probable and commonly used method is to place a radial stub immediately after l/4 high impedance bias line [4]. This helps to achieve proper isolation at desired RF frequency, no matter what component is added after l/4 long bias line.
MRSTUB Stub1 Subst="MSub1" Wi=1.5 mm {t} L=13.2066 mm {t} Angle=63 {t}

-20
MTEE_ADS Tee1 Subst="MSub1" W1=0.3 mm W2=3 mm W3=1.12 mm

MLIN TL6 Subst="MSub1" W=1.12 mm L=2 mm

d B (S (6 , 4 )) d B (S (5 , 4 )) d B (S (4 , 4 ))

Term Term6 Num=6 Z=50 Ohm

-40

-60

MLIN TL5 Subst="MSub1" W=0.3 mm L=22.77 mm

-80

Term Term4 Num=4 Z=50 Ohm

Term Term5 Num=5 Z=50 Ohm

-100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

freq, GHz

Fig(2) (a) ADS simulation setup for the calculation of the radial stub dimensions for the biasing & (b)graph showing the isolation between the DC & RF

S-PARAMETERS
S_Param SP1 Start=0 GHz Stop=2.5 GHz Step= MRST UB Stub2 Subst="MSub1" Wi=1.5 mm {-t} L=13.1458 mm {t} Angle=60 {-t}

MCORN Corn1 MLIN Subst="MSub1" T L11 W=2 mm Subst="MSub1" W=2 mm L=1 mm

MLIN C T L12 C1 Subst="MSub1" C=1.0 pF W=2 mm L=0.5 mm

MT EE_ADS T ee2 Subst="MSub1" W1=0.8 mm W2=1.5 mm W3=2 mm

MLIN T L8 Subst="MSub1" W=2 mm L=2 mm {-t}

L L1 L=1 nH {-t} R=

MLIN T L9 Subst="MSub1" W=2 mm {-t} L=2 mm {-t}

MT EE_ADS T ee3 Subst="MSub1" W1=2 mm W2=2 mm W3=2 mm MLIN T L10 Subst="MSub1" W=2 mm L=1 mm

MLIN T L7 Subst="MSub1" W=0.3 mm {t} L=23.2535 mm {t} MSub T erm T erm1 Num=1 Z=50 Ohm T erm T erm2 Num=2 Z=50 Ohm MSUB MSub1 H=1.6 mm Er=10.5 Mur=1 Cond=5.8e7 Hu=1.0e+033 mm T =0.018 mm T anD=0.0023 Rough=0.001905 mm

MCORN Corn2 Subst="MSub1" W=2 mm

R MLIN MLIN R1 T L13 T L14 R=50 Subst="MSub1" Ohm Subst="MSub1" W=2 mm W=2 mm L=1 mm L=3 mm

T erm T erm3 Num=3 Z=50 Ohm

Fig (3) ADS setup of full bias section

Design of matching sections The amplifier could be matched for a variety of conditions such as low noise applications, unilateral case and bilateral case [5]. The formulae for each condition follow [6]. (a) Optimum Noise Match: The matching for lowest possible noise figure over a band of frequencies requires that particular source impedance be presented to the input of the transistor. The noise optimizing source impedance is called as Gopt, and is obtained from the manufacturers data sheet. The corresponding load impedance is obtained from the cascade load impedance formula.

S 22 opt * L = 1 * S11 opt (b) Optimum power Match:

S S Unilateral case: in = S11 + 12 21 L 1 S 22 L
2

S S out = S 22 + 12 21 S 1 S 11 s
2

Bilateral case : M s =

B1 B1 4C1 2C1

M L =

B2 B2 4C 2 2C 2

B1 = 1 + mod 2 ( S11 ) mod 2 ( S 22 ) 2

B2 = 1 + mod 2 ( S 22 ) mod 2 ( S11 ) 2

C1 = S11 S 22

C 2 = S 22 S11

Once the corresponding load impedance is obtained, it can be realized using many techniques like L-section matching, single and double stub tuning, multistep transformer and Tapered lines [7]. A Tapered section with 10-transformers is used for the impedance transformation, because of its smooth transformation and hence high return loss. ADS setup for the tapered line matching section [8] is shown below

MSub
MSUB MSub1 H=1.6 mm Er=10.5 Mur=1 Cond=5.8e7 Hu=1.0e+033 mm T=0.018 mm TanD=0.0023 Rough=0.001905 mm MLIN TL2 Subst="MSub1" W=1.37937 mm L=0.105 mm MLIN TL4 Subst="MSub1" W=1.09583 mm L=0.105 mm MLIN TL6 Subst="MSub1" W=1.19739 mm L=0.105 mm
M STEP Step8

MLIN TL8 Subst="MSub1" W=1.32935 mm L=0.105 mm

M STEP Step4 Subs t="M Sub1"

M STEP Step5 Subs t="M Sub1"

MLIN TL10 Subst="MSub1" W=1.15854 mm L=0.105 mm

S-PARAMETERS
S_Param SP1 Start=0.5 GHz Stop=1.8 GHz Step=

M STEP Step1 Subs t="M Sub1" W1=2.5249 m m W2=1.37937 m m

M STEP Step2 Subs t="M Sub1" W1=1.10858 m m W2=1.09583 m m

M STEP Step3

W1=1.2492 m m Subs t="M Sub1" W2=1.32935 m m W1=1.19379 m m Subs t="M Sub1" W2=1.2492 m m W1=1.15218 m m W2=1.19739 m m

W1=1.38217 m m W2=1.15854 m m

R R2 V_DC R=100 Ohm SRC2 Vdc=5 V

M STEP Step6 Subs t="M Sub1" W1=1.37937 m m W2=1.10858 m m

M STEP Step7 Subs t="M Sub1" W1=1.09583 m m W2=1.15218 m m

M STEP Step9 Subs t="M Sub1" W1=1.32935 m m W2=1.38217 m m

M STEP Step10 Subs t="M Sub1" W1=1.15854 m m W2=0.824771 m m

L L4 L=20 nH R=
Term Term 2 DC_Bloc k DC_Bloc k 2 Num =2 Z=50 Ohm

Term Term1 MLIN C MLIN Num=1 TL13 C1 TL1 Z=50 Ohm Subst="MSub1" C=5.07167 pF Subst="MSub1" W=1.12991 mm W=2.5249 mm L=3 mm L=2 mm

MLIN TL3 Subst="MSub1" W=1.10858 mm L=0.105 mm

MLIN TL5 Subst="MSub1" W=1.15218 mm L=0.105 mm

MLIN TL7 Subst="MSub1" W=1.2492 mm L=0.105 mm

MLIN TL9 Subst="MSub1" W=1.38217 mm L=0.105 mm

L MLIN L1 TL11 L=8.66948 nH Subst="MSub1" R= W=0.824771 mm L=2 mm

MLIN TL12 Subst="MSub1" W=0.824771 mm L=3 mm

DC_Bloc k DC_Bloc k 1

L L3 L=20 nH R= R R R3 R1 R=470 Ohm {t} R=3063 Ohm

ph_hp_ATF34143_19990129 X1 L L2 L=5.96643 nH {t} R=

Fig (4) ADS setup of the Tapered line input matching section

V_DC SRC1 Vdc=-5 V

Design of the intermediate & output matching section The 1st stage has no matching on the output and as we require a good output return loss we should match to S22*. Note S22 will now have been modified by adding the input matching circuit and will have to design the matching circuit to be the conjugate of S22 modified (This is because S22 is looking into the device and the conjugate will looking towards the matching circuit. The intermediate matching section should transfer the impedance from the S22 modified to the S11 of the 2nd stage transistor (ATF-35143). In order to improve the gain and noise response of the final stage we need to provide the RL = ROUT* given by:

Optimization After the total circuit is realized, it is given to Optimization so that desired noise figure and gain is obtained. Simulation Results After optimization total circuit is simulated in the ADS. The simulation results are shown below.

0.26 0.24 0.22 -2 0.20 -4 0.18 0.16 1.10 1.15 1.20 1.25 1.30 1.35 1.40

nf(2)

dB(S(2,2)) dB(S(1,1))

-6 -8 -10 -12

freq, GHz

26

-14 1.10 1.15 1.20 1.25 1.30 1.35 1.40

24

freq, GHz

dB(S(2,1))

22

20

18 1.10 1.15 1.20 1.25 1.30 1.35 1.40

freq, GHz

Fig (5) Simulation results from the ADS

Conclusion
A 2-stage L-band low noise amplifier centered about 1.25GHz is designed using the software ADS. Fabrication & characterization is yet to be completed. The amplifier is centered at 1.25 GHz with a noise figure (NF) less than 0.17 dB & gain more than 20dB over a band width of 200 MHz. to obtain a overall noise figure less than 0.17 dB and. Return loss of at least 8dB is attained over a bandwidth of 100MHz.

References:
[1] Kuo-Jung Sun, Zuo-Min Tsai, Kun-You Lin, A Noise Optimization Formulation for CMOS Low-Noise Amplifiers With On-Chip Low-Q Inductors in IEEE Transactions on Microwave Theory and Techniques, Vol 54, N0 4. Feb 2006. [2] Yuhki Imai, Masami Tokumitsu, and Akira Minakawa , Design and Performance of Low-Current GaAs MMIC's for L-Band Front-End Applications in IEEE Transactions on Microwave Theory and Techniques, Vol 39, N0 2. Feb 1991. [3] Thomas H Lee, Design of RF CMOS circuits. [4] Anurag Bhargava , Amplifier design made simple. [5] David M. Pozar, microwave and RF design of wireless systems [6] Microwave Transistor Amplifiers: Analysis and Design, Gonzalez, Guillermo, Prentice Hall, 1984. [7] R.W.Klopfenstein , A tapered line taper of improved design in proceedings 1995 IRE. [8] Agilent ADS 2004A, help manual