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Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

ANALOG LAYOUT

By Ali Daneshfar

1383 - Azar

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Outline
Layout Overview and Design Rules Devices Matching Noise considerations LatchUp Antenna ESD PADs and Packaging

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Layout Overview and Design Rules


N-WELL and P-WELL

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

ACTIVE or DIFFUSION

Birds beak

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

GATE(POLY1)

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layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

PPLUS

Lateral diffusion

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

NPLUS

Well contact

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layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

CONTACT Contacts must be as separate squares not a continuous rectangle. Use maximum possible contacts. Do not contact over gate.

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

METAL1

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

VIA

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

METAL2 For Analog design, do not route over gate.

wafer

layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Isolated NMOS in a P-Substrate (useful in RF applications)


Implementing a retrograde well(R-well) or P-type well in the N-well.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Silicidation

silicide process

polycide process

molybdenum process

salicide(self aligned polycide) process metal spacer silicide

source/drain polysilicon

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Devices
PMOS NMOS BJT DIODE RESISTOR CAPACITOR INDUCTOR

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

PMOS
DIFF NWELL CONTACT POLY1 PPLUS METAL1 POLY2 NPLUS

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

NMOS
DIFF NWELL CONTACT POLY1 PPLUS METAL1 POLY2 NPLUS

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Split large W transistors into smaller W transistors


Even splitting is preferred. Splitting results in : Smaller area. Optimizing gate resistance. Reducing S/D junction parasitic capacitance.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

drain

(a) Drain area = 0.67X drain

(b) Drain area = 0.50X Structure (b) is preferred(even splitting).

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Reducing gate resistance and Noise

Necessary for very large transistors.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Series transistors

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Vertical PNP
DIFF NWELL CONTACT POLY1 PPLUS METAL1 POLY2 NPLUS

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

RESISTORS
N+ (5 4 / Silicide P+ (5 4 / POLY Nonsilicide P+ (160 15 / N+ Poly Nonsilicide is the most precise resistor. ) ) ) )

N+ (180 10 /

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

RESISTORS(continue)
N+ (5 4 / Silicide P+ (5 4 / DIFF Nonsilicide P+ (145 20 / NWELL (1100 400 / ) METAL ) ) (0.07 / ) ) )

N+ (61 7.5 /

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

RESISTORS(continue)

Poly resistor

DIFF NWELL CONTACT POLY1 PPLUS

NWELL resistor

METAL1 POLY2 NPLUS

R = Rs ( L / W )

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Better for precise resistors. Use large width(2 um). Use large length(Min. 3 )

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

RESISTORS in RF applications

VDD

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

CAPACITORS
Poly Poly ~ 1fF/um2 Metal Metal ~ 1fF/um2 MOS gate capacitance

C = Carea Area + Cperimeter Perimeter

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Precise capacitor

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

MET3 MET2 MET1 poly

C3 C2 C1

Ceq = C1 + C2 + C3 Between all conductor and semiconductor layers there are small capacitors called parasitic capacitors : surface to surface, edge to surface and edge to edge.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

INDUCTOR

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Matching : MOS
Equal W Same orientation Symmetry in X&Y (common centroid configuration) Dummy gates for outside transistors

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Common Centroid Configuration

15

dummy

A : 30/2

B : 30/2

C:60/2

dummy

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

DIFF NWELL CONTACT POLY1 PPLUS METAL1

POLY2 NPLUS

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Matching : Resistors

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Matching : Capacitors

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

A Sample OPAMP Layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Where does noise coupling occur?


Capacitive and Inductive coupling between wires. Direct ohmic connections(power supply line). Substrate coupling.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Cross Talk Noise


Use shields connected to power and ground.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Supply & Ground Bounce (Noise)

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Supply & Ground Bounce (Noise)


Use of different power supply lines(star topology).

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Substrate Coupling

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Substrate Coupling (continue)


Layout analog and digital circuitry in different sections of the chip. Protect analog(sensitive) layout by guard rings.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Substrate Coupling (continue)

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Substrate Coupling (continue)

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Design Techniques

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Design Techniques

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Design Techniques

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Antenna Effect
--------- - - - - - - - - - - - - - - - - - (problem)

(solution 1 )

(solution 2 )

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Latch Up
VDD rn rn Q1 Q2 Q2 rp GND rp Q1

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Latchup starts if : Large parasitic resistances(rn, rp). Large leakage current. Latchup prevention rules : Place substrate and well contacts between transistors of different types Maximize the number of substrate and well contacts. Minimize the distance between substrate contacts and transistors within a well. Minimize the spacing between substrate and well contacts.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

ESD
ESD damages: gate oxide break down. S/D junction melting.

Effects of ESD protection diodes: Parasitic capacitance : degrading the speed. Coupling noise on VDD. Causing latchup if bad designed.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

PADs and Packaging


cavity package bond wire

circuit core lead die

trace PAD

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

PAD structure : Overlaying all conductive layers . For possible bonding : PAD dimensions ? PAD spacing ? PAD placement ? Parasitic effects : bond wire and trace self inductance. trace to trace mutual inductance. trace to trace capacitance.

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Reduction of mutual coupling

Prependicular lines

Additional ground lines

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

A Sample Full Chip Layout

Analog VDD Digital VDD

ANALOG

DIGITAL

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design Sharif University Sayyed Mojtaba Atarodi

Design Flow
Design, Simulation

Layout

DRC

LVS

No Simulation Yes OK? Extraction Including Parasitics

Fabrication

GDSII

Emad Semicon Co. (Ali Daneshfar)

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