International Journal of Computer Information Systems, Vol. 4, No.

1, 2012

FPGA to ASIC Conversion An SOC Level Approach

Rajeev Kamal EECE Department ITM UNIVERSITY Gurgaon Haryana
Abstract Now-a days designing chips is no more challenging like earlier when there were no powerful eda tools available, with evergrowing technology ,engineers now have new considerations to balance while choosing for the best way to implement their designs. High-end field-programmable gate arrays (FPGAs) are growing in density (gate count) while handling higher-speed applications and more complex designs. On the other hand, high-end application-specific integrated circuits (ASICs) are considered unpredictable at 90 nm and below[1]. So the big question with a chip designer is of choosing the best way out to implement a design. Although there are no more distinctions between some traditional ASIC and FPGA applications, the basic ground rules are still in application. Yet designers should appreciate the subtle differences between each target platform optimising both on area, power, delay norms. This paper will fetch out of the confusion and offer some insights into the best pathway to silicon implementation. Keywords- Application-specific integrated circuits (ASIC), field programmable gate array(FPGA)

Vikas Nehra EECE Department ITM UNIVERSITY Gurgaon Haryana

using programmable switches. Logic blocks can be programmed a multiple times to perform the function of basic logic gates such as AND,OR, XOR, or more complex combinational functions such as decoders or any mathematical functions. ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed for a specific application, rather than intended for general-purpose use. Processors, RAM, ROM, etc are examplesofASICs. In this paper, we have emphasized on FPGA to ASIC conversion, highlighting the gap between the two in Section II. Section III raises up SoC design problems that come across with FPGA and ASIC design flows in next Section. Discussing a half-adder case study in Section V, we have headed towards the Comparison metrics in Section V to Conversion benefits in Section VII. Eventually, a conclusion has been included. I. GAP BETWEEN FPGAS AND ASICS A MEASUREMENT

Introduction Earlier standard-cell ASICs were considered the best implementation choice for high-volume, price-sensitive applications whereas FPGAs were restricted to low-volume, price-insensitive applications. FPGAs were used mainly to prototype parts and portions of a large ASIC design .Structured ASICs, which have some limited design flexibility, fell somewhere midway.Are all these generalizations of past hold still true? Havent latest trends in FPGAs included higher speeds, higher gate counts, lower non-recurring engineering (NRE) costs? How does the process flow affect the selection between an ASIC and an FPGA? And what is the key concern in design complexity? The answers to these and many more must be gained before one can select the best and apt route to silicon implementation. As with most engineered solutions, the final answer relies greatly upon a variety of design-tradeoffs studies. Even with the results of these studies, however, each decision point carries a host of forewarnings. But this is sort of technical balancing act that most engineers enjoy. A chip can be implemented as a programmable logic device (FPGA or CPLD) or an ASIC as per requirement. FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks that can be configured

Application-specific integrated circuits(ASICs) or fullcustom design, field programmable gate arrays (FPGAs) offer many advantages - reduced nonrecurring engineering costs , shorter time to market and capability of partial reconfiguration-process of configuring a portion of FPGA while other part is still running. However, all these advantages come at the cost of an increase in silicon area, a decrease in performance, and an increase in power consumption when designs are implemented on FPGAs. The existence of these kind of efficiency issues in FPGA-based implementations is widely known , but there have been a very few efforts to assess these differences. These differences result in an area, performance and power consumption gap between ASIC or full-custom designs and FPGAs. We were motivated to measure this FPGA to ASIC gap for the following reasons. 1) In the early stages of system design, when system architect choose their implementation medium, they often choose between FPGAs and ASICs. Such decisions are based on the differences in cost (which is related to area),performance, and power consumption between these implementation media, but to date, there have been few attempts to quantify these differences. A system architect can

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use these measurements to assess whether implementation in an FPGA is feasible. These measurements can also be useful for those building ASICs that contain programmable logic by quantifying the impact of leaving part of a design to be implemented in the programmable fabric. 2) FPGA makers seeking to improve FPGAs can gain insight by quantitative measurements of these metrics, particularly when it comes to understanding the benefit of less programmable (but more efficient) hard heterogeneous blocks such as block memory , multipliers/accumulators , and multiplexers that modern FPGA often employ.[2] . II. SOC DESIGN ISSUES

International Journal of Computer Information Systems, Vol. 4, No.1, 2012 PERFORMANCE As communication systems are evolving, terms like bandwidth and bit-rate grab greater importance. SoC designs within those systems are needed to give out as much performance as possible to keep up with data rates measured in gigabits per second (gps). Achieving higher performance is always a goal while designing complex SoCs used in communication systems. POWER Power is another critical resource in today's communication systems. As portable wireless devices are getting smaller and smaller the available power is decreasing while at the same time the complexity of the device is increasing. SoC designs used in such devices must conserve as much power as possible. Lower power equates to smaller and less expensive power supplies, savings on board space and fewer cooling components, which ultimately helps in reducing overall cost. QUALITY Design quality and manufacturing quality are two types of quality to be examined. The first quality issue, design quality, refers to whether or not the application functions are as specified. The second quality issue, manufacturing quality, refers to the quality and reliability of each manufactured device. Both are critical in providing quality parts to the customer.[3] IP

There are seven primary issues to consider when starting a SoC design: Cost, Time-To-Market (TTM), Capacity, Performance, Power, Quality and IP. This section will define all seven of them. COST The minimization of cost on any engineering project is important. The main issue with FPGAs is their high per unit cost and with ASICs , high up-front cost or NRE (Non-Recurring Engineering)-one-time cost of researching, designing, and testing of a new product. So which technology offers the most cost effective solution? This question will be answered in the following sections . Finally, a recommendation will be made on the most cost effective solution. TIME-TO-MARKET (TTM) Time-to-Market or TTM is another very vital issue that has to be taken care of when starting a new SoC development project. TTM is not only critical in defending competitors to market but it also impacts the overall cost of the project . The longer it takes to market a product , the greater is the impact to market share. In fact, every month a product is delayed, costing company a great loss in market share. Projects having longer development spans require additional resources (manhours, tool licensing, etc.). The bottom line is also affected by such additional resources. Between the impact to market share and the cost of additional resources, it is easy to understand the importance TTM possesses to every project. CAPACITY Capacity is another key issue when talking of SoC design. Presently, communication SoCs that are available can easily reach into the millions of gates. Size may be the determining factor when considering whether to implement the SoC as an FPGA or as an ASIC. However, even for large SoC designs , a methodology including the shorter FPGA verification cycle is desired to be put to use.

Design reuse in the form of proven IP cores can greatly reduce TTM and increase quality for SoC designs. According to Dataquest by 2005 SoCs will contain 80% pre-define IP blocks and 20% custom logic. By 2010 the percentage of IP contained in a SoC is predicted to grow to 95%. This increase in demand for IP cores has lead to an explosion of IP core vendors in the market. The use of IP cores gives designers the flexibility to concentrate most of their time on the application specific material while spending a small amount of time on common design blocks. The final effect is a substantial increase in overall productivity, which leads to a substantial decrease in TTM. Also, once an IP block is mature (has been used in numerous designs) the risk associated with implementing the core is minimal and results in higher design quality.[3] Power is another critical resource in today's communication systems. As portable wireless devices are getting smaller and smaller the available power is decreasing while at the same time the complexity of the device is increasing. SoC designs used in such devices must conserve as much power as possible. Lower power equates to smaller and less expensive power supplies, savings on board space and fewer cooling components, which ultimately helps in reducing overall cost.

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III.

FPGA VS ASIC CAD FLOW

International Journal of Computer Information Systems, Vol. 4, No.1, 2012 Testing of a design is of two kinds:-

1) Functional Testing-Functional testing is a type of black box testing that bases its test cases on the design under test (DUT)specifications. Designs are tested by feeding them with input and examining the output, and internal program structure is rarely considered. Functional testing typically involves five steps:
The identification of functions that the software is expected to perform The creation of input data based on the function's specifications The determination of output based on the function's specifications The execution of the test case The comparison of actual and expected outputs[4]

Figure-2 Circuit Simulation using ModelSim v5.4 2) Electrical Testing/FPGA Emulation- Electrical testing of a design is done on virtual platform using synthesis tools e.g. Altera,Xilinx etc connecting Xilinx Spartan3 kit(FPGA) . We provide inputs using configurable switches on kit and obtain the required outputs as per inputs. Oncethe design is successfully tested on FPGA,real time synthesis can be performed implementating that specific design as an ASIC as per above given ASIC design flow.

Figure1-FPGA & ASIC CAD FLOW

IV.

HALF ADDER-A CASE STUDY

A 0 0 1 1

Figure2- Circuit Diagram B S 0 0 1 1 0 1 1 0

C 0 0 0 1

Figure-3

Black Box Designs

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International Journal of Computer Information Systems, Vol. 4, No.1, 2012 V. COMPARISON METRICS Speed In terms of speed ,ASIC rules out FPGA. As ASICs are basically designed for a specific application they can be optimized to maximum, hence we can obtain highspeed in ASIC designs. ASIC can have high speed clocks. Figure -4 UCF File Cost FPGAs are most cost effective for small scale applications. But when it comes to complex and large volume designs (like 64-bit processors) ASIC products are comparatively cheaper. Size/Area FPGAs contain lots of LUTs(Look Up Tables) and routing channels connected via bit streams. As they are designed for general purpose and because of re-usability,they are ingeneral larger designs than corresponding ASIC designs. For example, LUT gives you both registered and nonregistered output, but if we are requiring only non-registered output, then having an extra circuitry is of no use. In this way ASIC would be smaller in size. Power FPGA designs dissipate more power than ASIC designs. As explained above the unwanted circuitry results in wastage of power. FPGA would not allow for having better power optimization. When it comes to ASIC designs ,these can be fully optimised in an efficient manner. Time to Market As design cycle of FPGA designs is small,they take less time when compared to that of ASIC designs. Layouts, masks or other back-end processes are not needed. Its is too simple: Specifications -- HDL + simulations -- Synthesis -Place and Route (along with static-analysis) -- Dump code onto FPGA and Verify. When it comes to ASICs we have to perform tasks like floor planning and also advanced verification incuding Design Rule Checks(DRC) and Layout vs Schematic(LVS) verification. The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic has already been synthesized to be placed onto an already verified, characterized FPGA device.[5] A. Type of Design ASICs can have both mixed-signal designs or only analog designs. But it is not at all possible to design and implement them using FPGA chips onlyAuthors and Affiliations Customization ASICs can be effectively customized as compared to FPGAs

Figure -5 RTL Diagram

Figure-6 FPGA Emulation (Bit file successfully dumped on FPGA)

Figure-7 Xilinx Spartan3AN kit

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as they are designed according to a given specification. Just think of implementing a 64-bit processor onto an FPGA. Prototyping Because of FPGAs being reusable, they are used as ASIC prototypes. ASIC design HDL code is first dumped onto a FPGA and then tested for accurate results. Once the design is proven error free then it is forwarded for further steps . Its almost clear that FPGA may be needed for designing an ASIC. Non Recurring Engineering ExpensesWhen budgeting for a a particular project, NRE must be considered in order to assess if a new product will be profitable or not.NRE refers to the one-time cost of researching, designing, and testing a new product, generally associated with ASICs.There are no such associations with FPGA. Hence FPGA designs are cost effective. Simpler Design Cycles Due to software handling much of the routing, placement, and timing, FPGA designs have smaller design cycles than ASICs.The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic has already been synthesized to be placed onto an already verified, characterized FPGA device.[5] One of the most time-consuming portions of the ASIC flow is all of the hand-off points, for place and route, test vector generation, and for prototype fabrication. Since the FPGA flow is integrated within a single front-to-back development system, there are no hand-off points and no loss of control during the design phase.[6] More Predictable Project Cycle Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project cycle. [7] Tools Tools used for FPGA design implementations are relatively cheaper than ASIC designs. Re-Usability A single FPGA can be used for various applications, by simply reprogramming it (dumping new HDL code). By definition ASIC are application specific cannot be reused.[7] Netlist The template is designed so that author affiliations are not repeated each time for multiple authors of the same affiliation. Please keep your affiliations as succinct as possible.

International Journal of Computer Information Systems, Vol. 4, No.1, 2012 VI. ASIC SYNTHESIS NETLIST . Cell AN2T0 XR2T0 Number of ports : Number of nets : Number of instances : Number of gates : Library References scl05u scl05u 1x 1x 5 5 4 4 2 10 Total Area 5 gates 5 gates

VII. FPGA SYNTHESIS NETLIST Number of ports : 4 Number of nets : 10 Number of instances : 8 Clearly, in case of FPGA the no. of nets and instances are quite larger than that of ASICs whereas no. of ports remain constant. VIII. FPGA TO ASIC CONVERSION-THE BENEFITS With an effective FPGA-to-ASIC conversion, system designers can quickly get their system designed and into production using FPGA technology. Then, once the design is fully proven on all means, can be converted to a structured ASIC rapidly and cost-effectively. The low nonrecurring-engineering (NRE) charges associated with a structured ASIC, coupled with the much lower unit cost, make this strategy of conversion a powerful tool to achieve low overall costs and improve competitive advantage. To achieve the full benefit of a conversion, it is important to prototype with conversion in mind. Any differences in core voltage, for example, can be accounted for and the advanced FPGA design moved to a larger-process-geometry structured ASIC. Package requirements and board layout must be considered, bearing in mind that, even though FPGA conversion targets pin-for-pin dropin replacement, the design may fit into a lower-pincount package once it is migrated to an ASIC. If, for example, the production ASIC can use a lowerperformance industry-standard package with lower ball counts, device costs can be further reduced over a typical drop-in replacement.[8] It is also important to understand long-term intellectual-property needs. Many FPGA vendors make small modifications to standard IP. Licensing agreements will prevent the designer from moving

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the FPGA vendor-specific IP to an ASIC, and the small modifications made to the IP mean that offthe-shelf third-party IP may not work as a drop-in replacement. If the design team believes a program will go into volume production, third-party IP should be used and a license agreement negotiated that allows IP used in the FPGA to be migrated to a structured ASIC.[8] The ability to convert from even the most complex FPGAs to structured ASICs is creating a symbiotic relationship between FPGA and ASIC vendors that provides OEMs with the best of both worldsflexible and rapid development at minimal cost, combined with compact, low-power, low-cost components for final manufacture. [8] We have successfully converted thousands of designs from costly FPGAs to efficient ASICs throughout the past few decades. The lower unit cost of an ASIC has long been a key motivating factor in such conversions. However, the appeal of FPGA to ASIC conversions goes far beyond the cost savings. The significant power savings realized through using an ASIC in the place of an FPGA significantly increases battery life. Applications, such as hand-held devices, find this to be a tremendous advantage. In contrast to the programmable logic used in FPGAs, the hardcoding of the logic in an ASIC, does not allow reprogramming of the device, thereby increasing security and reliability. This added reliability makes ASICs the obvious choice for flight-critical applications where SRAM based FPGAs are typically not qualified. [9]

International Journal of Computer Information Systems, Vol. 4, No.1, 2012 FPGA or an ASIC, therefore actually make sense to use EDA tools for this purpose that do not lock the developer into any one design flow, architecture, or vendor. Even the FPGA package selection is quite limited, but Structured ASICs have a wide range of packages, saving cost and board area. If pin compatibility with the FPGA prototype is needed, the pinout and package selection should be discussed at an early stage with your ASIC vendor to ensure that your requirements can be met later on. Thus,FPGA to ASIC conversion becomes a smooth process. ACKNOWLEDGMENT The authors are very grateful to their organization they belong for their constant encouragement and support. REFERENCES
[1] [2] http://chipdesignmag.com/display.php?articleId=115&issueId=11 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 http://www.design-reuse.com/articles/4360/fpga-to-asic-strategy-forcommunication-soc- designs.html http://en.wikipedia.org/wiki/Functional_testing http://www.xilinx.com/company/gettingstarted/fpgavsasic.htm http://www.xilinx.com/products/virtex/asic/methodology.htm http://only-vlsi.blogspot.com/2008/05/fpga-vs-asic.html http://www.design-reuse.com/articles/8664/fpga-to-asic-conversion-acrucial-concern.html AUTHORS PROFILE

[3] [4] [5] [6] [7] [8]

Moreover, by planning for FPGA-to-ASIC conversion from the outset, and to work with a conversion company that can offer the necessary IP taking an FPGA prototype and converting it to a structured ASIC, it is possible to have ASICs ready as soon as FPGA-based product trials are complete, thus minimum time-to-market and maximum competitive advantage are ensured. IX. CONCLUSION

Rajeev Kamal, Asst. Professor in the Department of Electrical, Electronics and Communication Engineering, ITM University, Gurgaon, (Haryana), India has received his M.Tech. (VLSI Design) from GGSIP University, Delhi and B.Tech. (Electronics & Communication Engineering) Degrees from the U P Technical University, Lucknow (Uttar Pradesh), India in the year of 2008 and 2006, respectively. His main research interests are in ASIC Design/Verification, Network on Chip, Open Source EDA, VerilogHDL, SystemVerilog, HVL, and RTL Design. He has more than two-years of experience in academics and industry. Vikas Nehra, Asst. Professor in the Department of Electrical, Electronics and Communication Engineering, ITM University, Gurgaon, (Haryana), India has received his M.Tech. (VLSI Design) from GGSIP University, Delhi and B.Tech. (Electronics & Communication Engineering) Degrees from the U P Technical University, Lucknow (Uttar Pradesh), India in the year of 2008 and 2006, respectively. His main research interests are in ASIC Design/Verification, Network on Chip, Open Source EDA, VerilogHDL, SystemVerilog, HVL, and RTL Design. He has more than two-years of experience in academics and industry.

Not mentioning the vast array of EDA tools needed to design FGPA or ASIC designs,the paper has focused upon the design issues and tradeoffs that must be kept in mind while implementing a design in silicon. It is not always easily visualised if a design could be implemented as an

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