Procedural Analog Design (PAD) Tool Users Manual

Procedural Analog Design (PAD) Tool is a chart-based design tool dedicated to the design of analog circuits aiming to optimise design and quality by finding good tradeoffs of basic analog structures. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog structure. At each step, one subset of design parameters can be changed interactively and the effect on other circuit parameters can be observed. An optimised design is ready for simulation (verification and fine-tuning). PAD provides a layout generator for transistor cells and matched structures, such as: current mirror, differential pair. The analog basic structures calculator uses complete set of equations of EKV MOS model, which links the equations for weak and strong inversion in a continuous way.

What can be designed?

The present version of PAD covers: 1) design and sizing of basic analog structures: NMOS transistor cell PMOS transistor cell N current mirror P current mirror N differential pair P differential pair N cascode mirror P cascode mirror N cascode stage P cascode stage N cascode pair P cascode pair N folded cascode pair P folded cascode pair 2) procedural analog design of complex analog structures: OTA Miller OpAmp Folded Cascode OTA

Start PAD tool

Double click the program icon.

Choose basic or complex analog structure (that will be designed) from the list and click OK (or double click the item in the list).

Follow step-by-step design of analog structures by using guidelines for each analog topology.

In every step two windows are displayed on the screen: the explication window with the guidelines and explications the design window with the appropriate graphical representations

For normal view the explication window + the design window, click Normal view: on the Standard toolbar. For design window on top the explication window is hidden under the design window, click Design Window on top: on the Standard toolbar. For the navigation use: The buttons Next / Previous in the explanation window or on the Standard toolbar. Reset button will reset all parameters to default values.

To create a new design: On the File menu, click New, choose basic or complex analog structure from the list and click OK (or double click the item in the list) or Click New on the Standard toolbar, choose basic or complex analog structure from the list and click OK (or double click the item in the list)

Save and Open design

To save a design: click Save folder. In the File name box, type a name for the design. The design is saved as name.pad. on the Standard toolbar, locate and open the

To open a design: On the File menu, click Open, locate and open the folder in which the design was saved, double click the design you want to open or Click Open on the Standard toolbar, locate and open the folder in which the design was saved, double click the design you want to open

Basic analog structure design and sizing

Basic analog structure design and sizing consists of two steps: initialisation design and sizing Initialisation Enter EKV model parameters and the bias information (supply voltages, bias voltages, bias current) that depends on basic analog structure.
EKV model params

the bias information and the basic analog structure scheme

Design and sizing The user interface has the same appearance, for every basic analog structure.
terminal voltages saturation voltages threshold voltages scheme

geometrical dimensions: W L W/L bias current(s) general parameters specific parameters layout generation

DC voltages and currents and geometrical dimensions can be changed interactively. When the parameters value is changed, it is possible to choose how this change will be performed. This will be explained in details in transistor cell sizing. At the same time, general and specific parameters are calculated and displayed in form of appropriate graphical representations. General parameters are parameters that are defined and calculated for simple transistor cell. Specific parameters are defined and related to the behaviour of other basic analog structures. All these parameters are displayed and

classified in form of cards: params, noise, mismatch, small signal params, speed, etc. This will be explained for each basic analog structure. Card layout is for layout generation. (See transistor cell.)

It is possible to change displayed parameters range, if a slider is used as a graphical representation. Click the minimum/maximum range value and a dialog will be displayed on the screen:

Enter a new value and click OK.

NMOS / PMOS transistor cell Initialisation Enter EKV model parameters, terminal voltages (gate, drain, source and bulk voltages) and transistor width and length. Users interface

DC params All terminal voltages Vg, Vs, Vd, Vb can be changed. Respect Vd > Vs for NMOS, and Vs >Vd for PMOS transistor. Threshold voltage and saturation voltage are calculated and indicated. For PMOS transistor a negative sign is given for these voltages. By default, when the geometrical dimensions: transistor width, transistor length and W/L ratio are changed, the transistor current is

considered constant and the change influence voltage Vg. Following options are possible: if W (L) is changed

to Vg, Idsat constant (default) Idsat is considered constant and the change influence Vg W/L constant the ratio W/L is kept constant, a new value for L (W) is calculated W/L variable Vg is considered constant, a new value for Idsat is calculated (and a new value for the ratio W/L is calculated) if the ratio W/L is changed

to Vg, L const (default) Idsat is considered constant and the change influence Vg (L is kept constant, a new value for W is calculated) to Vg, W const Idsat is considered constant and the change influence Vg (W is kept constant, a new value for L is calculated) W constant Vg is considered constant, a new value for Idsat is calculated (W is kept constant, a new value for L is calculated)

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L constant Vg is considered constant, a new value for Idsat is calculated (L is kept constant, a new value for W is calculated) If W < Wmin or L < Lmin, the warning is displayed!

the indication of weak/moderate/strong inversion the indication of linear/saturation region Transistor drain current Id and transistor saturation drain current Idsat are calculated and displayed. If Idsat < 1pF, too small current, the warning is displayed! If a new value for the current is calculated or the current is changed that refers to Idsat. The value of the voltage Vd determines if the transistor is in linear region or in saturation region, and the corresponding value for Id is calculated. The blue area inside Id slider corresponds to Idsat value. If Idsat is changed following options are possible:

to Vg the geometrical dimensions are kept constant and a new value for the voltage Vg is calculated

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to Vg, Vd the same the transistor is considered like diode-connected and the corresponding voltage is calculated to L the voltage Vg is considered constant and a new value for transistor length is calculated to W the voltage Vg is considered constant and a new value for transistor width is calculated to W/L, L const the voltage Vg is considered constant and a new value for the ratio W/L is calculated, where L is kept constant to W/L, W const the voltage Vg is considered constant and a new value for the ratio W/L is calculated, where W is kept constant General parameters params: gm/Idsat Early voltage E A =
I dsat g ds n g m Vt I dsat

transcoductance efficiency factor tef =

graph transcoductance efficiency factor tef in function of inversion factor if

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red point traces parameters changes clear deletes white trace, red point will stay in the current position

noise: thermal noise v _ thermal = 4kT qi flicker noise v _ flic ker =

1 2 gm

KF Weff Leff COX f

AF

equivalent noise v _ eq = v _ thermal 2 + v _ flic ker 2 corner frequency small signal params : transcoductances gm, gds, gmbs gain - gm/gds(dB) output resistance 1/gds inversion factor (the value and the indication) speed: intrinsic capacitances Cgs, Cgd, Cgb, Csb, Cdb overlap capacitances Cgsov, Cgdov, Cgbov transition frequency ft =
gm 2C gs

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Layout generation

transistor width transistor length number of devices in case of long L (W) layout type (for transistor cell only) area

redraw to redraw the layout when geometrical dimensions are changed export to export the current version in the buffer

The layout is automatically generated. When the transistor dimensions are changed, click redraw button to redraw a new layout version. To export the current layout version click export button and it will be saved in the internal buffer. This can be repeated as many times as it is needed. All exported versions of the layout (one by one, in the order in which they were exported) are saved in the internal buffer. But, the exported layout will be saved only if CIF file is created and saved. To save exported layout click Define CIF file name: on the Standard toolbar In the CIF File name box, type a name and click OK. then click Save CIF file: on the Standard toolbar to save CIF file. After this action, generated layout is exported and saved and can be imported in any layout editor. To empty the internal buffer click Empty buffer:

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on the Standard toolbar.

In the present tool version it is not possible to change the setup for layout
generation.

N / P current mirror
Initialisation Enter EKV model parameters, the supply voltages, the bias current, current mirror ratio (the ratio between mirrored current and bias current) and transistor width and length. Users interface

Following parameters can be changed: the bias current, current mirror ratio and the width and length of transistor mb.

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General parameters See general parameters for the transistor cell.

Specific parameters mismatch:

g 2 ) = + m T2 , Id Id in % A Avt T = , = WL WL

Id

current mismatch

I =

) Id Id in uA 100

Id

graph current mismatch in function of inversion factor if

small signal params: current mirror output resistance rout speed: capacitance seen in the gate of tran m1 Cg1 capacitance seen in the drain of tran m1 Cd1

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Layout generation

see transistor cell

N / P differential pair
Initialisation Enter EKV model parameters, the supply voltages, the drain current and the input voltage. Users interface

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From the initial conditions the ratio W/L is proposed. Terminal voltages are always set like:
Vs = Vg Vth Vd = Vg + Vth

This condition enables to design with large dynamic. Following parameters can be changed: the drain current and transistor width and length. Following options are possible: if W (L) is changed

W/L constant the ratio W/L is kept constant, a new value for L (W) is calculated (the drain current is constant, terminal voltages change) W/L variable a new value for the ratio W/L is calculated (the drain current is constant, terminal voltages change) if W/L changed

L constant L is kept constant, a new value for W is calculated (the drain current is constant, terminal voltages change)

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W constant W is kept constant, a new value for L is calculated (the drain current is constant, terminal voltages change) General parameters See general parameters for the transistor cell.

Specific parameters mismatch:

2 2 (Vg ) = T + , g m in mV voltage mismatch

Id A

T =

Avt

WL

, =

WL

graph voltage mismatch in function of inversion factor if Layout generation

see transistor cell

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N / P cascode mirror
Initialisation Enter EKV model parameters, the supply voltages, the drain current, transistor length and width and transistor length ratio n. Users interface

Transistor m1 and m2 are designed to be on the edge of saturation. For given transistor width and length, the voltage Vg1 is calculated. Transistor m3 and m4 are designed like:
W 3 = W1 L3 = n L1

For given terminal voltages and drain current, the voltage Vbias is calculated.

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Following parameters can be changed: the drain current, transistor m1(m2) width and length and transistor length ratio n. General parameters See general parameters for the transistor cell.

N / P cascode stage
Initialisation Enter EKV model parameters, the supply voltages, the drain current and the input voltage. Users interface

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From the initial conditions the ratio (W/L)1 is proposed, where terminal voltages are always set like:
Vg1 = Vs1 + Vth1 Vd1 = Vs1 + Vds sat 1 Vs3 = Vd1

For given drain current and ratio (W/L)3 the voltage Vbias is calculated. Following parameters can be changed: transistors widths and lengths, the input voltage and the drain current. Following options are possible for both transistors: if W (L) is changed

W/L constant the ratio W/L is kept constant, a new value for L (W) is calculated (the drain current is constant, a new value for Vbias is calculated) W/L variable a new value for the ratio W/L is calculated (the drain current is constant, a new value for Vbias is calculated) if W/L changed

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L constant L is kept constant, a new value for W is calculated (the drain current is constant, a new value for Vbias is calculated) W constant W is kept constant, a new value for L is calculated (the drain current is constant, a new value for Vbias is calculated)

General parameters See general parameters for the transistor cell. Specific parameters small signal params: cascode stage output resistance rout =
1 g g g m3 g ds1 g ds 3

gain (approximation) A = m1 m3 2 g ds1 g ds 3

speed: input capacitance Cin

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N / P cascode pair
Initialisation Enter EKV model parameters, the supply voltages, the drain current, the input and the bias voltage. Users interface

From the initial conditions the ratio (W/L)1 is proposed, where terminal voltages are always set like:
Vg1 = Vin Vs1 = Vg1 Vth1 Vd1 = Vg1 + Vth1 Vs3 = Vd1 Vg 3 = Vbias

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The ratio (W/L)3, as well as input and bias voltages can be changed interactively. (Always check the mode of operation, the polarisation and the transcoductances of all transistors). Following options are possible for both transistors: if W (L) is changed

W/L constant the ratio W/L is kept constant, a new value for L (W) is calculated W/L variable a new value for the ratio W/L is calculated if W/L changed

L constant L is kept constant, a new value for W is calculated W constant W is kept constant, a new value for L is calculated

General parameters See general parameters for the transistor cell.

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Specific parameters mismatch:

2 2 (Vg ) = T + , g m in mV voltage mismatch (input pair)

Id A

T =

Avt

WL

, =

WL

graph voltage mismatch in function of inversion factor if

small signal params: cascode stage output resistance rout =

1 g g g m3 g ds1 g ds 3

gain (approximation) A = m1 m3 2 g ds1 g ds 3

speed: input capacitance Cin

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N / P folded cascode pair

Initialisation Enter EKV model parameters, the supply voltages and the input currents. Users interface

From the initial conditions the ratio (W/L)1 is proposed, where terminal voltages are always set like:
Vdd Vss Vin = 2 Vg1 = Vin Vs1 = Vg1 Vth1 Vd1 = Vg1 + Vth1 Vs3 = Vd1

For given drain current and ratio (W/L)3, the voltage Vbias is calculated.

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Following parameters can be changed: transistors widths and lengths and the drain currents. Following options are possible for both transistors: if W (L) is changed

W/L constant the ratio W/L is kept constant, a new value for L (W) is calculated (the drain currents are constant, a new value for Vbias is calculated) W/L variable a new value for the ratio W/L is calculated (the drain currents are constant, a new value for Vbias is calculated) if W/L changed

L constant L is kept constant, a new value for W is calculated (the drain currents are constant, a new value for Vbias is calculated) W constant W is kept constant, a new value for L is calculated (the drain currents are constant, a new value for Vbias is calculated) General parameters See general parameters for the transistor cell.

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Specific parameters mismatch:

2 2 (Vg ) = T + , g m in mV voltage mismatch (input pair)

Id A

T =

Avt

WL

, =

WL

graph voltage mismatch in function of inversion factor if

small signal params: cascode stage output resistance rout =

1 g
g g m3 g ds1 g ds 3

gain (approximation) A = m1 m3 2 g ds1 g ds 3

speed: pole (approximation) f _ pole = input capacitance Cin

g m3 2 2C gs 3

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Procedural analog design of complex structures

Present PAD version covers analog design of following complex analog structures: OTA Miller Amplifier Folded Cascode

Procedural analog design for each analog structure consists of: initialisation circuit partitioning basic analog structures sizing circuit summary

Initialisation The user is asked to enter NMOS and PMOS EKV model parameters and the information for circuit initialisation (initial design requirements, the supply voltages, the bias current, load and compensation capacitances).

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scheme of analog structure

supply voltages bias current

initial design requirements: SR GBW power dissipation

load capacitance compensation capacitance

Circuit partitioning The circuit partitioning sequence (into basic analog structures) and the equation set (that describes circuit behavior) are proposed for every complex structure. Follow guidelines and explanations for every design step. Basic analog structures sizing From the initial design requirements, the values for some circuit parameters will be proposed. For each block, using the same procedure as described in Basic analog structure design and sizing, the user can modify parameters and observe impact of his decisions on circuit performances. Circuit summary Circuit performance can be checked, during and after sizing of each block.

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circuit performances can be checked and compared with initial design requirements

Following circuit parameters are calculated: gain CMRR PSRR equivalent input noise, corner frequency offset voltage positive / negative CMR output swing SR GBW power dissipation phase margin Frequency analysis is proposed, after basic analog structures design steps.

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the approximations for poles and zeros

phase margin in function of Cc (or Cl)

After having designed all building blocks, circuit level behavior is summarized.

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OTA design

Read the introduction, and follow proposed procedure and guidelines in the program.

Circuit scheme and proposed partitioning for n input OTA:

VDD

3
A B

2 1

VSS

Design sequence is following: 1. n current mirror 2. n differential pair 3. p current mirror

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 Circuit scheme and proposed partitioning for p input OTA:

3
A

Design sequence is following: 1. p current mirror 2. p differential pair 3. n current mirror

Circuit-level design equations:

slew rate gain bandwidth frequency gain positive/negative CMR
A=
I1 CL
g m1 2 CL

SR =

f _ GBW =

g m1 g ds1 + g ds 4

(n input) (p input)

CMR + = V dd V th 3 + V ds _ sat 3 V ds _ sat 2 + Vth 2 CMR = V ss + V ds _ sat 5 + Vth 2 CMR + = Vdd Vds _ sat 5 Vth 2 CMR = Vss + Vth 3 + Vds _ sat 3 + Vds _ sat 2 Vth 2

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output swing

(n input)

Vout _ swing = Vdd Vss Vds _ sat 3 Vds _ sat 1 Vds _ sat 5

(p input)
CMRR current mismatch (curr mirr) voltage mismatch (diff pair) equivalent noise

Vout _ swing = Vdd Vss Vds _ sat 3 Vds _ sat 1 Vds _ sat 5

CMRR = 2
Id
Id

g m1 g m 4 g ds 5 g ds 4

g 2 ) = + m T2 , Id A A T = vt , = WL WL

2 2 (Vg ) = T + , g m

Id A

T =

Avt WL

, =
2

WL
2

v _ eq2 = v _ eq1 + v _ eq2

2

g 2 2 + m4 v _ eq3 + v _ eq4 g m1

input offset

g 2 2 2 Voff = ( (Vg1 )) + m4 ( (Vg 4 )) g m1 I 2 2 = T + D g m A A T = Vt , = WL WL

( (V ))
g

pole estimations and phase margin

f _ pA =

gm3 g + gds4 , f _ pB = ds1 CA CB

f _ GBW f _ GBW PM = 180 arctg f _ p arctg f _ p ) A B

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Miller OpAmp design

Read the introduction, and follow proposed procedure and guidelines in the program.

Circuit scheme and proposed partitioning n input Miller Op Amp:

V DD

3
A B D

2 1

V SS

Design sequence is following: 1. n current mirror 2. n differential pair 3. p current mirror 4. output stage

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 Circuit scheme and proposed partitioning p input Miller Op Amp:

V DD

B A

4
VSS

Design sequence is following: 1. p current mirror 2. p differential pair 3. n current mirror 4. output stage

Circuit-level design equations:

slew rate gain bandwidth frequency power dissip gain
PowDissip
A=
I1 Cc

SR =

f _ GBW =

g m1 2C c

= (V dd V ss )( I o + I 1 + I 2 )
g m1 g m6 g ds1 + g ds 4 g ds 6 + g ds 7

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positive/negative CMR

(n input) (p input)

CMR + = V dd V th 3 + V ds _ sat 3 V ds _ sat 2 + Vth 2 CMR = V ss + V ds _ sat 5 + Vth 2 CMR + = Vdd Vds _ sat 5 Vth 2 CMR = Vss + Vth 3 + Vds _ sat 3 + Vds _ sat 2 Vth 2

output swing

(n input)

Vout _ swing = Vdd Vss Vds _ sat 6 Vds _ sat 7

(p input)
CMRR

Vout _ swing = Vdd Vss Vds _ sat 7 Vds _ sat 6

CMRR = 2

g m1 g m 4 g ds 5 g ds 4

PSRR+/PSRR-

PSRR = PSRR + =

g m1 g m 6 ( g ds1 + g ds 4 ) g ds 7 g m1 g m 6 ( g ds1 + g ds 4 ) g ds 6

current mismatch (curr mirr) voltage mismatch (diff pair) equivalent noise

g 2 ) = + m T2 , Id A A T = vt , = WL WL

Id
Id

2 (Vg ) = T +

Id 2 , gm A WL
2

T =

Avt WL

, =

g 2 2 2 2 v _ eq2 = v _ eq1 + v _ eq2 + m4 v _ eq3 + v _ eq4 g m1 g 2 v _ eq2 v _ eq6 + m7 7 g m6 + 2 gm1 ( g + g ) ds1 ds 4

2

input offset

g 2 2 2 Voff = ( (Vg1 )) + m4 ( (Vg 4 )) g m1 I 2 2 = T + D g m A A T = Vt , = WL WL

( (V ))
g

pole estimations and phase margin

f _ pA =

gm3 , f _ pB = CA

f PM = 180 arctg

gds1 + gds4 g m6 g , f _ pD = , f _ z = m6 CD + CC CC g m6 CB + Cc g +g ds7 ds6 f _ GBW _ GBW 3 arctg f _ p ) f _ z i =1 i

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Folded Cascode OTA design

Read the introduction, and follow proposed procedure and guidelines in the program.

Circuit scheme and proposed partitioning for p input Folded Cascode OTA:
VDD

3 2

VSS

Design sequence is following: 1. p current mirror (bias 1) 2. n current mirror (bias 2) 3. folded cascode pair 4. cascode current mirror 5. bias 3 6. bias 4

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 Circuit scheme and proposed partitioning for n input Folded Cascode OTA:
VDD

2 3

VSS

Design sequence is following: 1. n current mirror (bias 1) 2. p current mirror (bias 2) 3. folded cascode pair 4. cascode current mirror 5. bias 3 6. bias 4

Circuit-level design equations:

slew rate gain bandwidth frequency
Io CL
g m1 2 CL

SR =

f _ GBW =

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power dissipation gain

PowDissip = (Vdd Vss ) (2 I1 + 2 I bias + I bias1 + I bias 2 )

A=

gm1 g g g (g + g ) , gox = ds8 ds10 , goy = ds6 ds1 ds4 gox + goy gm8 gm6

positive/negative CMR

p input n input

CMR + = Vdd Vds _ sat17 Vth1 CMR = Vss + Vds _ sat 4 + Vds _ sat1 Vth1 CMR + = Vdd Vds _ sat 4 Vds _ sat1 + Vth1 CMR = Vss + Vds _ sat17 + Vth1
V out _ swing =

output swing

p input

V dd V ss V ds _ sat 8 + V ds _ sat 10 + V ds _ sat 6 + V ds _ sat 4

n input
equivalent noise

Vout _ swing =

Vdd Vss Vds _ sat 8 + Vds _ sat 10 + Vds _ sat 6 + Vds _ sat 4
v _ eq2 = v _ eq1 + v _ eq2
2 2 2

g g 2 2 2 2 + m 4 v _ eq3 + v _ eq4 + m9 v _ eq9 + v _ eq10 g g m1 m1

input offset

g 2 2 Voff = ( (Vg1 )) + m9 ( (Vg 9 ))2 g m1 Id 2 2 = T + g m A A T = Vt , = WL WL

( (V ))
g

pole estimations and phase margin

f _ p1 =

g ox + g oy CL

, f _ p2 =

g m6 Cgs6 + Cd 4 + Cd1

f _ GBW f _ GBW PM = 180 arctg f _ p arctg f _ p ) 1 2

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