AHB to APB Sheet (AHB2APB) Technical Data Bridge

Technical Data Sheet

Part Number:
Document Number: March 2007

T-CS-PR-0005-100
I-IPA01-0106-USR Rev 05

AHB to APB Bridge (AHB2APB)

2003 Cadence Design Systems, Inc. All rights reserved Proprietary Notice
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Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet

AHB to APB Bridge (AHB2APB)

1.

Features
Interfaces between the AMBA high performance bus (AHB) and AMBA peripheral bus (APB) (AMBA Specification, Revision 2.0) Provides latching of address, control and data signals for APB peripherals Support for the following: APB compliant slaves and peripherals Peripherals which require additional wait states Peripherals which require byte, half-word and word accesses on APB bus The design RTL can be parameterized to have a lower number of peripherals with support for up to 16 slaves on the APB side Big-endian and little-endian modes

2.

Description

The AHB2APB interfaces the AHB to the APB. It buffers address, control and data from the AHB, drives the APB peripherals and returns data and response signals to the AHB. It decodes the address using an internal address map to select the peripheral. The AHB2APB is designed to operate when the APB and AHB clocks have the same frequency and phase. In addition to supporting all basic requirements for AMBA compliance, the AHB2APB provides enhancements to the APB protocol. With AHB2APB, an APB peripheral can insert wait states by holding its pready signal low for the required number of cycles. In the AMBA specification, APB accesses are word-wide (32 bits). The AHB2APB provides the signal pbyte_enable[3:0] to allow byte and half-word accesses. These can be used by the APB peripheral as necessary. The AHB2APB does not perform any alignment of the data, but transfers data from the AHB to the APB for write cycles and from the APB to the AHB for read cycles. The AHB2APB does not support burst transfers and converts any burst transfers into a series of APB accesses. The AHB slave interface supplied by the AHB2APB does not make use of the split response protocol.

3.
3.1.

Operation
AHB Response

The sub-module AHB response sequences the way that the AHB2APB responds to AHB requests. Valid commands are forwarded to control transfer for action. Invalid commands are not forwarded and an error response generated. It operates on AHB clock and reset.

3.2.

Control Transfer

Control transfer transfers the AHB control signals to the APB access with appropriate delays inserted to map the pipelined AHB protocol to the two cycle APB protocol. It ensures that only one request is presented to the APB access while APB access is processing a request. It operates on AHB clock and reset.

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet

3.3.

APB Access

APB access generates the control signals on the APB for read and write cycles. It operates on the APB clock and reset.

3.4.

PRDATA MUX

The block prdata mux receives data read from all the APB slaves and transfers the data from the selected peripheral to the AHB.

3.5.

PREADY OR

The block pready or produces the logical OR of the pready signals generating a common pready that is used to help sequence AHB response and APB access.

4.

Block Diagram
c_bigendian

hwdata[31:0] hready hresp[1:0] pclk hsel haddr[31:0] hwrite AHB Interface htrans[1:0] hsize[2:0] AHB Response Control Transfer APB Access APB Interface pready PREADY OR psel_xx hrdata[31:0] PRDATA MUX prdata_xx[31:0] n_preset pwdata[31:0] pwrite paddr[31:0] pbyte_enable[3:0] psel_xx penable writeOn

hready_in n_hreset hclk

pready_xx

Note: xx has a value between 00 and 15. This value represents the slave number.

5.

Signal Interfaces
AMBA Advanced High Speed Bus (AHB) slave interface AMBA Advanced Peripheral Bus (APB) master interface Configuration interface

The AHB2APB includes the following signal interfaces:

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet

5.1.

AMBA AHB Slave Interface

hclk n_hreset hsel haddr[31:0] hsize[2:0] htrans[1:0] hwdata[31:0] hwrite hready_in AHB Slave Interface hrdata[31:0] hready hresp[1:0]

Signal Name n_hreset hsel haddr[31:0 ] hwrite htrans[1:0 ] hsize[2:0] hwdata[31: 0] hclk hready_in hready hresp[1:0] hrdata[31: 0]

I/O I I I I I I I I I O O O

Function AHB reset (active low, asynchronous to hclk) AHB slave select (from address decode) AHB address bus AHB write/read strobe AHB transfer method AHB size of transfer AHB write data AHB clock AHB bus access by last master finished AHB ready response from the AHB2APB AHB response from the AHB2APB AHB read data from the AHB2APB

5.1.1.

AHB Timing Characteristics

The following characteristics have been set as the default values for the synthesis of the module with the values in the table below being achieved with typical 0.25 m technology. Parameter Tclk Tclkh Clock period, T0 Clock high Description Min 10 40 to 60% Max DC Unit ns T0

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet Tclkl Tihsel Tissel Tihtr Tistr Tohrdy Tovrdy Tihrdy Tisrdy Tiha Tisa Tihctl Tisctl Tihwd Tiswd Tohrsp Tovrsp Tohrd Tovrd Clock low hsel hold after hclk hsel setup before hclk htrans hold after hclk htrans setup before hclk hready hold after hclk hready valid after hclk hready_in hold after hclk hready_in setup before hclk haddr hold after hclk haddr setup before hclk hwrite, hsize hold after hclk hwrite, hsize setup before hclk hwdata hold after hclk hwdata setup before hclk hresp hold after hclk hresp valid after hclk hrdata hold after hclk hrdata valid after hclk assuming an input delay of 7 ns for prdata 0.5 8.22 0.5 3.22 0.5 3.22 0.5 3.22 0.5 3.22 0.5 3 40 to 60% 0.5 3.22 0.5 3.22 0.5 3 T0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note 1:

All timings are specified relative to the target clock period, Tclk. These are coded into the synthesis script provided. These timings have been achieved with a typical technology, but are for guidance only

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet

Tclk hclk Tissel hsel Tistr htrans
NONSEQ

Tclkh Tclkl

Tihsel

Tihtr

Tovrdy Tohrdy hready Tisrdy hready_in Tisa haddr Tisctl hwrite, hsize Control Tiswd hwdata Tovrsp hresp OKAY Tovrd hrdata
Data (A)

Tihrdy

Tiha A Tihctl

Tihwd Data (A) Tohrsp OKAY Tohrd

. Note 2: Minimum timings are specified as an absolute value. These are coded into the synthesis script provided. These timings should be achievable, but depend on the technology used and are for guidance only.

5.2.

AMBA APB Master Interface

pwdata[31:0] pclk n_preset prdata_xx[31:0] pready_xx APB Master Interface pwrite paddr[31:0] psel_xx pbyte_enable[3:0] penable Note: xx has a value between 00 and 15. This value represents the slave number.

Signal Name pclk

I/O I I I

Function APB clock must be the same frequency and phase as the AHB hclk APB reset (active low) APB read data from slave 1 to slave 16

n_preset prdata_xx[31:0]

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet pready_xx pwdata[31:0] pwrite paddr[31:0] psel_xx pbyte_enable[3: 0] penable Note: I O O O O O O APB ready signal from slave 1 to slave 16 APB write data APB read/write strobe APB address bus APB slave select for slave 0 to slave 15 Byte enable signal for byte/half-word access APB enable

pready_xx and pbyte_enable[3:0] are enhancements to the APB protocol.

5.2.1.

APB Timing Characteristics

The following characteristics have been set as the default values for the synthesis of the module. Parameter Tclk Tclkh Tclkl Tohpsel Tovpsel Tihprdy Tisprdy Tohpen b Tovpen b Tohaddr Tovaddr Tohpwr Tovpwr Tohpbyt Tovpbyt Tihprd Tisprd Description Clock period (T0) Clock high Clock low psel hold after pclk psel valid after pclk pready hold after pclk pready setup before pclk penable hold after pclk penable valid after pclk paddr/pwdata hold after pclk paddr/pwdata valid after pclk pwrite hold after pclk pwrite valid after pclk pbyte_enable hold after pclk pbyte_enable valid after pclk prdata hold after pclk prdata setup before pclk 0.5 3.22 0.5 3 0.5 3 0.5 3 0.5 3.22 0.5 3 Min 10 40 to 60% 40 to 60% 0.5 3 Max DC Unit ns Tclk or T0 Tclk ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet

Note 1:

Maximum timings are specified relative to the target clock period, Tclk. These are coded into the synthesis script provided. These timings have been achieved with a typical technology, but are for guidance only
Tclk pclk Tovpsel psel Tisprdy pready Tovpenb penable Tovaddr Tohaddr Tohpenb Tihprdy Tohpsel Tclkh Tclkl

paddr, pwdata Tovpwr pwrite Tovpbyt pbyte_enable Tisprd prdata Tihprd Tohpbyt Tohpwr

Note 2:

Minimum timings are specified as an absolute value. These are coded into the synthesis script provided. These timings should be achievable, but depend on the technology used and are for guidance only.

5.3.

Configuration Interface

The AHB2APB can be programmed to operate in big-endian or little-endian mode. When the input c_bigendian is high, the AHB2APB operates in big-endian mode and when c_bigendian is low, the AHB2APB operates in little-endian mode.

Signal Name c_bigendi an

I/O I

Function Configures the endian mode

5.3.1.

Configuration Timing Characteristics

The following characteristics have been set as the default values for the synthesis of the module.

Parameter Tclk

Description Clock period (T0)

Min 10

Max DC

Unit ns

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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AHB2APB Technical Data Sheet Tclkh Tclkl Tihcbe Tiscbe Clock high Clock low c_bigendian hold after pclk c_bigendian hold after pclk 40 to 60% 40 to 60% 0.5 3.22 Tclk or T0 Tclk ns ns

Note 1:

Maximum timings are specified relative to the target clock period, Tclk. These are coded into the synthesis script provided. These timings have been achieved with a typical technology, but are for guidance only.
Tclk hclk Tiscbe c_bigendian Tihcbe Tclkh Tclkl

Note 2:

Minimum timings are specified as an absolute value. These are coded into the synthesis script provided. These timings should be achievable, but depend on the technology used and are for guidance only.

6.

Physical Estimates
1500 for 10 peripherals configuration 200 for 10 peripherals configuration 608 123

Gate count FF count SOC-Internal pins (in) SOC-Internal pins (out)

7.

Verification

All our IP modules are verified to one of the following levels: Gold IP has been to target silicon. Silver P has been to silicon in FPGA. Bronze IP has been verified in silicon with logical timing closure. In development IP has not yet been verified. Please contact the IPGallery (ipgallery@cadence.com) for the latest verification information.

8.

Deliverables

The full IP package comes complete with: Verilog HDL Cadence RC synthesis scripts with SDC contraints Verilog testbench AHB2APB Users Guide with full programming interface, parameterization instructions and synthesis instructions.

Document No: I-IPA01-0106-USR Rev 05, March 2007 2003 Cadence Design Systems, Inc.

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