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TYPE IRF740
s s s s s
V DSS 400 V
ID 10 A
TYPICAL RDS(on) = 0.48 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED
DESCRIPTION This power MOSFET is designed using the companys consolidated strip layout-based MESH OVERLAY process. This technology matches and improves the performances compared with standard parts from various sources. APPLICATIONS HIGH CURRENT SWITCHING s UNINTERRUPTIBLE POWER SUPPLY (UPS) s DC/DC COVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT.
s
3 1 2
TO-220
Value 400 400 20 10 6.3 40 125 1.0 4.0 -65 to 150 150
Unit V V V A A A W W/ o C V/ns
o o
C C
() Pulse width limited by safe operating area ( 1) ISD 10 A, di/dt 120 /s, VDD V(BR)DSS, Tj TJMAX First Digit of the Datecode Being Z or K Identifies Silicon Characterized in this Datasheet
October 1998
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IRF740
THERMAL DATA
R thj-case
Rthj-amb
R thc-sink Tl
Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose
AVALANCHE CHARACTERISTICS
Symbol IAR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max) Single Pulse Avalanche Energy (starting T j = 25 o C, I D = I AR , V DD = 50 V) Max Value 10 520 Unit A mJ
Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = 20 V
T c = 125 o C
ON ()
Symbol V GS(th) R DS(on) I D(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance V DS = V GS V GS = 10V Test Conditions I D = 250 A I D = 5.3 A 10 Min. 2 Typ. 3 0.48 Max. 4 0.55 Unit V A
DYNAMIC
Symbol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions V DS > I D(on) x R DS(on)max V DS = 25 V f = 1 MHz ID = 6 A V GS = 0 Min. 5.8 1400 220 27 Typ. Max. Unit S pF pF pF
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IRF740
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions V DD = 200 V ID = 5 A VGS = 10 V R G = 4.7 (see test circuit, figure 3) V DD = 320 V ID = 10.7 A V GS = 10V Min. Typ. 17 10 35 11 12 43 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions V DD = 320 V ID = 10 A R G = 4.7 V GS = 10 V (see test circuit, figure 5) Min. Typ. 10 10 17 Max. Unit ns ns ns
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % () Pulse width limited by safe operating area
Thermal Impedance
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IRF740
Output Characteristics
Transfer Characteristics
Transconductance
Capacitance Variations
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IRF740
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IRF740
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
6/8
IRF740
D1
L2
F1
G1
Dia. L5 L7 L6 L4
P011C
L9
F2
H2
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IRF740
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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