PULL nano 30 News from the European 32/22nm CMOS Research pool at month 30 December 2008

32nm EU reference project delivers !

After 30 months of hard work, the Pullnano project has successfully
achieved the development of a 32nm CMOS technology in Europe. The Stéphane Monfray
highly motivated consortium of 38 partners releases its final results : works in the Ad-
three functional demonstrators validating the 32nm technology, the vanced Devices
definition of suitable approaches for the future 22nm node, transistor Research team at
architecture simulation and statistical variability assessments in 32 and STMicroelectro-
22nm, and the creation of a forum for european equipment nics and coordina-
suppliers. Scanning results vs initial Pullnano's objectives. ted the 32nm
technology feasibi-
e l e c t r o n i c s

lity subproject in
The limits of miniaturization have Pullnano : « The
not yet been reached ! feasibility of the chosen thin film technology so-
lutions and the FDSOI and FinFET architectures
In charge of Pullnano's first objective, subproject 8 has some "world’s
has been demonstrated, and the results show a
firsts" demonstrators to its credits. Highlights by Stephane Monfray
from STMicroelectronics and SP8 coordinator. further scale reduction potential down to 22nm,
and even to 16nm. »
Can we safely talk about a full success re- the alignment between levels of lithography mo-
garding the major objectives of Pullnano ? dules, as we work at the limits of what's techni-
As announced at the IEDM 2007 conference, cally possible with the available equipments.
we demonstrated, for the first time, the func- The FDSOI device was made via e-beam litho-
tionality of a 0,179 µm2 6T-SRAM bitcell, the graphy on a Vistec SB350 in Crolles (France). It
N a n o C M O S

smallest SRAM cell size ever obtained with a
High K dielectric/metal gate architecture on a
fully depleted Silicon on Insulator (FDSOI) de-
vice. At this year's IEDM, the consortium will
present a similar sized 6T SRAM cell based on
a multigate FET architecture, i.e. a FinFET, thus
demonstrating the successful patterning of
very challenging structures at gate level in the
32nm technology node. Thin films devices are
one of the most promising solutions for sub
o f
features a HfSiON/TiN gate stack. The FinFET
device was fabricated at IMEC with an advan-
ced immersion lithography technique on a
TwinScan 1700i (193nm) from ASML ... and with
next generation EUV lithography for the contact
openings. Among the many challenges figured
also the processing of thin films with just C.Fenouillet-Beranger et al, IEDM07
10nm thickness (or
less) and the epitaxially The 0,179 µm2 FDSOI
SRAM bitcell was presented
raised source and drain at IEDM 2007. A world first in

45nm CMOS, thanks to their improved short regions for the FDSOI size and technology, it fea-
channel behaviour and low leakage currents. In devices, or the skills of tures a HfSiON/TiN gate
stack, a 10 nm Silicon thin
both cases, our strategy aimed at low power etching the very thin film and epitaxially raised
l i m i t s

consumption. We also achieved a BEOL de- fins – i.e. the vertical source and drain regions.
monstrator featuring an Ultra Low K dielectric 20nm membranes (see Next generation EUV-litho-
(with k = 2.3) as insulator between the metal in- the photograph on graphy has been used to
terconnexion layers (using a damascene struc- page 2) – in the FinFET etch open the contact holes
in the FinFET device at
ture with 32nm design rules) in order to obtain devices. IMEC.
the lowest possible delay. A.Veloso et al, IEDM08
t h e

Which process steps were the most chal- Table of contents

lenging to achieve ?
Different subprojects of Pullnano worked on Edito / Dr Dominique Thomas p2.
various technology modules, which were then Interview / Dr Gilles Thomas : “The human story behind the
P u l l i n g

integrated to demonstrate the feasibility of the

process with the respect of 32nm design rules.
An intense interaction between the subprojects
was mandatory, notably between those dedi-
cated to materials, architecture and simulation.
The most difficult task was probably to master
technology gains momentum” p4.
Prospective / And now, a step toward tomorrow ? p5.
Focus / Breakthrough in strain metrology with new
electron holographic technique p6.
On the system level power estimation p3.
1

EDITORIAL
PULLNANO : Building an
efficient European R&D
ecosystem in Nanoelectronics.
PULLNANO (2006-2008) benefited from the
excellent collaboration initiated by the core
group of partners present in NANOCMOS
(2004-2006) to which were incorporated 17
additional academic partners and later 3
SMEs. Thanks to a structured organisation
based on a combination of geographical and
topical cooperation sub-groups, this large
consortium evolved into an efficient ecosys-
tem contributing to create the condition for the
emergence of a manufacturing capability in 32
nm CMOS technology in Europe.
The sheer number of joint deliverables, multi-
partner publications and conference talks,
workshop and training lectures, wafer ex-
changes, workpackage / subproject and pro-
ject meetings is tantamount.
These include several presentations at confe-
rences such as IEDM, and results such as the
first 32-nm SRAM on fully depleted SOI, some
world’s firsts in finFETs and also stress cha-
racterization techniques, to name just a few.
The Pullnano project has created an incredi-
ble network of excellent teams and individuals
capable of generating state of the art know-
ledge and know-how; thus maintaining Eu-
rope at the leading edge of a very competitive
technological field.
The Pullnano dynamics will live on in further
cooperative projects including the ENIAC JTI
framework or Eurêka/CATRENE and extend
its reach from “More MOORE” to “More Than
MOORE” and “heterointegration” technolo-
gies. The Board of Pullnano would like to
thank all the partners of the project, and es-
pecially its coordinator, for their excellent work
and dedication during the course of this exci-
ting endeavour.
CONGRATULATIONS !
Dr Dominique Thomas
STMicrolectronics R&D Cooperative
Programs Director
2
Objective 2> To prepare the 22nm technology node
RESULTS
Large currents through narrow fins – FinFET
devices ready for the 22nm node
The second major objective of the Pullnano project is the assessment and demonstration of
suitable 22nm approaches in terms of materials, processes, integration and simulation in both
Front-End and Back-End of the line. Given the dimension of this challenge, the effort is evenly
distributed over many sub projects involving all major Pullnano players to benefit best of this
enormous competence network. One of the most important issues within this task is the
choice and demonstration of the 22nm device architecture that will have to fulfill both de-
manding performance and manufacturability criteria. Already for the 32nm node, Pullnano
made a big and ambitious leap forward by answering to the known limitations of bulk devices
by a successful demonstration of FDSOI devices that have an intrinsically better channel
control due to the confinement of the nano-scale Si channel by the underlying Buried Oxide.
For the 22nm node, Pullnano suggests to go even one step further: searching for ultimate
channel controllability, multi-gate device solutions are explored by several sites, such as Gate-
All-Around devices by ST, bonded Double Gate devices by the LETI and trigate FinFET de-
vices by NXP, IMEC and Infineon. Essential progress has been achieved within Pullnano on the
integration of the latter, with
well-controlled fins down to 5nm
now readily available giving ex-
cellent off-state control combi-
ned with very competitive
devices performances and, not
to forget, ultra-low device varia-
bility, which is one of the key
success criteria for 22nm node
manufacturability.
Contact : Markus Mueller, NXP
Figure 1: Tilted top-view SEM image of fin arrays after gate pat-
Semiconductors e-mail : terning (left) and TEM cross section through a 5nm “wide” fin after
markus.mueller@nxp.com full processing featuring a TiN/HfSiO Metal Gate / High-K stack.
Objective 3> To boost the synergy Technology/Design to cope
with power and interconnect delay limitations
Thin body to reduce statistical variability
Statistical variability and related need to introduce novel device architectures present major
challenges to scaling and integration. Strong links must be established between circuit des-
ign, system design and device technology to allow circuits and systems to accommodate the
uncertain transistor behaviour. In the framework of Pullnano using advanced 3D simulation
technology developed at Glasgow, the statistical variability of conventional bulk, FD SOI and
multi-gate device architectures as candidates for the 32 and 22nm technology generations
was accurately evaluated. FD SOI and multi gate transistors, which tolerate low channel do-
ping, offer significantly lower statistical variability. Statistical compact models extracted from
the physical simulations provide early means for studying the impact 32 and 22nm variability
on IP block and SoC an for development of design countermeasures.
Potential and electron concentration distribution in a square 22nm double gate transistor in the
presence of random discrete dopants. The device offers 20 mV standard deviation of the
threshold voltage which
compares favourably with
the more than 50 mV
standard deviation typical
for 45 nm bulk MOSFETs.
Contact : Asen Asenov,
The University of Glasgow
A.Asenov@elec.gla.ac.uk
 Air-Gap using Self-Aligned-barriers is
a promising architecture for 22nm
node interconnects
Using in-house simulation tools, LAHC (Laboratory of Microwave
and Characterization) has shown how Self-Aligned-Barriers (SAB)
improve 32 nm interconnect performance, reducing both delay
and crosstalk by 10% and 7% respectively. These are improve-
ments the designers are looking for.
Integrating Air-Gap using SAB is the most promising architecture
for the 22 nm node. This will also be quite a challenge for the des-
igner with a metal pitch dependant dielectric constant. Experi-
mental characterization shows moisture uptake in low k dielectric
BD2X after integration increases its k-value by 10% generating
dielectric losses. Classical Cu interconnects are limited by propa-
gation delay of high speed (RF) signals. The IMEP laboratory in-
vestigated wireless propagation which uses electromagnetic
waves. The synchronism of pulse fronts is assured by the trans-
ceivers and only jitter is to be controlled. Power consumption
and performance of transceivers required for wireless intercon-
nects is still to be validated.
Contact : Professor Anthony O'Neill, Newcastle University
email : anthony.oneill@newcastle.ac.uk
Objective 4> To be a forum of European
equipment suppliers
EU SMEs line up to achieve the milestones
for advanced metrology equipment
In Pullnano’s Equipment Forum, equipment related small and medium
sized enterprises (SME) are connected to Europe’s flagship project on
32/22nm technology research. They developed several techniques for
advanced characterization at the 32/22nm node:
! Improved secondary ion mass spectroscopy (SIMS) with low impact
energy of <150 eV to measure accurate dopant profiles of ultra-shallow
junctions (USJ). Partners: Cameca, IMEC.
! Novel scatterometry method to characterize the porosity and plasma-
induced sidewall damage of low-k material on patterned wafers. Part-
ners: Nova, IMEC.
! Innovative wafer surface analysis based on Shack-Hartman and Ma-
kyoh principles to measure wafer flatness on patterned wafers, e.g. after
chemical-mechanical polishing (CMP). Partners: Imagine Optic, Fraun-
hofer IISB.
! Integrated metrology solution based on residual gas analysis (RGA)
to control in-line the sealing process of porous low-k layers to ensure a
reliable backend of line (BEOL) integration in a high-volume environ-
ment. Partners: ST, Fraunhofer IISB.
! Unique 4-Point Probe system based on a micro-fabricated 4-point
probe head to resolve micro-scale variation in sheet resistance and to
perform reliable sheet resistance measurements of conducting films,
e.g. ultra-shallow junctions (USJ). Partners: Capres, IMEC, Fraunhofer
IISB.The Equipment Forum, coordinated
by Fraunhofer IISB, proved to be a flexi-
ble and powerful environment for ex-
change of requirements, specifications
and know-how and for successful de-
monstration of advanced metrology
equipment.
Contact : Martin Schellenberger e-mail :
martin.schellenberger@iisb.fraunhofer.de
Focus
On the system level power
estimation
Another key result related to Pullnano's objective 3 has been
achieved by a ten years old independant R&D organisation es-
tablished in Greece. Within Pullnano, ISD ( Integrated Systems
Development ) has developped a novel, entry-level SoC (Sys-
tem-on Chip) power estimation methodology which enables
preliminary estimation of dynamic power of bit and cycle-accu-
rate transaction-level SystemC macro-models. This system-level
power methodology targets power analysis and optimization
with sufficient accuracy and improved productivity with respect
to the traditional RTL design flow.
Dynamic power estimation is based on measuring system’s swit-
ching activity. It is computed by multiplying the number of bit tran-
sitions for all input and output signals with an appropriate bit
energy coefficient. Bit energy (or speed) coefficients adjust inter-
nal system performance (respectively, power) metrics by consi-
dering a precise technology node (e.g. 32 or 22nm) and variations
(e.g. high performance or low power). Such data can be extracted
from semiconductor technology roadmap data available from in-
ternational organizations (e.g. ITRS), simulation platforms (e.g.
MASTAR) or test structures. A representation of this methodology
is shown in Fig. 1.
In the course of Pullnano, ISD has successfully applied this novel
system-level power estimation methodology to design space ex-
ploration and dynamic power management of two complex,
state-of-the-art bit and cycle-accurate SystemC virtual platforms:
! A network bridge providing sequential access to internal me-
mory tables for inserting, searching or retrieving connection
contexts.
! A multicast router used as a building block in a NoC (Network-
on-Chip) configuration of a generic, shared memory-based mul-
ticore SoC supporting SIMD(Single Instruction,Multiple Data)-like
remote memory transactions to multidimensional arrays.
In the near future, ISD is interested to exploit automated and ef-
ficient high-level power estimation and design space exploration
of virtual platforms specified in SystemC based on algorithmic,
architectural, and technology features, both prior and after sys-
tem partitioning. This array of tools could enable efficient product
differentiation by providing performance and power dissipation
tradeoffs, as well as early optimization opportunities for key sys-
tem components.
Contact : Constantin Papadas, ISD Email : papadas@isd.gr
3
 INTERVIEW

“The human story behind

the technology gains momentum”
The FP6 Pullnano project coordinated by STMicroelectronics with a total budget of
45,15 M€ is nearing its completion. The key milestones – among which the 32nm SRAM
cell demonstrators – have been released in line and with the project timing as well as
the ITRS (International Technology Roadmap for Semiconductors). Pullnano results
pave the way for the european semiconductor manufacturers to produce complex chips
in a 32nm process by 2011 / 2012 ... and already open the door to the future 22nm Dr Gilles Thomas (STMicroelectronics)
node, says Gilles Thomas from STMicroelectronics and Pullnano coordinator. Pullnano coordinator

The Pullnano project started on June 1st
2006 for a duration of 30 months. Did you
achieve your original objectives ?
We have established and demonstrated the
technical feasibility of a CMOS 32nm techno-
logy. This was done with the help of European
fundings, and with much more partners than
the former project NANOCMOS (for the 45nm
node) but also with a broader scope of re-
search themes covering all the ingredients ne-
cessary for the technology to become reality,
semiconductor metrology equipments, new
material evaluation, device simulation and mo-
delisation, physical and electrical characteri-
zation and process modules developments for
32nm, even extending to 22nm. All the re-
search themes had a common purpose, i.e. in-
tegrate the process modules to finalize a
technology with a good chance to become
economically viable. The Pullnano project ends
but it doesn't mean that everything stops there ;
from now on, there is still a long road to a qua-
lified technology platform then to “productiza-
tion” and finally to the ramp up of a volume
production. Technology is only the enabler ma-
king later the IC product become reality.
Do the results position Europe competiti-
vely for the future ?
The Pullnano project puts Europe and the eu-
ropean manufacturers in a strong competitive
position as long as applications and products
come quickly to fruition The chosen solutions
like FDSOI to reduce junction leakages and
High K/metal gate to reduce gate leakage are
key concepts to design low power consump-
tion ICs targeting battery-powered portable ap-
plications which was our main focus in the
project. The SRAM cell results from Pullnano
are comparable to Intel's coming announce-
ment at IEDM 2008 on a cell area basis. The
Pullnano results demonstrate a solution to the
ITRS roadmap at 32nm and, already for more
than a year, there has been a vision for multi-
don't know today if multigate is going to be the
choice of the future for everybody in the indus-
try but it looks promising. If one doesn't need
the performance, however, it's perfectly accep-
table to stay planar, thus achieving a different
trade-off between cost and performance.
What do you foresee for the future process
technology research in Europe ?
The FP6 work programme was positioned for
early research in semiconductor technology and
the following development phase was pursued
in the EUREKA/MEDEA+ framework. Due to the
escalating costs of the leading edge technology
developments, the industry has adopted a cost
sharing attitude that requires pooling together
the ressources and creating larger and larger al-
liances; these alliances become global, reaching
a transcontinental size. At the European level, a
new Public-Private instrument exists: a JTI (Joint
Technology Initiative) specifically targeting the
micro-nanoelectronic industry which is federa-
ted under the ENIAC (name of the European
Technology Platform dedicated to Nanoelectro-
nics). It is within this new framework as well as
the existing EUREKA /MEDEA+ (renamed CA-
TRENE) that a future industry led consortium will
continue semiconductor technology research
with a focus shifting towards “More than Moore”
applications. The FP7 repositions itself for the
longer term “Beyond CMOS” research which is
largely taking place in an academic environment.
However, this does not mean that FP7 can't ac-
commodate smaller scope projects (STREP) still
dedicated to advancing Moore's Law (“More
MOORE”). Many themes related to modelisa-
tion, advanced characterisation techniques, new
materials, or process modules like lithography
can federate the huge existing competences,
knowledge and know-how generated over the
years in Europe.
What is the benefit of the Pullnano project
for the industrial community in Europe ?
the full capability of the technology, and of the
design community to make cost effective des-
igns, only then the manufacturing machine will
start kicking in. To have an economically viable
production in a state of the art process, given
the complexity and the cost of the process
(with a million $ mask set), we need very stan-
dardized high-volume chips, the so-called “kil-
ler applications”.
Beyond the industrial benefit, such a project is
above all the story of a cross-border human
collaboration working in synergy towards a
common goal. The project was a memorable
human experience, a sort of multicultural, multi-
interest community of scientists and engineers
with incredible talents acting like a network of
excellence. An important thrust behind the suc-
cess of the project was the considerable ex-
pertise coming from academic and research
institutes scattered all over Europe from Ireland
to Poland and from Sweeden to Greece. This
human dimension of the project will survive,
such a network of relationship has to and will
continue to thrive in the future !
Focus
Pullnano key numbers
> Means & Money
45.15 M! Total cost
25.00 M! EU funding
38 Partners
13 Countries
+300 Researchers
3335 Man-years
> Proficiency & Visibility
480 Publications
170 Deliverables
31 Lectures/tutorials
3 Patents
A powerful 3335 man-years project
9%
35 % Academic
Industrial

gate (at least dual gates, or trigate) devices at We have developed the enabling technologies R&D Centers
22nm. At the individual transistor level, these for the future. Now it's the turn of the electronic 23 % SME
22nm devices are electrically satisfactory. We systems industry to invent applications using 33 %

4
 And now, a step toward tomorrow ? PROSPECTIVE
Beyond the benefits directly derived from the project results, the consortium partners are
having a look at various potential opportunities and at the challenging problems for future
research to build upon the Pullnano foundations. Olof Engström ( Chalmers), Gerard
Ghibaudo (Imep-Cnrs), Thomas Schulz (Infineon) explain how to focus on the promising
modelization, materials and characterization thematics.

The 16nm technological options

already under scrutinity

The subproject 6 entitled “Device Charac- tion and performance limitations.

terization and Simulation” aimed at provi- In a fourth work package, the objective
ding experimental data and was to develop advanced physical models
modelling/simulation results for suppor- addressing the needs foreseen for the
ting the development of nano CMOS de- 22nm technology node. In particular, all
vices based on conventional and novel the issues related to strained silicon, the
architectures, which have been developed adoption of different crystal orientations
during the Pullnano project. The short- for the MOSFET channel, the use of High K
term oriented activities have been gate dielectrics, the fluctuations of do- Gérard Ghibaudo
conducted in three work packages, while pants, the dielectric and silicon layer thick- Director of IMEP-LHAC (CNRS)
a fourth package already tackled the ness and the effects of line-edge
22nm node. roughness, as well as their impact on the could be continued by exploring the best-
electrical parameters of the device have suited architectures and materials for the
In the first one, conventional TCAD simu- been investigated. The developed models, 16nm and beyond CMOS technology
lations have been carried out for the de- implemented in device simulators, will nodes. More specifically, this would imply
velopment and integration of 32nm CMOS allow evaluating and comparing different for example the study of new channel se-
devices. These activities have in particu- device architectures and technological op- miconductors such as Ge, GaAs with very
lar been focused on FinFET 3D simula- tions. high mobility and more aggressive archi-
tions and on the impact of strain on In the future, these research activities on tectures like silicon nanowires offering 3D
conventional and non-conventional de- device characterization and simulation integration.
vices based on classical drift-diffusion,
Monte Carlo and Quantum Mechanical
approaches. A simulation methodology to
connect stress, band structure and trans-
port calculations has been developed for
both biaxial and uniaxial stresses. In the
second work package, the objective was
to propose new compact models for cir-
cuit simulation and device technological
specification calculations, as well as to in-
vestigate (by simulation) the impact of the
device architecture and interconnects on
the power consumption of a complex cir-
cuit. Physically based compact device
models including quantum effects, nearly
and ballistic transport in conventional and
non-conventional architectures have the-
refore been created and implemented into
ST’s MASTAR tool for the assessment of
32nm and 22nm CMOS technological
specifications. In the third work package,
extensive electrical characterization (es-
pecially interface and mobility) of the fa-
Illustration of the activities in the “device characterization and simulation” subproject in PULL-
bricated 32nm and below CMOS test NANO : The different activities extend from mobility characterization to SRAM modelisation, in-
structures have been carried out, aiming cluding work on leakages in High K dielectrics, reliability issues of MOS built with High K gate and
at better understanding the device opera- stressed channels.

5
 PROSPECTIVE Olof Engström,
Chalmers University (Sweden)

The development of gate dielectrics looks
at rare earth oxides for the future
Even before the debut of the Pullnano project,
it became evident that, in order to keep the
ability of MOS transistors to act as efficient
switches on the ride along the More-Moore
road, new dielectric materials for the gate func-
tion will be necessary. The hafnium based die-
lectrics, which presently replace traditional
silicon dioxide insulators, will probably find a
substitute before the 22nm node is ready for
production. Two intrinsic material properties
are important for the choice of a new dielec-
tric. These are, on one side, the dielectric
constant (k-value) and, on the other side, the
Rare earth oxides offer interesting properties to
fulfil such requirements. Even if their k-values
are moderate, their !E-values are high enough
barrier height (offset to put them into the spotlight. The choice of
value, !E) seen by GdSiOx in Pullnano was based on this consi-
an electron ready to deration, with the addition of silicon to Gd2O3
leak between the to stabilize this oxide in its amorphous phase.
gate metal and the While GdSiOx was demonstrated feasible by
transistor channel. the “High-k-Gang” (www.high-k-gang.eu) for
At given limits of leakage current and insulator the 22nm node on SOI, a still higher k x !E –
thickness, the k and !E values are bound product needs to be developed for the nanoe-
roughly by a hyperbolic relation such that a lectronics landscape beyond this landmark. Al-
product, k x !E ≈ 70 eV is necessary for the 22 beit a multitude of challenging problems remain
nm bulk LSTP node, while the corresponding in this terrain, a number of possible candidates,
figure for silicon on insulator technology is in the like lanthanum based materials or even ferroe-
range of 30 - 40 eV. lectrics, are still aces up our sleeves.

Advanced characterization of nanodevices :

novel approaches are needed Thomas Shulz (Infineon)

With their dedication to advanced characterization, the subproject 5 team depth profiling techniques using SIMS, AES and XPS have to be impro-
partners are the eyes of the Pullnano community, aiming to further shar- ved, e.g. by enhancing sensitivity or by model-based interpretation of the
pen the sight of our colleagues in the project and make the nanodevices depth profiles. The use of much brighter X-ray sources (Synchrotron ra-
and their properties more visible. Various tools and techniques are used diation) is likewise a must for a better analysis within the nanoscale de-
to characterise and simulate the whole list of physical parameters des- vice structures themselves or of very thin films. Also, as outlined by the
cribing in detail the key features of the investigated devices and materials. updated ITRS roadmap, models for mechanical stress engineering have
The scaling down of feature sizes in modern CMOS processes imposes been identified as an
very rigorous requirements for characterization methods with respect to important and diffi-
Characterization of
accuracy and reproducibility. To cope with the challenges of the 32nm and cult challenge for ul- high-k materials :
22nm nodes, the currently established measurement techniques have to timate nanoscale with the first ever
synchroton-radiation
be further improved or substituted by novel innovative approaches. One simulation capabi- XPS (X-Ray Photo-
electron Spectro-
example from the Pullnano project is the holodark technique used for the lity. Today's com- scopy), the
elemental composi-
strain measurement in the devices (see Focus). This technique is expec- mercial process tion of high-k layer
ted to potentially replace or complement the older Raman techniques simulators are far interfaces have been
investigated without
which have for instance a much more limited resolution. from providing ac- sample destruction.
For future needs, the characterization of the material composition and curate and physical
density at the interfaces high-k dielectric/metal and high-k dielectric/Si, strain fields !

FOCUS Distribution of strain

Breakthrough in strain
metrology with new
electron holographic
technique
Strained-silicon channels is now a mainstream technique in state-
of-the-art CMOS technologies and will continue to be for the
32nm to 22nm technology generations to come. The reason for
the success is that strain-induced deformation of the crystal lat-
tice in active regions of nanoelectronic devices improves CMOS
logic performances. Electron (or hole) mobility is significantly in-
creased, making it possible to boost circuit speed. Without accu-
rate methods of measuring strain at the nanoscale, however,
manufacturers cannot have complete mastery of device design or
of device reproducibility. This problem has now been solved,
thanks to a new strain measurement method invented by the
CNRS team in Toulouse working within the Pullnano project.
Director of Publication : Gilles Thomas (STMicroelectronics)
Managing Editor : Chantal Cochini email : nano32@lops.fr
Contributing Editor : Elisabeth Feder
For more information on Pullnano: WWW.pullnano.eu
across three p-MOSFET
devices measured by
dark-field electron holo-
graphy. The Si1-xGex
source and drain regions
apply compressive strain
(in blue) to the silicon
channel.
The technique, which is based on electron holography, is innova-
tive in a number of ways. Strain can be mapped across devices
with high precision whilst maintaining nanometre spatial resolution
(4nm) (see Figure). Precision in strain values exceeds 0.1%. More
traditional techniques have been limited to carrying out measure-
ments at isolated data points or for small regions at a time. Com-
plex strain distributions can therefore now be studied to improve
modelling of devices and optimise strain engineering. The work
was published in the June 19th, 2008 issue of the journal Nature
and has led to two patents. M.J. Hÿtch, F. Houdellier, F. Hüe, and E.
Snoeck, Nature 453 (2008) 1086-1089.
Nanoscale holographic interferometry for
strain measurements in electronic
PULLnano is a project supportyed by the Euro- devices. doi :10.1038/nature07049.
pean Commission from the IST Programme Contact Martin Hycht
within the European Union 's Sixth RTD email : hytch@cemes.fr
Framework programme.