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24 | wirelessdesignmag.com  testing Lte DEsign Talk Addressing the Design and Verification Challenges of

24 | wirelessdesignmag.com

testing Lte

DEsign Talk

Addressing the Design and Verification Challenges of Long Term Evolution

Design simulation can be useful in addressing LTE design and verification challenges but requires consideration in selecting the appropriate model abstraction for the given phase of the design cycle.

|By greg Jue, Agilent technologies

E merging standards such as 3GPP Long Term Evolution

(LTE) present a number of design and verification chal-

lenges for system engineers. Some examples include deter-

mining design requirements and specifications for new hardware designs, evaluating hardware re-use, and testing RF/mixed-signal designs and hardware independently of baseband hardware. Electronic Design Automation (EDA) simulation tools can help address these challenges by enabling system engineers to perform system-level trade-offs early in the design cycle to determine design requirements and specifications. Simulating RF and baseband designs together in one simulation environ- ment enables evaluation of the system’s RF/mixed-signal performance. Combining EDA simulation with test equipment provides flexibility in addressing testing needs for an emerging standard such as LTE. This article investigates 3GPP LTE sys- tem design and verification challenges, and shows new design simulation capabilities to help address these challenges. Several

case studies highlight how design simulation can be applied to address these LTE design and verification challenges.

to address these LTE design and verification challenges. Figure 1. LTE uplink transmitter design swept simulation

Figure 1. LTE uplink transmitter design swept simulation results.

Simulation Case Study – Top Level Design A system engineer typically trades off various RF/mixed- signal requirements to make decisions on an overall perfor- mance budget allocation for a design. These trade-offs can involve baseband performance, such as the required bit-width of a fixed-point Root Raised Cosine (RRC) filter to meet a spectral mask or Error Vector Magnitude (EVM) metric. They can also involve RF performance trade-offs, such as the required transmitter LO phase noise or Power Amplifier (PA) 1 dB compression point to meet an EVM metric. The system engineer may need to trade off the required baseband performance versus RF performance to meet a system-level EVM specification. To illustrate this, a simplified transmitter design is con- structed in EDA simulation using an LTE Uplink source, as shown in Figure 1. Parameterized behavioral models allow a top-level design to be quickly constructed and evaluated by specifying parameters such as gain, 1 dB compression point, filter order and bandwidth. Upconverter LO phase noise is specified in dBc/Hz at various frequency offsets on the LO source. The ideal Root Raised Cosine (RRC) filter in the LTE uplink signal source is replaced with a fixed-point RRC filter (inside of the hierarchical source), and the effective RRC bit-width is specified on the top level design. The constellation types on the LTE signal source are defined as QPSK, 16QAM, or 64QAM using the LTE mapper element on the far left of the schematic. The output of the transmitter is connected to an EVM measurement sink.The simulation results at the bottom of Figure 1 show how EDA simulation can help the system engineer to trade-off RF versus baseband design requirements to meet a design performance specifica- tion such as EVM. The lower left plot shows the simulated EVM versus the RRC filter’s effective swept bit-width. The middle plot shows EVM versus swept phase noise in dBc/Hz at a fixed frequency offset. The right plot shows EVM versus swept 1 dB compression point on a PA amplifier.

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DEsign Talk DEsign Talk 26 | wirelessdesignmag.com  t e s t i n g Lt

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The system designer can trade off these base- band and RF requirements in one simulation envi- ronment to determine the top-down design require- ments for the RF and baseband sections to meet

a given system performance requirement such as EVM. Although time and cost are not explicitly shown, these may also be considerations in trading off the RF versus baseband performance to meet a

 Q: What are the challenges and solutions with Lte testing?  Li Cui, Product
Q: What are the challenges and solutions
with Lte testing?
 Li Cui, Product
Marketing Manager,
tektronix, inc.
F irst and foremost,
designers need
to verify signal
compliance to the latest LTE
standard.
They need tools to
identify and, ultimately, isolate where the problem
exists, whether this be an algorithm problem or
signal interference. Furthermore, simply passing
conformance testing does not ensure a device will
work properly. The software-controlled changes
commonly cause glitches, intermittent interfer-
ence, pulse aberrations, digital to RF couplings
and software-dependent phase errors, to name a
few. When these transients occur, spectral leak-
age will occur, resulting in frequency "splatter"
that conventional spectrum analyzers or VSAs
will miss.
Designers need instruments that are able
to discover and capture those transients for
analysis. The Digital Phosphor Technology
(DPX) available from Real-Time Spectrum Ana-
lyzers offers an intuitive live color view of signal
transients changing over time in the frequency
domain, and can instantly display a fault when
it occurs. The Frequency Mask Trigger technol-
ogy (FMT) can then be used to set to trigger on
the event in the frequency domain, capture a
continuous time record of changing RF events,
and perform time-correlated analysis in all
domains. Effective Discover, Trigger, Capture
capability along with the Analysis capability that
supports the March 2008 LTE release are the
key considerations for LTE designers.

given performance requirement.

Simulation Case Study – Verify System Level Performance with Detailed Baseband and RF Designs Design simulation can be useful in addressing LTE design and verification challenges, but requires consideration in selecting the appropriate model abstraction for the given phase of the design cycle. Specifically, models at several levels of abstraction are typically needed to support a design flow as it progresses from a conceptual phase to a detailed design phase. Top-level designs need to be quickly and easily constructed in the early design phase to evaluate system-level metrics and to perform design trade-offs. However, improved modeling fidelity with a more detailed level of modeling abstraction is generally needed later in the design cycle to verify that the system-level performance is still being met as the development phase progresses to hardware implementation. For example, key system-level met- rics, such as EVM and Bit Error Rate (BER), are evaluated on designs constructed with parameterized behavioral models which provide the high level of modeling abstraction needed to quickly construct and evaluate designs. Improved modeling fidelity is then achieved by replacing the behavioral models with HDL code or transistor-level circuit designs to verify EVM and BER as the design cycle progresses to a detailed-level design phase. Co-simulating detailed

Two Primary Challenges Drive lTE Test Requirements

detailed Two Primary Challenges Drive lTE Test Requirements  Ron Rausch, sr. Marketing Manager, Keithley instruments

Ron Rausch, sr. Marketing Manager, Keithley instruments

a s RF designers roll-out products that sup-

port the new LTE cellular wireless standard,

understanding the new test requirements for

LTE assumes ever greater importance. Two primary challenges affect LTE test:

• Moving from single-carrier to multi-carrier OFDM

(Orthogonal Frequency Division Multiplexing) modulated signals;

• Moving from SISO (single-input single-output) to

MIMO (multiple-input multiple-output) signal stream transmissions. Multi-carrier OFDM signals are complex and typically wide bandwidth, requiring measurements from multiple dimensions. For instance, measur- ing EVM (Error Vector Magnitude) and power versus subcarrier across the frequency channel, or measuring EVM and power versus time slot across the transmission frame, can isolate problems. The higher PAR (Peak-to- Average Ratio) of OFDM signals warrants checking the transmitter gain compression using OFDM-modulated test signals. Moving from SISO to

MIMO signal stream transmissions requires new measurements and test equipment capable of measuring multiple signal streams. MIMO measure- ments are made of the composite data channel and of the individual data streams. New measurements include Channel Response, the power of the individual spatial streams of an N-by-M MIMO transmission, and Matrix Condition, the ability of the receiver to separate the multiple signal stream transmissions. Beyond ensuring high measurement integrity, test instru- mentation for LTE will ideally be fast and flexible. Since SISO measure- ments will continue to be made, MIMO test equipment able to make SISO measurements and also scalable to four precisely-synchronized MIMO channels for signal generation and signal analysis will save time and money. Since LTE will be incorporated into equipment employing other wireless standards, such as GSM, W-CDMA and WLAN, test instruments that are capable of testing multiple standards with signal bandwidths up to 40 MHz will also provide time and cost advantages. OFDM and MIMO are powerful technologies enabled by high-performance, low-cost DSP chips. The next-generation test instrumentation for LTE will have high-speed DSP technology for signal processing, capability to test multiple wireless standards, and be scalable to four MIMO channels.

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28 | wirelessdesignmag.com  t e s t i n g Lt e DEsign Talk transistor-level

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transistor-level circuit designs together with HDL code allows the system engineer to verify the sys- tem-level performance with detailed baseband and RF designs in one simulation environment to help minimize system integration risk and unexpected surprises when system integration testing begins. Figure 2 shows an example of HDL being co-simu- lated together with a transistor-level circuit design in EDA design simulation to verify the system-level RF/mixed-signal performance. A fixed-point RRC is replaced with HDL code in an LTE downlink source, providing a more detailed level of baseband modeling fidelity. Similarly, the amplifier behavioral model is replaced with a transistor-level circuit design, also providing a detailed level of RF modeling. The LTE downlink simulation results for the transmitter with both HDL co-simulation and cir- cuit co-simulation are shown in Figure 3. The LTE downlink simulation results reflect the baseband and RF simulation impairments from the RRC HDL co-simulation and RF amplifier circuit co-simulation. The constellations are shown, along with simulated EVM. The LTE downlink source allows the user to specify either QPSK, 16QAM, or 64 QAM for the User Equipment (UE).

Simulation Case Study – Receiver Design and Verification Simulated EVM is shown for the transmitter design, which is typically a key metric for transmit- ter design performance. A key metric for receiver design performance, however, is typically Bit Error Rate (BER) or Block Error Rate (BLER). A receiver design is constructed with parameter- ized behavioral models and uncoded BER curves are simulated for swept Eb/No into the receiver. Phase noise can be a critical issue for OFDM-based sys- tems, so the downconverter LO phase noise was also swept for several dBc/Hz settings at a fixed frequency offset to evaluate the impact of phase noise on BER. Figure 4 shows the simulation results for QPSK, 16QAM, and 64QAM, moving from left-to-right, respectively. Multiple curves are shown for each case (QPSK, 16QAM, 64QAM) as a result of the LO phase noise being swept from -80 dBc/Hz to -60 dBc/Hz. Observe that the 64QAM BER performance degrades more significantly with the swept phase noise values than the QPSK BER performance as a result of the constella- tion states being closer to one another with 64QAM.

Hardware Testing of R&D LTE Hardware An emerging standard such as LTE can pose unique hardware testing challenges, and may require a flexible

hardware testing challenges, and may require a flexible Figure 2. Verifying the system performance of baseband

Figure 2. Verifying the system performance of baseband HDL and RF transistor-level circuit.

performance of baseband HDL and RF transistor-level circuit. Figure 3. Baseband HDL and RF circuit co-simulation.

Figure 3. Baseband HDL and RF circuit co-simulation.

Figure 3. Baseband HDL and RF circuit co-simulation. Figure 4. LTE receiver downlink uncoded BER swept

Figure 4. LTE receiver downlink uncoded BER swept simulation results.

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testing approach to address these
challenges. An example is evaluat-
ing existing RF/mixed-signal hard-
ware performance independently of
the baseband section to evaluate
hardware re-use for LTE. Another
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Figure 5. LTE test setup for mixed-signal BER test-
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Nominal
Figure 6. Mixed signal DUT testing results.
Model
RF
Frequency Range (MHz)
LO
IF
(dBm) Typ.
(dBm)Typ.
ed BER). The test setup
in Figure 5 illustrates
5-1000
10-1500
1-500
10
6.0
20/50
how uncoded BER measurements can be made on a mixed-signal receiver. In
MCH3008
1-3000
1-3100
1-2000
7.0
20/50
this case, the DUT is not a full receiver. It is an off-the-shelf Analog-to-Digital
1-3400
1-3400
1-2000
8.0
20/50
Converter (ADC) board. However, the same approach could be used to test a
mixed-signal receiver with RF inputs and digital outputs. The test setup con-
10-2000
10-2000
5-1000
13
7.0
22/38
sists of a signal arbitrary waveform generator, a logic analyzer, a signal source
MTS6018
2000-6000 2000-6000 5-1000
2000-6000 2000-6000 5-3000
7.5
15/30
8.0
15/30
to clock the ADC board DUT and the ADC board DUT.
The EDA design simulation environment is installed inside of the logic
MS10623
7000-9000 7000-9000 DC-500
6000-10000 6000-10000 DC-2000
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8.5
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analyzer as a custom application example. (Note, however, that the EDA solu-
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tion does not ship with the logic analyzer.)
The IF input power into the mixed-signal DUT was swept from -60 dBm to
2000-20000 2000-20000 5-2000
MMP20281 2000-20000 2000-20000 2000-4000
2000-20000 2000-20000 4000-6000
13
7.0
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-50 dBm, and the resulting uncoded BER results with an LTE downlink signal are
7.0
shown in Figure 6. A 1% uncoded BER occurs at approximately -57 dBm into the
8.5
DUT. Please note that this is a component-level measurement, not a sensitivity
measurement for an entire receiver.
Typical and guaranteed specifications vary versus frequency; see detailed data sheets for specification variations.
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Summary
This article discussed some design and verification challenges posed by
3GPP LTE, and showed how EDA design simulation helps address these chal-
lenges. The system design simulation case study highlighted various RF and
baseband design trade-offs using metrics such as EVM and uncoded BER to
evaluate the system performance. The EDA LTE design simulation functionality
was then used together with instrumentation to measure the uncoded LTE BER
performance of a mixed-signal DUT.
WDD
Request 2008/09
Product Guide
by phone or online.
927 Thompson Place • Sunnyvale, CA 94085
408-522-3838 • Fax 408-522-3839
www.teledyne-cougar.com
email: Amp@teledyne.com
Greg Jue is an application specialist with Agilent EEsof EDA. He is the product manager for the
Advanced Design System 3GPP LTE Wireless Library, and has pioneered combining design and test
solutions at Agilent as an applications technical lead.

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