QUAID-E-AWAM UNIVERSITY OF ENGINEERING SCIENCE AND TECHNOLOGY NAWABSHAH DEPARTMENT OF ELECTRONIC ENGINEERING SUBJECT: FPGA BASED SYSTEM DESIGN

Practical No. 01 Name: Roll No: ____________ Score: _________ Signature: _________Date: ____________________

Object: Introduction to VHDL

EQUIPMENT PC with operating system ModelSim 6.5 (or 6.x SE)

Modelsim
ModelSim is a powerful HDL simulation tool that allows you to stimulate the inputs of your modules and view both outputs and internal signals. It allows you to do both behavioral and timing simulation.

INTRODUCTION TO HDL:
We specify the logic function we want to build in several different ways .There are two methods most commonly used, Hardware description language Schematics

Hardware description language (HDL)

Hardware description language is a textual description also known as entry based language, the software allows the user to enter a logic design in the form of text using hardware description language. HDLS are most important tools used to describe hardware.

Schematics
It is a graphical description; the software allows the user to enter a logic design using logic components (e.g. logic gates flip flop) and to interconnect them on the computer screen to form a schematics diagram. Schematics are generally structural description of the components and wires in a design.

There are two most commonly used HDLS are VHDL Verilog HDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming language used to model a digital system by dataflow, behavioral and structural style of modeling. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC program. In 1983 IBM, Texas instruments and Intermetrics started to develop this language. In 1985 VHDL 7.2 version was released. In 1987 IEEE standardized the language.

Design Entity
A design entity is design element in VHDL And consists of: An entity declaration and An architecture body. Entity Declaration Each port in an entity should include: Name of the signal (identifier) Direction (mode) Data type It defines the names, input output signals and modes of a hardware module. Syntax: entity entity name is Port declaration; end entity name; An entity declaration should starts with entity and ends with end keywords. Architecture: It describes the internal description of design or it tells what is there inside design. Each entity has atleast one architecture and an entity can have many architecture. Architecture can be described using structural, dataflow, behavioral or mixed style. Architecture can be used to describe a design at different levels of abstraction like gate level, register transfer level (RTL) or behavior level.

Syntax: Architecture architecture name of entity name architecture_declarative_part; begin Statements; end architecture name; The internal working of an entity can be defined using different modeling styles inside architcture body. They are 1. Dataflow modeling. 2. Behavioral modeling. 3. Structural modeling.

Q: 1 Define HDL? __________________________________________________________________________ _ __________________________________________________________________________ _

Q: 2 what are the types of HDL? _________________________________________________________________________________ _________________________________________________________________ Q: 3 Define VHDL? _________________________________________________________________________________ _________________________________________________________________

Q: 4 write the syntax of entity and architecture in VHDL?

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