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ECEN 454
ECEN 454
4.2
MOS Capacitor
Gate and body form a MOS capacitor
Operating modes
000000000000000000000000000
000000000000000000000000000 polysilicon gate
Accumulation
Depletion
Inversion
00000000000000000000000000000000
00000000000000000000000000000000
Vg < 0
+
-
(a)
p-type body
00000000000000000000000000000000
000000000000000000000000000
000000000000000000000000000
000000000000000000000000000
0 < Vg < Vt
+
-
(b)
depletion region
00000000000000000000000000000000
000000000000000000000000000
000000000000000000000000000
000000000000000000000000000
Vg > Vt
+
-
inversion region
depletion region
(c)
ECEN 454
4.3
Vgs = Vg Vs
Vgd = Vg Vd
Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
Cutoff
Linear
Saturation
ECEN 454
+
Vgs
Vs
+
Vgd
Vds +
Vd
4.4
nMOS Cutoff
No channel
Ids = 0
Vgs = 0
+
s
g
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000000
n+
+
-
Vgd
d
n+
p-type body
b
ECEN 454
4.5
nMOS Linear
Channel forms
Current flows from d to s
e- from s to d
Ids increases with Vds
Similar to a linear resistor
Vgs > Vt
+
s
000000000000000
0000000000000
0000000000000
0000000000000
0000000000000
n+
+
-
Vgd = Vgs
d
Vds = 0
n+
p-type body
b
Vgs > Vt
+
s
000000000000000
0000000000000
0000000000000
0000000000000
0000000000000
n+
+
d
n+
p-type body
b
ECEN 454
4.6
nMOS Saturation
Channel pinches off
Ids independent of Vds
(approximately)
Vgs > Vt
+
-
0000000000000000
0000000000000
0000000000000
0000000000000
0000000000000
n+
+
-
Vgd < Vt
d Ids
n+
p-type body
b
Similar to a voltage
controlled current
source
ECEN 454
4.7
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
ECEN 454
4.8
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel =
000000000000
000000000000
000000000000
00000000000000000000000
000000000000
000000000000000000
000000000000000000
000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
polysilicon
0000000000
0000000000000000000
gate
0000000000
0000000000000000000
0000000000
0000000000000000000
W
0000000000
0000000000
0000000000000000000
0000000000
0000000000
tox 0000000000
0000000000
n+
gate
000000000000000
000000000000000
Vg
000000000000000
+
+
000000000000000
n+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+ Vds
p-type body
p-type body
ECEN 454
4.9
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel = CV
C=
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000000000000
000000000000
00000000000000000000000
000000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
polysilicon
0000000000000000000
0000000000
gate
0000000000000000000
0000000000
0000000000000000000
0000000000
W
0000000000000000000
0000000000
0000000000
0000000000
0000000000
0000000000
tox 0000000000
n+
n+
000000000000000000
000000000000000000
gate
000000000000000
000000000000000
Vg
000000000000000
+
+
000000000000000
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+ Vds
p-type body
p-type body
ECEN 454
4.10
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V=
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000000000000
000000000000
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000000000000
000000000000000000
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000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
polysilicon
0000000000
0000000000000000000
gate
0000000000
0000000000000000000
0000000000
0000000000000000000
W
0000000000
0000000000
0000000000000000000
0000000000
0000000000
tox 0000000000
0000000000
n+
gate
000000000000000
000000000000000
Vg
000000000000000
+
+
000000000000000
n+
Cox = ox / tox
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+ Vds
p-type body
p-type body
ECEN 454
4.11
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
000000000000
000000000000
000000000000
00000000000000000000000
000000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
0000000000000000000
0000000000
polysilicon
0000000000000000000
0000000000
gate
0000000000000000000
0000000000
0000000000000000000
0000000000
W
0000000000000000000
0000000000
0000000000
0000000000
0000000000
0000000000
tox 0000000000
n+
n+
Cox = ox / tox
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gate
000000000000000
000000000000000
Vg
000000000000000
+
+
000000000000000
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+ Vds
p-type body
p-type body
ECEN 454
4.12
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field
between source and drain
v=
ECEN 454
4.13
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E=
ECEN 454
4.14
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=
ECEN 454
4.15
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v
ECEN 454
4.16
I ds =
ECEN 454
4.17
I ds =
Qchannel
t
ECEN 454
4.18
Qchannel
t
W
V
= Cox Vgs Vt ds Vds
2
L
V
= Vgs Vt ds Vds
2
I ds =
= Cox
ECEN 454
W
L
4.19
I ds =
ECEN 454
4.20
10
I ds = Vgs Vt
Vdsat
Vdsat
ECEN 454
4.21
I ds = Vgs Vt
ECEN 454
(V
2
gs
Vt )
Vdsat
Vdsat
4.22
11
0
Vgs < Vt
V
I ds = Vgs Vt ds Vds Vds < Vdsat
2
2
V
V
Vds > Vdsat
(
)
gs
t
cutoff
linear
saturation
ECEN 454
4.23
Example
For a 0.6 m process
tox = 100
= 350 cm2/V*s
Vt = 0.7 V
2.5
Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2
Vgs = 5
2
1.5
V gs = 4
1
V gs = 3
0.5
0
14
3.9 8.85 10
W
W
W
= Cox = ( 350)
A /V 2
= 120
8
L
L
100 10
ECEN 454
Vgs = 2
Vgs = 1
Vds
4.24
12
pMOS I-V
All dopings and voltages are inverted for pMOS
Source is the more positive terminal
-0.2
Vgs = -3
Ids (mA)
Vgs = -1
Vgs = -2
-0.4
Vgs = -4
-0.6
-0.8
-5
Vgs = -5
-4
-3
-2
-1
Vds
ECEN 454
4.25
Mobility degradation
Due to vertical E-field
ECEN 454
4.26
13
ECEN 454
4.27
Velocity Saturation
Ideally, carrier drift velocity increases linearly with
lateral field ( Vds / L )
If lateral field is very strong, the velocity saturated
due to scattering
-power law model
As velocity saturated, increasing Vgs has less effect
As velocity saturated, no benefit to raise VDD
ECEN 454
4.28
14
Velocity Saturation
Velocity saturation
n (m/s)
sat = 105
Constant velocity
c = 1.5
(V/m)
ECEN 454
4.29
Velocity Saturation
Velocity saturation
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT
VGS - V T
VDS
4.30
15
Mobility Degradation
Strong vertical field (Vgs) causes scattering, reduces
carrier mobility
Captured in -power law model
By
ECEN 454
4.31
250
0
ECEN 454
Et(V/um)
100
4.32
16
Leakage Current
Subthreshold leakage
Vgs Vt
Ids = Ids0 e
nvT
(1 e
Vds
vT
Junction leakage
Gate tunneling
ECEN 454
4.33
Body Effect
Vsb affects threshold voltage
Vt = Vt 0 + ( | 2 F | +Vsb | 2F |)
ECEN 454
4.34
17
Temperature Dependence
When temperature increases
Carrier mobility decreases, ON current decreases
Threshold voltage decreases, leakage increases
ECEN 454
4.35
Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
ECEN 454
4.36
18
Gate Capacitance
Approximate channel as connected to source
Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m
tox
n+
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000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
polysilicon
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
gate
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
W
00000000000000000000000000000
000000000000000
00000000000000000000000000000
000000000000000
000000000000000
000000000000000
000000000000000
000000000000000
000000000000000
000000000000000
000000000000000
n+
p-type body
ECEN 454
4.37
Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process
ECEN 454
4.38
19
Diffusion Capacitance
We assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
2C
2C
Shared
Contacted
Diffusion
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
3
3
3C 3C 3C
ECEN 454
7C
3C
3C
4.39
Activity
1) If the width of a transistor increases, the current will
increase
decrease
not change
2) If the length of a transistor increases, the current will
increase
decrease
not change
3) If the supply voltage of a chip increases, the maximum
transistor current will
increase
decrease
not change
4) If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
5) If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase
decrease
not change
ECEN 454
4.40
20
Activity
1) If the width of a transistor increases, the current will
increase
decrease
not change
2) If the length of a transistor increases, the current will
increase
decrease
not change
3) If the supply voltage of a chip increases, the maximum
transistor current will
increase
decrease
not change
4) If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
5) If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase
decrease
not change
ECEN 454
4.41
21