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JFET DC Biasing Topics

Fixed Bias Self-bias Voltage-divider bias GOAL: To locate the Q-point and plot it in the characteristic curves (input and output) of the FET. Q-pt (VGS, ID) input graph Q-pt (VDS, ID) output graph

JFET DC Biasing
EE 21 Fundamentals of Electronics

EE 21 Slides (AAMS) 1

Important relationships
Shockleys Equation:

Fixed Bias Circuit

Simplest FET bias circuit. Presence of DC bias in VGG directly manipulates control voltage VGS value.

For the FET: gate current IG 0. ID may be assumed equal to IS.

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DC Analysis of Fixed Bias

INPUT SIDE: Since IG = 0, resistor RG is effectively shorted. By KVL, -VGG VGS = 0, and VGS = -VGG. Note that the value of VGS is fixed, hence the name fixed bias.
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DC Analysis of Fixed Bias

OUTPUT SIDE ID is determined by Shockleys eqn By KVL: VDS = VDD IDRD * VS = 0 (grounded) Therefore, VDS = VD
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Plotting the loadline / output characteristics curve

From the loadline equation VDS = VDD IDRD Intercepts of line: When ID = 0, VDS = VDD When VDS =0, ID = VDD/RD.
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Example: Fixed Bias Circuit

Determine the Q-point of the fixed bias circuit and plot in on the Shockley and characteristic curves. Use both mathematical and graphical approach. Take IDSS = 10mA and VP = - 8 Volts.
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Self-bias circuit
Term self-bias comes from its independence from a VGG source. Also known as common-gate configuration.
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DC Analysis of Self-bias circuit

Again, RG is shorted by the absence of IG. Since ID = IS, KVL on the input ckt yields the ff:

VGS I D RS
Note now that VGS is a function of the drain current ID, which is what we are looking for.
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Mathematical Solution for ID

Substituting VGS = -IDRS to Shockleys eqn

Graphical Solution for ID

Provides an accurate enough solution for the current ID (as long as the graphs are constructed neatly and properly scaled). This doesnt mean the graphical solution is ALWAYS better than the mathematical. There are cases that the mathematical solution (though not necessarily the quadratic) is needed to find the answer.
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Manipulate this to get a quadratic equation in terms of ID. Note that this will yield two possible answers. (How will you know which one to accept?)

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Graphical Solution
Shockley curve is plotted (through 4 points) The line VGS = IDRS is also plotted on the same set of axes. The Q-point is the intersection of the two graphs.
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Completing the solution

After solving for ID (using either method) KVL on output circuit: VDS = VDD ID(RD+RS) Also, Vs = IDRS VG = 0 VD = VDS + VS = VDD - VRd
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Example: Self-bias circuit

For the self-bias circuit, determine: a. VGSQ b. IDQ (2 methods) c. VDS d. VS e. VG f. VD IDSS = 8mA, VP = -6 V.

Voltage Divider Bias Circuit

Similar to the BJT voltage divider Since IG = 0, then R1 and R2 are in series, and

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DC Analysis of voltage divider bias

KVL (lower loop) gives us VG VGS VRs = 0 VGS = VG VRS since IS = ID, VRs = IDRS And VGS = VG IDRS (variable as well!)

Graphical Solution
Mathematical solution for ID is too tedious due to the lines equation Therefore we use graphical solution (similar to self bias)
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Example: Voltage Divider Bias

For the voltage divider circuit, solve for a. IDQ and VGSQ b. VD c. VS d. VDS e. VDG FET Characteristics: IDSS = 8mA VP = - 4 V

Combination Networks
Includes both JFET and BJT First approach the device that will provide a terminal voltage or current level BJT and FET analysis are carried over (creeping solution)
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Example
For the combination network, determine a. VD b. VC c. VCE d. VDS
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Step-by-step solution
Determine VB Find VE Find IE Extend to IC and ID Solve for VD Solve for VC (and VGS by extension) Get VCE Get VDS

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