Digital CMOS Logic Operation in the Sub-Threshold Region

Hendrawan Soeleman and Kaushik Roy
Purdue University
Department of Electrical and Computer Engineering
West Lafayette, IN 47907, USA

fsoeleman, kaushikg@ecn.purdue.edu

ABSTRACT
Numerous eorts in balancing the trade-o between power,
area and performance have been carried out in the medium
performance, medium power region of the design spectrum.
However, not much study has been done at the two extreme
ends of the design spectrum, namely, the ultra-low power
with acceptable performance at one end, and high performance with power within limit at the other. In this paper,
we focus on the ultra-low power end of the spectrum where
performance is of secondary importance. One solution to
achieve the ultra-low power requirement is to operate the
digital logic gates in sub-threshold region. In this paper, we
analyze both CMOS and Pseudo-NMOS logic operating in
sub-threshold region. We compare the results with CMOS
in normal strong inversion region and with other known lowpower logic, namely, energy recovery logic. Results show energy/switching reduction of two orders of magnitude from
an 8x8 carry-save array multiplier when it is operated in the
sub-threshold region.

1.

INTRODUCTION

In the medium performance, medium power consumption

design region, numerous optimization eorts have been carried out, such as: voltage scaling, transistor sizing, reducing
switching activities, clock gating, etc[1; 2; 3]. However, not
much study has been done at the two ends of the design spectrum, namely ultra-low power with acceptable performance
at one end, and high performance design with power within
specied limit at the other end. This paper focuses on design techniques for ultra-low power dissipation where performance is of secondary importance. One way to achieve this
goal is by running the digital circuits in sub-threshold region. The incentive of operating circuits in the sub-threshold
region is to be able to exploit the sub-threshold leakage current as the operating drive current. Note that sub-threshold

This research is supported in part by SRC under contract#

98-HJ-638 and by NSF(CCR-9901152)

current leaks continuously whether the circuit switches or idles. The sub-threshold current is exponentially related to
the gate voltage. This exponential relationship is expected to give an exponential reduction in power consumption,
but also an exponential increase in delay. Our results show
that the reduction in power outweighs the increase in delay,
and thus, giving the overall reduction in energy consumption. The paper is organized as follows. Section 2 shows
some of the specic application areas where sub-threshold
circuit is suitable. In section 3, we extend the traditional
CMOS logic family to sub-threshold region, and analyze the
sub-threshold characteristics of the circuit. In section 4, we
analyze the Pseudo-NMOS logic family and compare its results with sub-threshold CMOS logic family. Section 5 shows
the comparison results of both CMOS and Pseudo-NMOS
sub-threshold logic with other known low-power logic, such
as energy recovery logic. Conclusions are given in section 6.

2. APPLICATION AREAS

Sub-threshold circuits have been used quite extensively in

analog design[4; 5], but not in the digital domain. Subthreshold digital circuits will be suitable only for specic
applications which do not need high performance, but require extremely low power consumption. Such applications include medical equipments, such as: hearing aids and
pace-makers[6; 7], wearable computing[8], and self-powered
devices[9]. Sub-threshold circuits can also be applied to applications where the circuits remain idle for an extended period of time. This type of applications appears almost in every design, including the high performance microprocessors.
For example, when the microprocessor goes into deep sleep,
a specic module will poll the input devices (e.g. keyboard
or mouse) at a regular period of time. This module handles the interrupt from the input devices and is responsible
to re-awaken the microprocessor. This continuous periodic
monitoring can be done in sub-threshold mode where the
circuits consume much less power, while running at much
slower speed. Fig.1 shows the bursty characteristics of such
application. The original active time period T in strong inversion region (top half) is being extended throughout the
idle time period T 0 running in sub-threshold region (bottom half). The same number of operations is performed in
both cases, but with much lower power consumption in the
sub-threshold operation.

3. SUB-THRESHOLD CMOS LOGIC

We extend standard CMOS logic to operate in sub-threshold

region by reducing the power supply Vdd until it is below the

14

4.5

PowerDelay product vs Vdd

x 10

3.5

Figure 1: Bursty Computation in Sub-threshold Mode

Power vs Frequency (for various power supply)

10

PowerDelay product

2.5

1.5

10

Vsupply=3V

0.5

10

0.5

Power

Vsupply=1V

1.5
Vdd

2.5

10

Figure 3: Power Delay Product for Various Power Supply

10

Vsupply=0.5V

10

12

3.2 Power Delay Product

Vsupply=0.3V

10

14

10

10

10

10

10

10

10

10

Frequency

Figure 2: Power vs. Frequency for Various Vdd

transistors' threshold voltage Vth (Vdd < Vth ). This is done
to ensure that all the transistors are indeed operating in the
sub-threshold region. In the sub-threshold region, the drain
current Ids is exponentially related to the gate voltage Vgs
as shown in Eqn.1,





Vds
Ids = Io exp Vgs Vth 1 exp
(1)
Vtm
Vtm
2
where Io = WL

Cox
Vtm
. Vtm is the thermal voltage kTq

(=26mV at 25 C). For Vds > 3Vtm , Ids becomes independent of Vds for all practical purposes. In analog design, this

Fig.3 shows another important advantage of sub-threshold

circuits: lower power-delay product (PDP). The PDP for
Vdd =0.5V is about 40 times smaller than the PDP for Vdd =3V.
The lower PDP is because the reduction in power consumption outweighs the increase in delay. Our result shows that
the delay of the sub-threshold circuit is three orders of magnitude higher than the delay of strong inversion circuit, but
the power consumption is improved by four orders of magnitude. The PDP is the amount of energy per switching.
Thus, having a lower PDP means the sub-threshold circuit
consumes less energy than the normal strong inversion circuit when both circuits operate with the same amount of
switching activities. This reduction is expected as the ener2
gy per switching activity (PDP) is proportional to C
Vdd
.

3.3 Voltage Transfer Characteristics

favorable characteristic has been extensively exploited as it

provides an excellent current source that spans for almost
the entire rail-to-rail voltage range. In digital design, the
near-ideal current source characteristic improves the noise
margin of the logic gates.

The voltage transfer characteristics (VTC) of the inverter

gate running in sub-threshold mode is closer to ideal compared to the VTC in normal strong inversion region (Fig.4).
The improvement is mainly caused by the increase in the
circuit gain. The exponential relationship between Ids and
Vgs in sub-threshold region gives rise to an extremely high
transconductance gm , i.e. also exponentially related to Vgs .
The much improved VTC yields better noise margin.

3.1 Power Consumption

3.4 Transistor Sizing

Fig.2 shows the power consumption of CMOS Inverter vs.

frequency for various power supply values. The gure is
obtained by simulating a chain of inverter gates forming a
ring oscillator. From the gure, we notice that:




At higher frequency, the power consumption is linearly dependent with the operating frequency due to the
dominant dynamic power component i.e. P = CV 2 f
where  is the switching activity.
At lower frequency, the power consumption becomes
independent of operating frequency as the static power
component takes over i.e. P = Vdd
Isub threshold .
At the same operating frequency, sub-threshold circuits consume less power than the normal strong inversion circuits e.g. at f=100kHz, the power consumption from Vdd =0.5V is about two orders of magnitude
smaller than at Vdd =3V.

In the normal strong inversion region, it is well-known that

the optimum PMOS
q n to NMOS size ratio which gives a minimum delay is p where n and p are the NMOS and PMOS transconductance parameters, respectively[10]. Fig.5
shows the ratio of PMOS to NMOS of an inverter gate versus
delay for Vdd =0.5V. The wider range of atness of PMOS
to NMOS ratio means that circuit designers can have more
freedom in sizing the circuits and still obtain a near optimum delay value. The spreading of the optimum ratio is
mainly due to the exponential ratio between the PMOS and
NMOS currents.

3.5 Sensitivity to Power Supply Variation

In practice, about 10% variation in power supply (Vdd ) is expected due to various glitches and noises. The sensitivity of
the gate delay due to Vdd variation increases with decreasing
power supply value. Fig.6 shows the normalized operating

Sensitivity of Frequency to Vdd

9

Vout vs Vin (VTC) of a CMOS Inverter

3.2

2.8

6
Frequency Sensitivity

2.6

2.4

2.2

Voltages (lin)

Vdd=3.3V

1.8

1.6

1.4

Vdd=2V

1.2

1
1

0
0.5

800m
Vdd=1V

1.5

2.5

Vdd

600m

400m

Figure 6: Frequency Sensitivity to Vdd Variation

Vdd=0.5V
200m

0
0

200m

400m

600m

800m

1.2
1.4
1.6
1.8
Voltage X (lin) (VOLTS)

Design
D1: /tmp_mnt/home/karma/b/kaushik_research/work/hendra/prelim/simulation/cmos/inv/vtc

2.2
Type
DC

2.4

2.6

2.8

Wave
v(a1

Symbol

Table 1: Strong Inversion Region (Vdd =3.3V)

Logic
Power(W) Delay(s) PDP(J)
INV
3.101e-4 5.421e-11 1.681e-14
NOR-2
4.27e-4
1.211e-10 5.171e-14
NAND-2 2.243e-4 9.307e-11 2.087e-14

Figure 4: VTC for Various Vdd

8

14

Ratio of (W/L)p/(W/L)n vs Delay

x 10

er as the comparison unit. The multiplier is laid-out using

HP 0.6m process technology. All the parasitics capacitances are extracted for simulation purposes. The 217.45m
x 294.1m multiplier is shown in Fig.7. The multiplier is
fed with a series of constantly toggling input vectors. Table 3 shows the results of running the same series of input
vectors for the multiplier in both sub-threshold (Vdd =0.5V)
and strong inversion regions (Vdd =3.3V). Power saving of
nine orders of magnitude is obtained for the same amount of switching operations. The delay, however, increases by
seven orders of magnitude. The overall PDP is thus reduced
by two orders of magnitude.

13

12

11

Delay

10

3
Ratio of (W/L)p/(W/L)n

Figure 5: Size Ratio of PMOS to NMOS vs. Delay

frequency sensitivity to Vdd variation. The increase of a factor of eight in sensitivity when Vdd = 0.5V, as shown in Fig.6,
has a signicant negative impact on sub-threshold circuit.
Hence, Vdd stabilization is crucial for the proper operation
of sub-threshold circuit.

3.6 Results
3.6.1 Logic Gates
We use HP 0.35m process technology for our circuit simulation with the threshold voltages of NMOS and PMOS
transistors as 0.57V and 0.74V, respectively. Several logic gates are simulated and compared. Table 1 and 2 show
the simulation results for Inverter, 2-input NOR and 2-input
NAND gates in strong inversion and sub-threshold regions,
respectively.
3.6.2 Array Multiplier
To further conrm the power savings of the sub-threshold
circuits, we use a standard 8x8 carry-save array multipli-

4. SUB-THRESHOLD PSEUDO-NMOS

Previous section has shown that it is possible to meet the

ultra-low power requirement by operating the logic circuits
in the sub-threshold region. The trade-o is very low performance. Thus, in order to maintain the ultra-low power property while achieving some improvement in operating
speed, we use the Pseudo-NMOS logic, operating in the subthreshold region.

4.1 Robustness and Sizing Issues

In the normal strong inversion region, Pseudo-NMOS logic

is less robust compared to CMOS. To ensure that the logic gate is functioning correctly, careful sizing of PMOS to
NMOS ratio is a must in Pseudo-NMOS logic. The alwaysconducting PMOS load must be weak enough not to cause
Table 2: Sub-threshold Region (Vdd =0.5V)
Logic
Power(W) Delay(s) PDP(J)
INV
5.324e-10 4.493e-7 2.392e-16
NOR-2 6.842e-10 9.527e-7 6.519e-16
NAND-2 3.943e-10 7.417e-7 2.924e-16

Ratio of kp/kn vs Delay

x 10

3.5

Delay

2.5

1.5

0.5

Figure 7: An 8x8 Carry-Save Array Multiplier

15

Ratio of kp/kn vs PDP

x 10

2.2

PDP

1.8

1.6

1.4

1.2

5
Ratio of kp/kn

10

Figure 8: PDP vs. Sizing of PMOS to NMOS Ratio

10

Vin=0.5V
100n

Vin=0.4V

10n

Vin=0.3V

100p

LX (log)

Vin=0.2V

10p
Vin=0.1V

1p

Vin=0
100f

10f

Ids for PMOS

Ids for NMOS

1f

100e-18
0

50m

100m

150m

200m
250m
300m
Voltage X (lin) (VOLTS)

Design
D0: /home/karma/b/kaushik_research/work/hendra/postprelim/PseudoNMOS/MOS/ids
D0: /home/karma/b/kaushik_research/work/hendra/postprelim/PseudoNMOS/MOS/ids

350m
Type
DC
DC

400m

450m

Wave
D0:A0:lx(idsp0)
D0:A0:lx(idsn0)

500m
Symbol

Figure 10: Ids for PMOS and NMOS with Vdd =0.5V

Ids for both PMOS and NMOS are shown in Fig.10. The

logic gate will continue to function correctly as long as the

Ids for PMOS is within the bands of Ids curves of NMOS.
Since the Ids curves of the NMOS spans several orders of
magnitude, the sizing of PMOS to NMOS ratio becomes
less critical to ensure the proper operation. The eects of
temperature and process variation on Pseudo-NMOS which
cause Ids uctuation, may cause Ids for PMOS to be located
outside the bands of Ids currents of NMOS and thus, causing
functional error. The problem can be solved by adaptively
biasing the PMOS load[11](Fig.11). The adaptive biasing
acts as a negative feedback to ensure that the Ids for PMOS
is maintained within Ids curves of NMOS. It dynamically
adjusts the PMOS drive strength, which cannot be done in
the xed bias regular Pseudo-NMOS logic without constantly changing the size of the PMOS load.

4.2 VTC and Noise Margin

0.8

Ids of PMOS and NMOS in Pseudo-NMOS for Vdd=0.5V

1n

2.4

Figure 9: Delay vs. Sizing of PMOS to NMOS Ratio

Table 3: Results for Array Multiplier

Inversion Region Power (W) Delay (s) PDP (J)
Strong
3.339e-3
1.271e-9 4.24e-12
Weak
1.495e-12
8.294e-2 12.40e-14
any signicant burden to NMOS pull-down network (PDN)
tree, but must be strong enough to reduce the gate delay
during pull-up. Unlike CMOS, Pseudo-NMOS does not have
an optimum ratio-sizing point for minimum PDP. The PDP
will continue to increase with increasing sizing ratio of PMOS to NMOS, until the logic gate fails to function. The
delay is much higher at lower PDP. Fig.8 and 9 show the
PDP and the delay versus the sizing ratio of PMOS to NMOS, respectively.
In sub-threshold region, Pseudo-NMOS logic is more robust than its strong-inversion counterpart. This is mainly
because of the favorable device characteristics in the subthreshold region, namely: excellent voltage-controlled constant current source characteristics and exponential subthreshold slope. Sub-threshold slope (S ) is dened as the
amount of Vgs needed to change the Ids current by one
decade. S is a process-dependent parameter, e.g. TSMC
0.35m process technology gives S for NMOS and PMOS to
be 87mV/decade and 100mV/decade, respectively, for W/L
= 1.2m/0.4m at 27 C. For sub-threshold Pseudo-NMOS
logic with Vdd =0.5V, the Ids for NMOS will vary by almost
six orders of magnitude due to its sub-threshold slope. The

5
Ratio of kp/kn

The VTC and the noise margin of Pseudo-NMOS in strong

inversion region worsen with stronger PMOS load (Fig.12).
In the sub-threshold region, however, the VTC is very similar to the ideal curve (Fig.13). The voltage levels swing

Vdd

Vdd

Vdd

Output
NMOS
Network

Input

Vss

Vss

Vss

Figure 11: Adaptively-biased Pseudo-NMOS

Figure 13: VTC of Sub-threshold Pseudo-NMOS INV

Table 4: Sub-threshold CMOS and Pseudo-NMOS Logic
CMOS
Pseudo- NMOS
Logic
Power
Delay
Power
Delay
INV
4.886nW 223.4ns 31.86nW 54.74ns
NOR-4 6.064nW 803.4ns 31.87nW 70.54ns
NOR-8 6.852nW 1808ns 31.87nW 91.60ns
NOR-16 7.815nW 4482ns 31.87nW 133.7ns
FA
4.691nW 1377ns 23.06nW 221.9ns
Figure 12: VTC of Normal Pseudo-NMOS INV
rail-to-rail, and does not suer from low logic level degradation problem as with the case of the strong inversion case.
The ratio of PMOS to NMOS only shifts the VTC sideways
i.e. only aecting the noise margins, but not the functionality of the gate.

4.3 Advantages Over CMOS Logic

With the PMOS pull-up network tree of CMOS logic being

replaced by a single PMOS transistor, Pseudo-NMOS logic
consumes less area than CMOS. The gate and interconnect
wire capacitances are also reduced because the output node
needs to be connected to only the NMOS pull down tree network. Thus, Pseudo-NMOS operates faster than CMOS and
consumes less area. The advantages are even more signicant for wide NOR-like gates due to the absence of the long
chain of series-connected PMOS transistors. In strong inversion region, the two main disadvantages of Pseudo-NMOS
as compared to CMOS are higher power consumption and
less robustness. However, in sub-threshold region, these disadvantages are eliminated. The power consumption and the
robustness of Pseudo-NMOS are comparable to CMOS logic.

4.4 Experimental Results

We compare the sub-threshold Pseudo-NMOS logic with

sub- threshold CMOS logic. In the comparison, we use the
same optimized eective ratio sizing of PMOS to NMOS.
We simulate logic gates connected in a ring oscillator using
TSMC 0.35m process technology. The following gates: In-

verter, 4-input NOR, 8-input NOR, and 16-input NOR, were

used in our experiments. We also use standard Full Adder
(FA) in our comparison by analyzing the Carry chain. Table
4 shows the experimental results.

5. ADIABATIC LOGIC

To validate the power savings of sub-threshold logic, we

compare it with other known low-power logic, such as adiabatic logic[12; 13; 14]. Quasi-static energy recovery logic
(QSERL)[15] is used to represent the adiabatic logic family. QSERL is chosen due to its close resemblance to static
CMOS (Fig.14).  and  are out-of-phase sinusoidal power supply. The diodes are used to break the circuit during
the hold time and are transparent during the normal evaluation period. We implement QSERL and simulate it using
TSMC 0.35m process technology. Due to the high leakage current in the transistors, the QSERL logic gate does
not hold its outputs constant during the hold time period
as expected. The deterioration of the node voltages due to
the leakage is more pronounced when the logic gates are
operated at slow speed. Often times, the instability of the
node voltages cause the gates to have erroneous switching
and produce incorrect results. Moreover, the capacitances
between the gate with the drain and source act as bootstrap
capacitances which further deteriorate the output voltage.
The eects of the leakage current and capacitances are worsened by the constantly oscillating power supply. Thus, it is
quite a challenge to implement and to ensure the circuit to
function correctly. In our implementation, we use a number of idealized assumptions to get better result for QSERL

6. CONCLUSIONS

PMOS

PMOS

PMOS

Network

Network

Network

NMOS

NMOS

NMOS

Network

Network

Network

7. REFERENCES

Figure 14: QSERL

Inverter

4
3.5

60

MO
oN

MO
oN
ud
se

b-P
su

ud

ER

MO

QS

b-C
su

se

b-P

su

10

0.5

20

ER

30

MO

1.5

40

QS

50

b-C

2.5

su

Energy/switching in fJ

3
Energy/switching in fJ

4input NOR

70

In this paper, we have studied various characteristics of digital circuit operating in sub-threshold region as a mean to
achieve ultra-low power. The sub-threshold logic can be easily implemented and derived from the traditional existing
circuits by lowering the supply voltage to be less than the
threshold voltage. A number of advantages in sub-threshold
operation includes improved gain, noise margin, and tolerant
to higher stack of series transistors while being more energy
ecient than standard CMOS at the same frequency of operation. However, due to its slow performance, sub-threshold
circuit is limited to only certain applications where ultralow power is the main requirement, and performance is of
secondary importance.

Figure 15: PDP of QSERL and Sub-threshold Logic

logic:

The sinusoidal power supply is being supplied by perfect oscillator with 100% eciency, and thus consumes
no power. In reality, most oscillators have only 80-90%
eciency.

The diodes are implemented with ideal Schottky diodes

with Vth =0.12V, instead of diode-connected, low Vth
transistors. The leaky transistors cause a problem in
holding the output voltage value during the long hold
time period.

We simulated a chain of Inverter and 4-input NOR gates.

In order to compensate for the high leakage current and
help stabilize the output node voltage during the hold time,
we inserted 0.5pF capacitances in between the gates in the
chain. The capacitances will not cause any additional power
consumption in QSERL, since the charges used in charging
the capacitances are being recovered by the power supply.
Despite all the idealizing assumptions made in the implementation, QSERL still consumed more energy than subthreshold logic (Fig.15).

[1] J. Frenkil, \A Multi-Level Approach to Low-Power IC

Design", in IEEE Spectrum, volume 35, pp. 54{60,
February 1998.
[2] M. Horowitz, T. Indermaur and R. Gonzalez, \LowPower Digital Design", in IEEE International Symposium on Low Power Electronics and Design, pp. 8{11,
1994.
[3] A. P. Chandrakasan, S. Sheng and R. W. Brodersen,
\Low-Power CMOS Digital Design", in IEEE Journal
of Solid State Circuits, volume 27, pp. 473{484, April
1992.
[4] C. Mead, Analog VLSI and Neural Systems, AddisonWesley Publishing Co., 1989.
[5] E. Vittoz and J. Fellrath, \CMOS Analog Integrated
Circuit Based on Weak Inversion Operation", in IEEE
Journal of Solid-State Circuits, pp. 224{231, June 1977.
[6] L. A. Geddes, \Historical Highlights in Cardiac Pacing", in IEEE Engineering in Medicine and Biology
Magazine, pp. 12{18, June 1990.
[7] A. P. Pentland, M. Petrazzuoli, A. Gerega and T. Starner, \Digital Doctor: An Experiment in Wearable
Telemedicine", in International Symposium on Wearable Computers, Digest of Papers, pp. 173{174, 1997.
[8] T. Starner, \Human-Powered Wearable Computing", in
IBM Systems Journal, volume 35, pp. 618{629, 1996.
[9] R. Amirtharajah and A. P. Chandrakasan, \SelfPowered Signal Processing Using Vibration-Based Power Generation", in IEEE Journal of Solid-State Circuits, volume 33, pp. 687{695, May 1998.
[10] J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice-Hall Inc., 1996.
[11] F. Lu and H. Samueli, \A High-speed CMOS Fulladder Cell Using a New Circuit Design Technique Adaptively-biased Pseudo-NMOS Logic", in IEEE International Symposium on Circuits and Systems, volume 1, pp. 562{565, 1990.
[12] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis
and E. Ying-Chin Chou, \Low-power Digital Systems
Based on Adiabatic-switching Prin- ciples", in IEEE
Transactions on Very Large Scale Integration (VLSI)
Sys- tems, volume 2, pp. 398{407, December 1994.

[13] A. G. Dickinson and J. S. Denker, \Adiabatic Dynamic

Logic", in IEEE Journal of Solid-State Circuits, volume 30, pp. 311{315, March 1995.
[14] Y. Ye, K. Roy and G. Stamoulis, \Quasi-static Energy
Recovery Logic and Supply-clock Generation Circuits", in IEEE International Symposium on Low Power
Electronics and Design, pp. 96{99, 1997.