Comparative study of Different VLSI Design Flow Techniques

Sunil Jangid*, Jitendra Gupta**, Rajesh Kumar*** Student, M.Tech. of PCE, Jaipur.*Student M.Tech. PIT, Punjab**, Lecturer in SPSU, Udaipur***

1. Abstract: The word digital has made a dramatic impact on our society. More significant is a continuous trend towards digital solutions in all areas from electronic instrumentation, control, data manipulation, signals processing, telecommunications etc., to consumer electronics. Development of such solutions has been possible due to good digital system design and modeling techniques. In VLSI there are too many factors that affect the performance of the designed circuit. Basically the design parameters are Area Speed and Delay. The area is referred as the total chip area and the speed is the speed of the designed circuit and delay is the total propagation delay of the circuit. In general we can minimize the area using very low level type of technology like 99ns, 45ns, etc. If we go toward the decreasing order of technology the area tends to decrease but complexity is tends to increase. The parameter area is inversely proportional to the speed. As we reduce the area the speed increased. To design the circuit in VLSI we have to use a specific Procedure that is well defined as Design Flow [1]. As long as technology increases the complexity of circuit also increase. To overcome the problem of complexity different types of design flow are used. Here we are going to compare the power efficiency of the design flow. In general there are three types of design flow according to performance they are used as per technology demand. They are ASIC, Semi custom, FPGA based design flow. In This Paper we are studying that which design flow is efficient for the different technology.
Key Words: VLSI design Flow, Different Design Style, Comparison of Design Flow, Logic Design Flow performance.

intermediate between ASICs and industry standard integrated circuits like the 7400 or the 4000 series. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SOC (system-on-chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. The initial ASICs used gate array technology.

2. ASIC design flow: An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC[2]. Application-specific standard products (ASSPs) are

Figure-1 Design flow for VLSI logic circuits

An Application Specific Integrated Circuit (ASIC) is a semiconductor device designed especially for a particular customer (versus a Standard Product, which is designed for general use by any customer) The three major categories of ASIC Technology are : Gate-Array-Based Standard-Cell-Based Full custom I. Gate array Based: Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization[in other words, unconnected. The physical design process then defines the interconnections of the final device. For most ASIC manufacturers, this consists of from two to as many as nine metal layers, each metal layer running perpendicular to the one below it. Nonrecurring engineering costs are much lower, as photolithographic masks are required only for the metal layers, and production cycles are much shorter, as metallization is a comparatively quick process [2]. There are two types of Gate Array Channel Gate array Channel less gate array A channeled gate-array is manufactured with single or double rows of basic cells across the silicon. A basic cell consists of a number of transistors. The channels between the rows of cells are used for interconnecting the basic cells during the final customization process

II. Standard cell-based: In the mid 1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers. Most designers ended up using factory-specific tools to complete the implementation of their designs. A solution to this problem, which also yielded a much higher density device, was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance that could also be represented in third-party tools. Standard Cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost [2]. III. Full custom: By contrast, full-custom ASIC design defines all the photolithographic layers of the device. Full-custom design is used for both ASIC design and for standard product design [4]. The benefits of full-custom design usually include reduced area (and therefore recurring component cost), performance improvements, and also the ability to integrate analog components and other predesigned and thus fully verified components, such as microprocessor cores that form a system-onchip [8]. The disadvantages of full-custom design can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the computer-aided design (CAD) system, and a much higher skill requirement on the part of the design team. For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems, can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimize any performance-limiting aspect of the design.

A channel-less gate array is manufactured with a sea of basic cells across the silicon and there are no dedicated channels for interconnection. Gate arrays contain from a few thousand equivalent gates to hundreds of thousands of equivalent gates. Due to the limited routing space on channeled gate arrays, typically only 70% to 90% of the total number of available gates can be used [8]. The library of cells provided by a gate array vendor will contain: primitive logic gates, registers, hard-macros, soft-macros. Hard-macros and soft-macros are usually of MSI and LSI complexity, such as multiplexers, comparators and counters. Hard macros are defined by the manufacturer in terms of cell primitives Softmacros are characterized by the designer, for example, specifying the width of a particular counter

Semi Custom Design approach: Semicustom engineering is a new concept when it comes to custom application/product engineering. EMAC has been doing custom engineering since 1984. Since that time EMAC has developed a wide array of single board computers, peripherals, and development software. These off-the-shelf products have a wide variety of features allowing them to be easily

incorporated into a number of applications. Typically EMAC can make use of these off-the-shelf items along with an arsenal of ready to run library routines and device drivers in a custom application. This semicustom approach provides the customer with a substantial cost savings and time savings over a fully custom approach [2].

FPGA based Design: On the highest level, an

FPGA consists of programmable logic elements and programmable routing resources used to interconnect the logic elements. The logic elements implement the combinational and Sequential logic functions the user wants to implement in the FPGA and the routing resources interconnect logic elements to implement the desired system [3]. FPGA design usually consists of an array of identical blocks of logic and routing resources called tiles. Logic element (LE) is connected to two connection boxes: connection box right (CBR) and connection box bottom (CBB). The

CBR connects the vertical routing tracks to the inputs of the LEs on its left and right, while the CBB connects the horizontal routing tracks to the inputs of the LEs above and below it, and connects the output of the LE above it to the routing tracks. Finally, the switch box (SB) interconnects the horizontal and vertical routing tracks. Our FPGA contains 4 vertical and 4 horizontal routing tracks. The LE, connection boxes, and the switch box contain SRAM cells that can be programmed to implement desired functionality [5][2][7]. The basic parameters that are to be compare for the design flow are: cost, speed, area, efficiency, complexity, life time, programmability.

3. Comparison of different design style S.no. Parameter 1. 2. 3. Design Cost Speed Area required Full Custom High Very fast for Designed Circuit Less Semi -Custom Low Fast for all Designed Circuit Area Manipulate according to circuit Less Programmable reduced Less as to Full Custom Depend on the Circuit design FPGA Very low High Speed As the No. of LB increase Required Area also increased very Less Programmable Very Low Not so complex to design Circuit High for Complex Circuit

4. 5. 6. 7. 8.

life time

High

Programmability Can't Changed Prototype-time complexity accuracy High Very Complex Very high for designed

Figure-2 Compression of Parameter of Different Design Flow

Figure-3 Circuit Performance of Full & Semi customs Design

4. Conclusion:
As we studied about the Different Design Styles of The VLSI Design we conclude that if the Performance or Design Density is of Primary Importance. The Physical Design seems to be the Only Options. The Full Custom Design is the best option to design. The Design Process in which the designed circuit is the prime criterion the design cost is not the prime design principle the Full Custom Design is Preferred. Benefits of Custom Design Because only your desired features are provided, costs are reduced. The required features, functions, and options can be placed on one printed circuit card, reducing costs. Plug in options, functions, and features, reduce costs and inventory. Installation time is reduced by eliminating wiring and cabling. Generally, for custom designs, space requirements are reduced. Benefits of Semi Custom There is substantial cost savings compared to a fully custom approach. Typically over 80% of the hardware development cost is saved. Prototype time is dramatically reduced. Because we are intimately familiar with our off-the-shelf hardware and development software, prototypes are completed rapidly. For applications requiring only a few pieces, the semicustom approach offers easy part

replacement for off-the-shelf components, allowing easy maintenance and repair.

As shown in Fig 3 that the full custom design has more opportunity for performance improvement and also have the longer design time until maturity, While Semi custom design has the less opportunity for performance improvement and have shorter design time until maturity.

5. References:
[1]Cadence. Encounter Design Flow Guide and Tutorial, Product Version 3.3.1, February 2004.

[2] Chinnery, D., Keutzer, K., Closing the Gap Between ASIC and Custom, Kluwer Academic Publishers, 2002. [3] A. Sharma, C. Ebeling, S. Hauck, "ArchitectureAdaptive Routability-Driven Placement for FPGAs",International Symposium on FieldProgrammable Logic and Applications, 2005.
[4] W. J. Dally and A. Chang. The role of custom designin ASIC chips. In DAC '00, pages 643{647, 2000. [5] S. D. Brown, R. Francis, J. Rose, and Z. Vranesic. Field-programmable gate arrays. Kluwer Academic Publishers, 1992.

[6] www.mosis.org [7] S. Baker. Quicklogic unveils FPGA. EE Times, 639, April 1991. [8]S. L. Hurst, D. M. Miller, and J. C. Muzio. Spectral Techniques in Digital Logic. Academic Press, 1985.