D-Type Latch II

TUTORIAL OBJECTIVES

Use a data flip-flop to create clock division circuits Create 4-bit binary counters using data flip-flops.

Clock Division Circuits

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The hardware of our computer runs at different speeds. The different busses and components actually specify what maximum speed clock they can use for their edge triggered operations. The fastest signal is the clock signal of the processor. This signal is shared between other hardware components that run slower than the processor. In order for those to share this signal, the signal frequency must be divided by certain circuitry. The Data Flip-flop can be used to do such division using a circuit shown below.

CLK Q

This circuit is simply a Data Flip-Flop but with its Q signal connected to its Data (D) input. We will do a few examples to show how this new circuit works. Move onto Frame 2 and follow the frames on Example 1.

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EXAMPLE 1

A D-Type Flip-Flop is shown with its initial logical state. For the following clock signal (CLK), complete the timing diagram for Q and D.

CLK Q

CLK

Now, we know that when we reach the next rising clock signal, the value of D is copied across to Q. So at the first dotted line, we can draw in the new value of Q. Hence we get a new diagram of ...

3
CLK

Because ... at the dotten line, the clock rising from 0 to 1 triggers the flip flop to copy the value of Data D, equal to 1 across to Output Q. So Q is now equal to 1. So now that Q is equal to 1, look back at our diagram:
1

CLK Q

We can see that Q must now be 0 and because it is being fed around to D we can say that D is now 0. This all happens in one go when the clock rising from 0 to 1. On our timing diagram we can now show the new value of D which would give a diagram of ...

CLK

So after first edge-triggered operation, our data flip flop has the new state of.

CLK Q

Now we can extend the values of D and Q up until the next edge triggers an operation. This would give us a new diagram of ...

5
CLK

Now we are at the next clock edge. Here, using the same reasoning as before: flip-flops copy the value of D across to Q on clock edges, so find the new values of both D and Q ...

CLK

Because before the edge-triggered operation we had the state:

1 0

CLK Q

On execution of at edge, D is copied to Q so we now have:

1

CLK Q

Giving on the timing diagram:

CLK

Now that Q is 0, Q must now be 1 and because it is being fed around to D we can say that D is now 1. Hence we get the timing diagram shown below.

CLK

Again, we can extend the values of D and Q up until the next edge triggers an operation. This would give us a new diagram of ...

CLK

Now on this edge, complete the diagram to show the new values of Q and D. Remember that the circuit now looks like:
1 0

CLK Q

CLK

This is because ... at the rising edge, D is copied to Q so we now have:

1

CLK Q

Giving on the timing diagram:

CLK

Now that Q is 1, Q becomes 0 as they are always opposite. So D is also now 0. So we get a new advance on the timing diagram:
CLK

We can extend the values of D and Q until the next clock rise but we will stop there. If we wanted to, we could continue performing the edge-triggered operations but we will stop.
CLK

Now compare this signal...

D

with this signal...

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If we compare the time peroid of these peroid signals, we can see that the time peroid of Q is twice as long as the time peroid of CLK.
CLK

CLK time period Q

CLK Q

Q signal time period

Write this in your notes then move onto frame 10.

10
Now we can go back to talking about the components of a computer.

D Oscillating Crystal 1.0 MHz

0.5 MHz Component Requiring 0.5Mhz

CLK Q

Central Processing Components

Here we imagine a system with a processor with a clock rate of 1.0 MHz. By using a our circuit we can divide this high frequency by two (equivalent to doubling the time peroid) and output this signal to other parts of the computer hardware that can operate at this clock. Of course, a real computer system would be far more complex and you certainly would not find a single flip-flop like this seperating components. To put things in perspective, you may remember that the Intel Pentium IV processor has around X transistors in its small central processing microchip. Other computer components would also have thousands of transistors. Going back to our imaginary system however, what is the easiest way to obtain a clock signal of 0.25MHz? Remember that we already had signal of 1.0MHz and got a signal of 0.5MHz. Think about it then move onto Frame 11 to compare answers.

11

Use another D-type flip-flop to divide the 0.5MHz clock by two

You probably noticed the simple solution of dividing the 0.5MHz clock signal; giving a signal of twice the time period, with a frequency of 0.25MHz. Such a circuit looks like this:
Q1 Q2

D1
CLK1

Q1 Q1

D2
CLK2

Q2 Q2

Here we are using two Data Flip-flops. This circuit has one input (CLK) and has two outputs (Q1 and Q2). Notice that Q1 will be the input clock signal with its frequency divided by two and Q2 will be the input clock signal with its frequency divided by four. So for example:
Q1 0.5 MHz Q2 0.25 MHz

D1 1.0 MHz
CLK1

Q1 Q1

D2
CLK2

Q2 Q2

Lets do an example to see how this circuit works. Move onto frame 2 and follo the frames on Example 1.

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EXAMPLE 2

The Data Flip-Flops shown below are connected together. For their initial logical state, complete the timing diagrams for Q and D. (a) D1, Q1, and Q1 (b) D2 and Q2

Q1
0 1 1 1 1

Q2
0

D1
CLK

Q1 Q1

D2
CLK

Q2 Q2

CLK

For part (a) we have the following timing diagrams to complete:

D1

Q1

This time we are additionally going to complete the diagram for Q1 to make part (b) easier.
Q1

Now extend these diagrams until the first rising edge and perform the flip-flop operation; giving the new values of D1, Q1 and Q1 ...

13

D1

Q1

Q1

This is because when we are coming up the rising edge the state of the flip-flop (the leftmost flip-flop) is such that D1 is equal to 1 and Q1 is equal to 0. On the clock edge, the flip-flop operates by setting Q1 equal to D1. So now Q1 is 1.

This gives us the following:

D1

Q1

Q1

But we now remember that D1 is connected to Q1:

Q1
1

Q1 is now 1

D1
CLK

Q1 Q1

Because Q1 is now 1, Q1 falls to 0 and because D1 is connected to Q1, D1 also falls to 0. Hence we have the timing diagrams that look like:
CLK

D1

Q1

Q1

Now repeat the same process at the next clock signal to work out the new values of D1, Q1 and Q1. The diagram you should get should be ... Complete the diagrams above up until the next clock edge and check with Frame 14

14

D1

Q1

Q1

Because when we arrive at the second rising edge the state of the flip-flop has D1 is equal to 0 and Q1 is equal to 1. On the clock edge, the flip-flop transfers D1 equal to Q1. So now Q1 is 0. So this means that Q1 and D1 are now equal to 1.
Q1
0

Q1 is now 0

so D1 is now 1
1

Q1
0

D1
CLK

Q1 Q1

D1
CLK

Q1 Q1
1

so Q1 is now 1

So now we have:
CLK

D1

Q1

Q1

Hopefully by now, you are getting the hang of this. At each clock edge, the same thing happens so indeed, explaining each stage becomes trivial once youre used to whats going on. So I leave it to you to complete the rest of the diagrams for D1, Q1 and Q1. Finish the three timing diagrams completely and check it agrees with Frame 15

15

CLK

D1

Q1

Q1

If you correctly got the above, then move onto frame 16. Otherwise, stay here to find out where you went wrong as the solution is explained.

16
Now that we have got a clock we will use Q1 as a clock input to our second flip-flop. This is where we start to answer part (b). So we will copy its signal below.
Q1

Now notice that we will add the upwards arrows to help remind us that those edges are used for triggering operations on right-hand flip-flop.

Part (b) of the question asks us to find the timing diagrams for D2 and Q2. From the diagram it gave, it showed us that initially, D2 is 1 and Q2 is 0.
Q1

D2

Q2

Now to finish Example 2, we just need to repeat the process for the second flip-flip. So complete the diagrams above. Finish the two timing diagrams completely then move on to Frame 17

17
Q1

D2

Q2

If you managed to get the above, then move onto Frame 18. Otherwise, stay here to see what errors you have made.

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REVISION QUESTIONS

Binary Counters
20
Another fundamental circuit is a binary counter. Remember that each flop can represent two states. So a flip-flop can represent the numbers 0 and 1. Similarly two flip-flops can hold four states and three flip-flops can hold ... states.

21

eight

And in general n flip-flops can store 2n states. So going back to our binary counter circuit. If we want a circuit that can count from zero to seven slowly: 0 ... 01 ... 10 ... 11 ... 100 ... 101 ... 110 ... 111 - then we would need need ... flip-flops because our system has ... states.

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we would need need three flip-flops because our system has eight states

If we wanted a system that counted from 0 to 127, then we would need seven flip-flops. So then, how many data-type flip-flops do we need to count from (a) 0 to 255 (b) 0 to 63 (c) 0 to 7 (d) 7 to 0 (e) 1 to 16 (f) 1 to 4 (g) 8 to 1

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(a) 8 (b) 6 (c) 3 (d) 3 (e) 4 (f) 2 (g) 3

Notice that we want to instead, design a circuit that counts down rather than one that counts up. In either case, we will still need as many n flip-flops to store 2n binary numbers existing to stored in the circuit. Essentially, each flip-flop would represent a binary digit. So what does this binary counter circuit look like? It may seem a bit familiar:
Q1 Q2 Q3

D1
CLK

Q1 Q1

D2
CLK

Q2 Q2

D3
CLK

Q3 Q3

This is exactly the same circuit that would be used for dividing a clock frequency by three. So how can this same circuit be used as a counter? Notice that there are three d-type flipflops. So this circuit is probably be used to count from zero to seven (or maybe from seven to zero). To understand fully, we look in detail at the timing diagrams for this circuit.

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Here is the timing diagram for Q1, Q2 and Q3.
Q1

Q2

Q3

tA

tB

tC

tD

tE

tF

tG

tH

tI

tJ

Consider the values of these three variables at the certain times highlighted on the diagram. The first of these times is at tA, where Q1 is 0, Q2 is 0 and Q3 is 0. The state of the system at this time is:
Q1
0

Q2

Q3

If we start to fill in a table, then with the first row it would look like: tA tB tC tD tE tF tG tH tI tJ Logic of Q3 0 Logic of Q2 0 Logic of Q1 0

Notice that the column headers are in descending order of: Q3, Q2 then Q1. Now onwards to tB. Here, the new state of the system has: Q1 at ..., Q2 at ... and Q3 at ...

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Q1 at 1, Q2 at 0 and Q3 at 0

So the second row of the table would look like ...

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tA tB tC tD tE tF tG tH tI tJ Logic of Q3 0 0 Logic of Q2 0 0 Logic of Q1 0 1

And the circuit with the logic of Q1, Q2 and Q3 would look like ...
Q1
1

Q2

Q3

Now complete rows of the table for times tC to tJ showing the values of Q1, Q2 and Q3. For convenience, the timing diagrams have been repeated below.
Q1

Q2

Q3

tA

tB

tC

tD

tE

tF

tG

tH

tI

tJ

Take your time to complete the table for the remaining times and move onto Frame 27.

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tA tB tC tD tE tF tG tH tI tJ

Logic of Q3 0 0 0 0 1 1 1 1 0 0

Logic of Q2 0 0 1 1 0 0 1 1 0 0

Logic of Q1 0 1 0 1 0 1 0 1 0 1

You shouldve got the table above. The logical state of the three flip-flop circuit is summarised below for the times tA to tJ.
Q1
0

Q2

Q3

Q1

Q2

Q3

tA

0
Q1
1

0
Q2
0

0
Q3
0

tF

1
Q1
0

0
Q2
1

1
Q3
1

tB

1
Q1
0

0
Q2
1

0
Q3
0

tG

0
Q1
1

1
Q2
1

1
Q3
1

tC

0
Q1
1

1
Q2
1

0
Q3
0

tH

1
Q1
0

1
Q2
0

1
Q3
0

tD

1
Q1
0

1
Q2
0

0
Q3
1

tI

0
Q1
1

0
Q2
0

0
Q3
0

tE

tJ

By now, you should realise that the circuit is a binary counter that counts from zero to seven. Notice that once the system has counted up to 1112, it resets back to 0, then it will continue counting again. This occurs at tI. Each flip-flops Q contributes to a digit of our binary representation. So three Flip-Flops give a three digit binary representation for counting with. The biggest number we can count to is 1112 which is equivalent to 710. Also note that it is Q3 that contributes to the MSB not Q1. Remember that the table we completed is arranged Q3, Q2 then Q1, not Q1, Q2 then Q3. You could say that the counters bits are reversed when we are to look at the actual flip-flop system circuit. So for example at tG, the number we were currently on was 1102 which looked like:
Q1
0

Q2

Q3

tG

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To summarise, the circuit below counts the binary numbers from 0002 to 1112.
D1 D2 D3

D1
CLK

Q1 Q1

D2
CLK

Q2 Q2

D3
CLK

Q3 Q3

The outputs D1, D2 and D3 represent the binary number D3D2D1. Make a note of this in your exercise book then move onto Frame 29.

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