HDA Codec Layout Guide

HIGH DEFINITION AUDIO (HDA) CODEC LAYOUT GUIDE Introduction

To ensure maximum performance from the High Definition Audio (HDA) codec, proper component placement and routing are very important. This document includes properly isolating the digital circuitry and analog circuitry, The effects of ground and supply plane geometry, decoupling/bypassing/filtering capacitors placement priorities, LINK signals, analog power supplies, and analog ground planes.

The layout design of Ground and Supply plane Geometry Figure.1 shows a top view layout for onboard HDA codec. The layout separates the analog and digital ground planes with a 60 to 100 mils gap. The moat helps to isolate noisy digital circuitry from quiet analog audio circuitry. The digital and analog ground planes are tied together by a wide link, about 50mils, at one point and only one point beneath the codec. This will be the "drawbridge" that goes across the moat. Do not allow any digital or analog signal traces pass through the drawbridge, otherwise, the digital noise may be induced into the analog signals, makes audio performance worse. Similarly, NO SIGNALS WHATEVER are permitted to cross the moat (to do so creates a "slot antenna" radiator which will hammer your PCB layout with crosstalk, and create huge amounts of EMI, totally defeating your purpose). In HDA codec layout, the major difference is the JACK DETECTION. Because of during sensing procedure, each sense pin will sense the corresponding resistors network that may interfere the performance of analog signal. In order to avoid such a situation, layout must pay attention at two points: one is the resistors network should be placed as close as possible to the sense pin. Another is the layout traces between the resistors network and HDA jack should away from any analog trace because sensing current might distorts the audio performance. The bottom layer is best choice. In additional, in order to present the best audio performance and prevent cross-talk issue from having no enough space between left and right channels. Realtek recommended to layout the width of each IN/OUT signal traces at least 10 mils and the space is the least one time the size of width of signal trace.

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PORT-D-R

PORT-D-L

Sense B

VREFO-B-R

VREFOE-R VREFOF-R VREFO-C-L VREFO- -L B

VREF AGND AVDD

+3.3DVdd

DGND SDIN

SYNC RESET

GPIO0

GPIO1 DGND

SDOUT

BITCLK

PCBEEP

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HD JACK (O Combo Jack) pen The widt of IN/OUT signal t ces are the least 10 mils h ra The space is the least one time the size of width of the signa l (Acco rding to the 3 W rule, the best width of spacing is 3 time o f width of the signal ). s Resistors Netwo rk Re altek suggeste d that layout trac of the sense pin should away e from a ny an g tra because se nsing current might distorts the alo ce a udio perfo r ance. (The bottom layer is best choice.) m +5AVdd

REGU LATOR

+5A Vdd

+12DVdd

Usi ng the Ferrite Bead to minimi ze stray noise causi ng current

Regions between analog signal trace should be fille d with copper , which should be attached to the analog ground plane. By passin and decoupling capacitors should be g clo to the IC pins, or positioned for the se shortest connection to pin with WIDE traces to reduce im pedance.
PORT-C -R PORT-C -L POR T-B -R PORT-B -L CD-R CD-GN D CD-L PORT-F -R POR T-F-L PORT-E -R PORT-E -L Sens eA

AVDD
+5 A Vdd

Analog Compo ent n & Analog Ground PORT-A-L PORT-A-R AGND Analog and Digital GND c onne ted at o e point c n beneath c odec

Figure.1 HDA Layout Guide

SPDIF- N/EAPD I S/PDIF -OUT +3.3DVdd R esistors Network

Split by Digital ground

An alog Components & Analog Ground

Digital Com ponent & Digital Ground

Regions between digital signal trace should be filled with copper , which should be attached to the digital ground plane. :V to the bo ia ttom layer :Via to the po wer plane :Via to the ground plane :T hroug hole to opposite layer h

HDA Codec Layout Guide

1. The codec is partitioned into a digital and analog section to s help isolate noisy digital circuitry from quiet analog circuitry. 2. The layout separates the analog and digital planes with a 60 to 100 mils gap and connect them at one point beneath the codec w a 50 mils wide link. ith 3. Never route digital traces or digital planes under the analog ground areas. Analog components should be located over analog planes (ground and power planes) and digital components should be located over digital planes.

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HDA Codec Layout Guide

For a layout that helps to reduce noise, separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. In addition to ground planes scheme, digital and analog power supply planes should be partitioned directly over their respective ground planes. Placing analog power coincident with analog ground, and digital power coincident with digital ground (as Figure.2 Recommended separation). If any portions of analog and digital plane overlap, the distributed capacitance (result from power plane reference to ground plane or signal plane reference to ground plane ) between the overlapping portions will couple digital noise into the analog circuitry. This defeats the purpose of isolated plane (as Figure.2 wrong separation). The power and ground planes should be separated by approximately 40mils for the four layer PCB design. Using power and ground planes forming a natural, high capacitive, bypass capacitor to reduce overall PCB noise.

WRONG
ANALOG SIGNAL PLANE
DIGITAL SIGNAL PLANE

distributed capacitance
ANALOG GROUND

DIGITAL GROUND PLANE

ANALOG POWER PLANE

DIGITAL POWER PLANE

ANALOG SIGNAL PLANE

DIGITAL SIGNAL PLANE

RIGHT
ANALOG SIGNAL PLANE DIGITAL SIGNAL PLANE

PCB ISOLATION
ANALOG GROUND PLANE DIGITAL GROUND PLANE

Natural Capacitance .

ANALOG POWER PLANE

DIGITAL POWER PLANE

ANALOG SIGNAL PLANE

DIGITAL SIGNAL PLANE

Figure.2 Cross section of PCB, the recommended separation for analog and digital plane.

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HDA Codec Layout Guide

Figure.3 Recommended capacitor placement

Decoupling and bypassing capacitors

Bypass capacitors on the PCB are used to short digital noise into ground . Commonly, codec may generate noise when its internal digital circuitry is operating. The current changes arise in the power and ground pins for the related section of the codec. The goal is to force AC currents to flow in the shortest possible loop from the supply pin through the bypass cap and back into the codec through the nearby ground pin. A bypassing circuit is supposed to be a low lead inductance between the codec and the bypass capacitors when in the operating frequency of the codec. The longer the trace the greater the inductance. To avoid long-trace inductance effects, use the shortest possible traces for bypass capacitors, with wide traces to reduce impedance. For best performance, use supply bypass leads of less than one-half inch.

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HDA Codec Layout Guide

In Figure 3, Pins with a first A priority components placed around the codec are the bypass caps, which are located as close as possible to the supply pins. The capacitors must have low inductance and low equivalent series resistance (ESR). Tantalum 10F surface mount devices are good if they are used in conjunction with 0.1F ceramics. The filter capacitors with B priority, the reference filter to stabilize the reference voltage for internal Ops and reference output filters should be placed close to codec. A good reference voltage is relative to good analog performance. These decoupling capacitors (C priority) should be close to the codec pins (pin-12 to pin-24), or positioned for the shortest connections to pins, with wide traces to reduce impedance. The Table I also point out the distribution of codec capacitor locations and placement priorities. Table I. Capacitor placement priorities Signal Description Digital Supply Voltage , +5DVdd Analog Supply Voltage, +5AVdd Voltage Reference Filter(V REF) Voltage Reference out (V REF_OUT) Analog Signal Inputs(Decouple) Package Pins 1,9 25,38 27 28,29,30,31,32 12 ~ 24 Priority of Close Proximity to Codec Pin Placement of Filter and Decoupling Capacitors A A B B C

The LINK Trace The LINK signals operated at 24MHz bit block rate, it is sensitive to trace length. A long trace causes a slow rising time makes operation is unstable or failed. Figure.4 describes topology configuration that has been simulated on a four layers microstrip desktop platform by INTEL. It is expected that system level simulations will be done using actual trace and board model.

1-3" Host Controller 0.5-9" R 1-5" -0.5" Modem Codec Audio Codec

Figure 4. Recommended link trace

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HDA Codec Layout Guide

The Anti-Glitch Capacitors In practical situation, it is possible that there are glitches induced on LINK signals. Glitch on RESET- generated by chipset makes a misunderstanding to reset codec in run time. Glitch on SYNC makes codec loss synchronization with chipset, analog output will be corrupted. BCLK generated by controller sometimes has ring -back or overshoot phenomenon due to impedance mismatch at receive terminal, it may cause unstable LINK operation. Figure 6 suggests system designer reserve some anti-glitch capacitors at LINK bus, Ce10 and Ce11 used to anti-glitch on SYNC and RESET-. The ring-back resister Re6 and Ce6 are used to suppress overshoot and control slew rate on BCLK.

Figure 5. Reserved anti-glitch capacitors on LINK bus

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