TMS320C54x DSP Reference Set

Volume 1: CPU and Peripherals

Literature Number: SPRU131F April 1999

Printed on Recycled Paper

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 1999, Texas Instruments Incorporated

Preface

Read This First

About This Manual
The TMS320C54x is a fixed-point digital signal processor (DSP) in the TMS320 family. This book, the first volume of a 5-volume set, serves as a reference for the TMS320C54x DSP and provides information for developing hardware and software applications using the 54x. Unless otherwise specified, all references to the 54x apply to the TMS320C54x, the TMS320LC54x, and the TMS320VC54x. Many device references are shown with an apostrophe ( ) replacing the usual alphanumeric prefix (ex. 549 instead of TMS320C549). You should consult the device-specific datasheet if you need more information about the devices nomenclature. This users guide contains limited information about the enhanced peripherals available on the 5402, 5410, and 5420 devices. For detailed information on the enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302. For a summary of updates in this book, see Appendix D, Summary of Updates in This Document.

How to Use This Manual

The table below summarizes the 54x information contained in this book. (For a complete listing, refer to the Table of Contents.)
If you are looking for information about: Addressing modes Turn to these chapters: Chapter 5, Data Addressing Chapter 6, Program Memory Addressing Buffered serial port Bus structure Clock generator Chapter 9, Serial Ports Chapter 2, Architectural Overview Chapter 2, Architectural Overview Chapter 8, On-Chip Peripherals

Read This First

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How to Use This Manual

If you are looking for information about: CPU architecture

Turn to these chapters: Chapter 2, Architectural Overview Chapter 4, Central Processing Unit

External bus Hold mode Host port interface Interrupts Memory

Chapter 10, External Bus Operation Chapter 10, External Bus Operation Chapter 8, On-Chip Peripherals Chapter 6, Program Memory Addressing Chapter 2, Architectural Overview Chapter 3, Memory

On-chip peripherals Overview of the 54x Parallel I/O Ports

Chapter 8, On-Chip Peripherals Chapter 1, Introduction Chapter 2, Architectural Overview Chapter 8, On-Chip Peripherals

Power-down modes Program control Pipeline latencies Reset ROM code submission to TI Serial ports Status registers TDM serial port Timer

Chapter 6, Program Memory Addressing Chapter 6, Program Memory Addressing Chapter 7, Pipeline Chapter 6, Program Memory Addressing Appendix C, Submitting ROM Codes to TI Chapter 9, Serial Ports Chapter 4, Central Processing Unit Chapter 9, Serial Ports Chapter 2, Architectural Overview Chapter 8, On-Chip Peripherals

Wait-state generator

Chapter 2, Architectural Overview Chapter 8, On-Chip Peripherals

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Notational Conventions Notational Conventions / Information About Cautions

Notational Conventions
This book uses the following conventions.

The TMS320C54x DSP can use either of two forms of the instruction set: a mnemonic form or an algebraic form. This book uses the mnemonic form of the instruction set. For information about the mnemonic form of the instruction set, see TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set. For information about the algebraic form of the instruction set, see TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set. Program listings and program examples are shown in a special typeface. Here is a segment of a program listing:
STL RSBX B A,*AR1+ INTM MAIN_PG ;Int_RAM(I)=0 ;Globally enable interrupts ;Return to foreground program

Square brackets, [ and ], identify an optional parameter. If you use an optional parameter, specify the information within the brackets; do not type the brackets themselves.

Information About Cautions

This book contains cautions.

This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.

The information in a caution is provided for your protection. Please read each caution carefully.

Read This First Read This First

Related Documentation from Texas Instruments

Related Documentation from Texas Instruments

The following books describe the 54x and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924. When ordering, please identify the book by its title and literature number. Many of these documents are located on the internet at http://www.ti.com. Click DSPS Solutions, then click DSP Literature.

TMS320C54x DSP Reference Set is composed of five volumes that can be ordered as a set with literature number SPRU210. To order an individual book, use the document-specific literature number: TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) describes the TMS320C54x 16-bit fixed-point general-purpose digital signal processors. Covered are its architecture, internal register structure, data and program addressing, the instruction pipeline, and on-chip peripherals. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator. TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set (literature number SPRU172) describes the TMS320C54x digital signal processor mnemonic instructions individually. Also includes a summary of instruction set classes and cycles. TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set (literature number SPRU179) describes the TMS320C54x digital signal processor algebraic instructions individually. Also includes a summary of instruction set classes and cycles. TMS320C54x DSP Reference Set, Volume 4: Applications Guide (literature number SPRU173) describes software and hardware applications for the TMS320C54x digital signal processor. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator. TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) describes the enhanced peripherals available on the TMS320C54x digital signal processors. Includes the multichannel buffered serial ports (McBSPs), direct memory access (DMA) controller, the HPI-8 and HPI-16 host port interfaces, and the interprocessor communication module. TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors (literature number SPRS039) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages.
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Related Documentation from Texas Instruments

TMS320C54x DSKplus Users Guide (literature number SPRU191) describes the TMS320C54x digital signal processor starter kit (DSK), which allows you to execute custom C54x code in real time and debug it line by line. Covered are installation procedures, a description of the debugger and the assembler, customized applications, and initialization routines. TMS320C54x Assembly Language Tools Users Guide (literature number SPRU102) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the C54x generation of devices. TMS320C5xx C Source Debugger Users Guide (literature number SPRU099) tells you how to invoke the C54x emulator, evaluation module, and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality. TMS320C54x Code Generation Tools Getting Started Guide (literature number SPRU147) describes how to install the TMS320C54x assembly language tools and the C compiler for the C54x devices. The installation for MS-DOS, OS/2, SunOS, Solaris, and HP-UX 9.0x systems is covered. TMS320C54x Evaluation Module Technical Reference (literature number SPRU135) describes the C54x evaluation module, its features, design details and external interfaces. TMS320C54x Optimizing C Compiler Users Guide (literature number SPRU103) describes the C54x C compiler. This C compiler accepts ANSI standard C source code and produces TMS320 assembly language source code for the C54x generation of devices. TMS320C54x Simulator Getting Started (literature number SPRU137) describes how to install the TMS320C54x simulator and the C source debugger for the C54x. The installation for MS-DOS, PC-DOS, SunOS, Solaris, and HP-UX systems is covered. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 digital signal processors. A myriad of products and applications are offeredsoftware and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.
Read This First
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Technical Articles Related Documentation from Texas Instruments / Technical Articles

TMS320C548/C549 Bootloader Technical Reference (literature number SPRU288) describes the process the bootloader uses to transfer user code from an external source to the program memory at power up. (Presently available only on the internet.) TMS320 DSP Development Support Reference Guide (literature number SPRU011) describes the TMS320 family of digital signal processors and the tools that support these devices. Included are code-generation tools (compilers, assemblers, linkers, etc.) and system integration and debug tools (simulators, emulators, evaluation modules, etc.). Also covered are available documentation, seminars, the university program, and factory repair and exchange.

Technical Articles
A wide variety of related documentation is available on digital signal processing. These references fall into one of the following application categories:

General-Purpose DSP Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support

In the following list, references appear in alphabetical order according to author. The documents contain beneficial information regarding designs, operations, and applications for signal-processing systems; all of the documents provide additional references. Texas Instruments strongly suggests that you refer to these publications.

General-Purpose DSP:
1) Chassaing, R., Horning, D.W., Digital Signal Processing with Fixed and Floating-Point Processors , CoED, USA, Volume 1, Number 1, pages 1-4, March 1991. 2) Defatta, David J., Joseph G. Lucas, and William S. Hodgkiss, Digital Signal Processing: A System Design Approach, New York: John Wiley, 1988.
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Technical Articles

3) Erskine, C., and S. Magar, Architecture and Applications of a SecondGeneration Digital Signal Processor, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, USA, 1985. 4) Essig, D., C. Erskine, E. Caudel, and S. Magar, A Second-Generation Digital Signal Processor, IEEE Journal of Solid-State Circuits, USA, Volume SC-21, Number 1, pages 86-91, February 1986. 5) Frantz, G., K. Lin, J. Reimer, and J. Bradley, The Texas Instruments TMS320C25 Digital Signal Microcomputer, IEEE Microelectronics, USA, Volume 6, Number 6, pages 10-28, December 1986. 6) Gass, W., R. Tarrant, T. Richard, B. Pawate, M. Gammel, P. Rajasekaran, R. Wiggins, and C. Covington, Multiple Digital Signal Processor Environment for Intelligent Signal Processing, Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1246-1259, September 1987. 7) Jackson, Leland B., Digital Filters and Signal Processing, Hingham, MA: Kluwer Academic Publishers, 1986. 8) Jones, D.L., and T.W. Parks, A Digital Signal Processing Laboratory Using the TMS32010, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 9) Lim, Jae, and Alan V. Oppenheim, Advanced Topics in Signal Processing, Englewood Cliffs, NJ: Prentice- Hall, Inc., 1988. 10) Lin, K., G. Frantz, and R. Simar, Jr., The TMS320 Family of Digital Signal Processors, Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1143-1159, September 1987. 11) Lovrich, A., Reimer, J., An Advanced Audio Signal Processor , Digest of Technical Papers for 1991 International Conference on Consumer Electronics, June 1991. 12) Magar, S., D. Essig, E. Caudel, S. Marshall and R. Peters, An NMOS Digital Signal Processor with Multiprocessing Capability, Digest of IEEE International Solid-State Circuits Conference, USA, February 1985. 13) Oppenheim, Alan V., and R.W. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 and 1988. 14) Papamichalis, P.E., and C.S. Burrus, Conversion of Digit-Reversed to BitReversed Order in FFT Algorithms, Proceedings of ICASSP 89, USA, pages 984-987, May 1989. 15) Papamichalis, P., and R. Simar, Jr., The TMS320C30 Floating-Point Digital Signal Processor, IEEE Micro Magazine, USA, pages 13-29, December 1988.
Read This First
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Technical Articles

16) Papamichalis, P.E., FFT Implementation on the TMS320C30, Proceedings of ICASSP 88, USA, Volume D, page 1399, April 1988. 17) Parks, T.W., and C.S. Burrus, Digital Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. 18) Peterson, C., Zervakis, M., Shehadeh, N., Adaptive Filter Design and Implementation Using the TMS320C25 Microprocessor , Computers in Education Journal, USA, Volume 3, Number 3, pages 12-16, July-September 1993. 19) Prado, J., and R. Alcantara, A Fast Square-Rooting Algorithm Using a Digital Signal Processor, Proceedings of IEEE, USA, Volume 75, Number 2, pages 262-264, February 1987. 20) Rabiner, L.R. and B. Gold, Theory and Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975. 21) Simar, Jr., R., and A. Davis, The Application of High-Level Languages to Single-Chip Digital Signal Processors, Proceedings of ICASSP 88, USA, Volume D, page 1678, April 1988. 22) Simar, Jr., R., T. Leigh, P. Koeppen, J. Leach, J. Potts, and D. Blalock, A 40 MFLOPS Digital Signal Processor: the First Supercomputer on a Chip, Proceedings of ICASSP 87, USA, Catalog Number 87CH2396-0, Volume 1, pages 535-538, April 1987. 23) Simar, Jr., R., and J. Reimer, The TMS320C25: a 100 ns CMOS VLSI Digital Signal Processor, 1986 Workshop on Applications of Signal Processing to Audio and Acoustics, September 1986. 24) Texas Instruments, Digital Signal Processing Applications with the TMS320 Family, 1986; Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 25) Treichler, J.R., C.R. Johnson, Jr., and M.G. Larimore, A Practical Guide to Adaptive Filter Design, New York, NY: John Wiley and Sons, Inc., 1987.

Graphics/Imagery:
1) Reimer, J., and A. Lovrich, Graphics with the TMS32020, WESCON/85 Conference Record, USA, 1985.

Speech/Voice:
1) DellaMorte, J., and P. Papamichalis, Full-Duplex Real-Time Implementation of the FED-STD-1015 LPC-10e Standard V.52 on the TMS320C25, Proceedings of SPEECH TECH 89, pages 218-221, May 1989.
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Technical Articles

2) Gray, A.H., and J.D. Markel, Linear Prediction of Speech, New York, NY: Springer-Verlag, 1976. 3) Frantz, G.A., and K.S. Lin, A Low-Cost Speech System Using the TMS320C17, Proceedings of SPEECH TECH 87, pages 25-29, April 1987. 4) Papamichalis, P., and D. Lively, Implementation of the DOD Standard LPC-10/52E on the TMS320C25, Proceedings of SPEECH TECH 87, pages 201-204, April 1987. 5) Papamichalis, Panos, Practical Approaches to Speech Coding, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 6) Pawate, B.I., and G.R. Doddington, Implementation of a Hidden Markov Model-Based Layered Grammar Recognizer, Proceedings of ICASSP 89, USA, pages 801- 804, May 1989. 7) Rabiner, L.R., and R.W. Schafer, Digital Processing of Speech Signals, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 8) Reimer, J.B. and K.S. Lin, TMS320 Digital Signal Processors in Speech Applications, Proceedings of SPEECH TECH 88, April 1988. 9) Reimer, J.B., M.L. McMahan, and W.W. Anderson, Speech Recognition for a Low-Cost System Using a DSP, Digest of Technical Papers for 1987 International Conference on Consumer Electronics, June 1987.

Control:
1) Ahmed, I., 16-Bit DSP Microcontroller Fits Motion Control System Application, PCIM, October 1988. 2) Ahmed, I., Implementation of Self Tuning Regulators with TMS320 Family of Digital Signal Processors, MOTORCON 88, pages 248-262, September 1988. 3) Allen, C. and P. Pillay, TMS320 Design for Vector and Current Control of AC Motor Drives , Electronics Letters, UK, Volume 28, Number 23, pages 2188-2190, November 1992. 4) Panahi, I. and R. Restle, DSPs Redefine Motion Control , Motion Control Magazine, December 1993. 5) Lovrich, A., G. Troullinos, and R. Chirayil, An All-Digital Automatic Gain Control, Proceedings of ICASSP 88, USA, Volume D, page 1734, April 1988.
Read This First Read This First
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Technical Articles

6) Ahmed, I., and S. Meshkat, Using DSPs in Control, Control Engineering, February 1988. 7) Meshkat, S., and I. Ahmed, Using DSPs in AC Induction Motor Drives, Control Engineering, February 1988. 8) Matsui, N. and M. Shigyo, Brushless DC Motor Control Without Position and Speed Sensors , IEEE Transactions on Industry Applications, USA, Volume 28, Number 1, Part 1, pages 120-127, January-February 1992. 9) Hanselman, H., LQG-Control of a Highly Resonant Disc Drive Head Positioning Actuator, IEEE Transactions on Industrial Electronics, USA, Volume 35, Number 1, pages 100-104, February 1988. 10) Bose, B.K., and P.M. Szczesny, A Microcomputer-Based Control and Simulation of an Advanced IPM Synchronous Machine Drive System for Electric Vehicle Propulsion, Proceedings of IECON 87, Volume 1, pages 454-463, November 1987. 11) Ahmed, I., and S. Lindquist, Digital Signal Processors: Simplifying HighPerformance Control, Machine Design, September 1987.

Multimedia:
1) Reimer, J., DSP-Based Multimedia Solutions Lead Way Enhancing Audio Compression Performance , Dr. Dobbs Journal, December 1993. 2) Reimer, J., G. Benbassat, and W. Bonneau Jr., Application Processors: Making PC Multimedia Happen , Silicon Valley PC Design Conference, July 1991.

Military:
1) Papamichalis, P., and J. Reimer, Implementation of the Data Encryption Standard Using the TMS32010, Digital Signal Processing Applications, 1986.

Telecommunications:
1) Ahmed, I., and A. Lovrich, Adaptive Line Enhancer Using the TMS320C25, Conference Records of Northcon/86, USA, 14/3/1-10, September/October 1986. 2) Casale, S., R. Russo, and G. Bellina, Optimal Architectural Solution Using DSP Processors for the Implementation of an ADPCM Transcoder, Proceedings of GLOBECOM 89, pages 1267-1273, November 1989. 3) Cole, C., A. Haoui, and P. Winship, A High-Performance Digital Voice Echo Canceller on a SINGLE TMS32020, Proceedings of ICASSP 86,
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Technical Articles

USA, Catalog Number 86CH2243-4, Volume 1, pages 429-432, April 1986. 4) Cole, C., A. Haoui, and P. Winship, A High-Performance Digital Voice Echo Canceller on a Single TMS32020, Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, USA, 1986. 5) Lovrich, A., and J. Reimer, A Multi-Rate Transcoder, Transactions on Consumer Electronics, USA, November 1989. 6) Lovrich, A. and J. Reimer, A Multi-Rate Transcoder , Digest of Technical Papers for 1989 International Conference on Consumer Electronics, June 7-9, 1989. 7) Lu, H., D. Hedberg, and B. Fraenkel, Implementation of High-Speed Voiceband Data Modems Using the TMS320C25, Proceedings of ICASSP 87, USA, Catalog Number 87CH2396-0, Volume 4, pages 1915-1918, April 1987. 8) Mock, P., Add DTMF Generation and Decoding to DSP- P Designs, Electronic Design, USA, Volume 30, Number 6, pages 205-213, March 1985. 9) Reimer, J., M. McMahan, and M. Arjmand, ADPCM on a TMS320 DSP Chip, Proceedings of SPEECH TECH 85, pages 246-249, April 1985. 10) Troullinos, G., and J. Bradley, Split-Band Modem Implementation Using the TMS32010 Digital Signal Processor, Conference Records of Electro/86 and Mini/Micro Northeast, USA, 14/1/1-21, May 1986.

Automotive:
1) Lin, K., Trends of Digital Signal Processing in Automotive, International Congress on Transportation Electronic (CONVERGENCE 88), October 1988.

Consumer:
1) Frantz, G.A., J.B. Reimer, and R.A. Wotiz, Julie, The Application of DSP to a Product, Speech Tech Magazine, USA, September 1988. 2) Reimer, J.B., and G.A. Frantz, Customization of a DSP Integrated Circuit for a Customer Product, Transactions on Consumer Electronics, USA, August 1988. 3) Reimer, J.B., P.E. Nixon, E.B. Boles, and G.A. Frantz, Audio Customization of a DSP IC, Digest of Technical Papers for 1988 International Conference on Consumer Electronics, June 8-10 1988.
Read This First
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Trademarks Technical Articles / Trademarks

Medical:
1) Knapp and Townshend, A Real-Time Digital Signal Processing System for an Auditory Prosthesis, Proceedings of ICASSP 88, USA, Volume A, page 2493, April 1988. 2) Morris, L.R., and P.B. Barszczewski, Design and Evolution of a PocketSized DSP Speech Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications, Proceedings of ICASSP 88, USA, Volume A, page 2516, April 1988.

Development Support:
1) Mersereau, R., R. Schafer, T. Barnwell, and D. Smith, A Digital Filter Design Package for PCs and TMS320, MIDCON/84 Electronic Show and Convention, USA, 1984. 2) Simar, Jr., R., and A. Davis, The Application of High-Level Languages to Single-Chip Digital Signal Processors, Proceedings of ICASSP 88, USA, Volume 3, pages 1678-1681, April 1988.

Trademarks
HP-UX is a trademark of Hewlett-Packard Company. MS-DOS is a registered trademark of Microsoft Corporation. OS/2 and PC-DOS are trademarks of International Business Machines Corporation. PAL is a registered trademark of Advanced Micro Devices, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SPARC is a trademark of SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc. Windows is a registered trademark of Microsoft Corporation. 320 Hotline On-line, TI, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Micro Star is a trademark of Texas Instruments Incorporated.

xiv

If You Need Assistance

If You Need Assistance . . .

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Documentation
When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Email: dsph@ti.com Technical Documentation Services, MS 702 P.O. Box 1443 Houston, Texas 77251-1443

Note:

When calling a Literature Response Center to order documentation, please specify the literature number of the book.

Read This First

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Contents

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C54x DSP and lists its key features. 1.1 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 History, Development, and Advantages of TMS320 DSPs . . . . . . . . . . . . . . . . . 1.1.2 Typical Applications for the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C54x Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C54x Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 2 2 3 5 6

1.2 1.3 2

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Summarizes the TMS320C54x architecture. Provides general information about the CPU, bus structures, internal memory organization, on-chip peripherals, and scanning logic. 2.1 2.2 Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Internal Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 2.2.1 On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 2.2.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.2.3 On-Chip Single-Access RAM (SARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.2.4 On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.2.5 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2.3.1 Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2.3.2 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2.3.3 Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.3.4 Multiplier/Adder Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2.3.5 Compare, Select, and Store Unit (CSSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 Program Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 11 2.7.1 General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 11 2.7.2 Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2 11 2.7.3 Programmable Bank-Switching Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 2.7.4 Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 2.7.5 Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 2.7.6 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13
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2.4 2.5 2.6 2.7

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2.8

2.9 2.10 3

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 Synchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Buffered Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.3 Multichannel Buffered Serial Ports (McBSPs) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.4 TDM Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Standard 1149.1 Scanning Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 2 2 2 2 2 2

14 14 14 15 15 16 16

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Describes the TMS320C54x memory configuration and operation. Includes memory maps and descriptions of program memory, data memory, and I/O space. Also includes descriptions of the CPU memory-mapped registers. 3.1 3.2 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 15 3.2.1 Program Memory Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 16 3.2.2 On-Chip ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17 3.2.3 Program Memory Address Map and On-Chip ROM Contents . . . . . . . . . . . . . 3 18 3.2.4 On-Chip ROM Code Contents and Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 18 3.2.5 Extended Program Memory (Available on 548/549/5402/5410/5420) . . . . . 3 20 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 22 3.3.1 Data Memory Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 22 3.3.2 On-Chip RAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 23 3.3.3 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 25 3.3.4 CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 26 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 30 Program and Data Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 30

3.3

3.4 3.5 4

Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 Describes the TMS320C54x CPU operations. Includes information about the arithmetic logic unit, the accumulators, the shifter, the multiplier/adder unit, the compare, select, store unit, and the exponent encoder. 4.1 CPU Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 4.1.1 Status Registers (ST0 and ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 4.1.2 Processor Mode Status Register (PMST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 4.2.1 ALU Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 4.2.2 Overflow Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 13 4.2.3 The Carry Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 13 4.2.4 Dual 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 14 Accumulators A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 15 4.3.1 Storing Accumulator Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 15 4.3.2 Accumulator Shift and Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16 4.3.3 Saturation Upon Accumulator Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 17 4.3.4 Application-Specific Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 17

4.2

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4.4 4.5

4.6 4.7 5

Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplier/Adder Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Multiplier Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Multiply/Accumulate (MAC) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 MAC and MAS Saturation Upon Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . Compare, Select, and Store Unit (CSSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exponent Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 4 4 4 4 4 4

19 21 22 24 25 26 29

Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 Describes the seven basic addressing modes of the TMS320C54x. 5.1 5.2 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5.2.1 dmad Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5.2.2 pmad Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5.2.3 PA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5.2.4 *(lk) Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Accumulator Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 5.4.1 DP-Referenced Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 5.4.2 SP-Referenced Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 5.5.1 Single-Operand Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 5.5.2 ARAU and Address-Generation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 5.5.3 Single-Operand Address Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 13 5.5.4 Dual-Operand Address Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 19 5.5.5 TMS320C2x/C20x/C24x/C5x Compatibility (ARP) Mode . . . . . . . . . . . . . . . . . 5 23 Memory-Mapped Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25 Stack Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 27 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28

5.3 5.4

5.5

5.6 5.7 5.8 6

Program Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 Describes the TMS320C54x program control mechanisms. Includes information about address generation, the program counter, the hardware stack, reset, interrupts, and power-down modes. 6.1 6.2 6.3 Program-Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6.3.1 Unconditional Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6.3.2 Conditional Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 6.3.3 Far Branches (Available on 548/549/5402/5410/5420) . . . . . . . . . . . . . . . . . 6 8 Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 6.4.1 Unconditional Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 6.4.2 Conditional Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 6.4.3 Far Calls (Available on 548 /549/5402/5410/5420) . . . . . . . . . . . . . . . . . . . . 6 11
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6.5

6.6

6.7 6.8 6.9 6.10

6.11

Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Unconditional Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Conditional Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Far Returns (Available on 548/549/5402/5410/5420) . . . . . . . . . . . . . . . . . . Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Using Multiple Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Conditional Execute (XC) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 Conditional Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Repeating a Single Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Repeating a Block of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Interrupt Flag Register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.3 Phase 1: Receive Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.4 Phase 2: Acknowledge Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.5 Phase 3: Execute Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . . . . . . . . 6.10.6 Interrupt Context Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.7 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.8 Interrupt Operation: A Quick Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.9 Re-mapping Interrupt-Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.10 Interrupt Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 IDLE1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 IDLE2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.3 IDLE3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.4 Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.5 Other Power-Down Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

12 12 13 14 16 17 17 18 20 23 25 26 27 29 31 32 33 34 34 35 36 38 50 50 51 51 52 52

Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 Describes the TMS320C54x pipeline operation and lists the pipeline latency cycles for these types of latencies. 7.1 Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 7.1.1 Branch Instructions in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 7.1.2 Call Instructions in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 7.1.3 Return Instructions in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 7.1.4 Conditional Execute Instructions in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . 7 19 7.1.5 Conditional-Call and Conditional-Branch Instructions in the Pipeline . . . . . . . 7 20 Interrupts and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 25 Dual-Access Memory and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 27 7.3.1 Resolved Conflict Between Instruction Fetch and Operand Read . . . . . . . . . 7 29 7.3.2 Resolved Conflict Between Operand Write and Dual-Operand Read . . . . . . 7 30 7.3.3 Resolved Conflict Among Operand Write, Operand Write, and Dual-Operand Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 31

7.2 7.3

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7.4 7.5

Single-Access Memory and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Recommended Instructions for Accessing Memory-Mapped Registers . . . . . 7.5.2 Updating ARx, BK, or SPA Resolved Conflict . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 Rules to Determine DAGEN Register Access Conflicts . . . . . . . . . . . . . . . . . . 7.5.4 Latencies for ARx and BK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.5 Latencies for the Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.6 Latencies for Temporary Register (T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.7 Latencies for Accessing Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.8 Latencies in Repeat-Block Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.9 Latencies for the PMST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.10 Latencies for Memory-Mapped Accesses to Accumulators . . . . . . . . . . . . . . .

7 7 7 7 7 7 7 7 7 7 7 7

33 35 35 38 44 44 50 57 60 72 75 79

On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 Describes the TMS320C54x peripherals and how to control them. Includes information about the general-purpose I/O pins, timers, clock, and host port interface. 8.1 Available On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 8.2 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 8.3 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 8.3.1 Branch Control Input Pin (BIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 8.3.2 External Flag Output Pin (XF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 8.4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 21 8.4.1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 21 8.4.2 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 23 8.5 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 26 8.5.1 Hardware-Configurable PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 26 8.5.2 Software-Programmable PLL (541B/545A/546A/548/549/5402/5410/5420) . . . . . . . . . . . . . . . . . . . . . . . 8 27 Programming Considerations When Using the Software-Programmable PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 31 Using the PLLCOUNT Programmable Lock Timer . . . . . . . . . . . . . . . . . . . . . . 8 31 Switching Clock Mode From DIV Mode to PLL Mode . . . . . . . . . . . . . . . . . . . . 8 32 Switching Clock Mode From PLL Mode to DIV Mode . . . . . . . . . . . . . . . . . . . . 8 33 Changing the PLL Multiplier Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 34 PLL Operation Immediately Following Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 35 PLL Considerations When Using IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . 8 35 PLL Considerations When Using the Bootloader . . . . . . . . . . . . . . . . . . . . . . . . 8 36 8.6 Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 37 8.6.1 Basic Host Port Interface Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 8 38 8.6.2 Details of Host Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 41 HPI Control Register Bits and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 44 8.6.3 Host Read/Write Access to HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 46 Access Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 49 8.6.4 DSPINT and HINT Function Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 51 Host Device Using DSPINT to Interrupt the 54x . . . . . . . . . . . . . . . . . . . . . . . . 8 51 Host Port Interface (54x) Using HINT to Interrupt the Host Device . . . . . . . . 8 52 8.6.5 Considerations in Changing HPI Memory Access Mode (SAM/HOM) and IDLE2/3 Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 52 8.6.6 Access of HPI Memory During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 54
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Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1

Describes the TMS320C54x serial ports. Includes information about the standard serial port interface, buffered serial port interface, multichannel buffered serial port interface, and time-division multiplexed serial port interface.
9.1 9.2 Introduction to the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 9.2.1 Serial Port Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 9.2.2 Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 9.2.3 Configuring the Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Reserved Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 DLB Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 FO Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 FSM Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 MCM Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 TXM Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 XRST and RRST Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 IN0 and IN1 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 15 RRDY and XRDY Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 15 XSREMPTY Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 16 RSRFULL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 16 SOFT and FREE Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 17 9.2.4 Burst Mode Transmit and Receive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 9 18 9.2.5 Continuous Mode Transmit and Receive Operations . . . . . . . . . . . . . . . . . . . . 9 24 9.2.6 Serial Port Interface Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 26 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 27 Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 29 9.2.7 Example of Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 31 Buffered Serial Port (BSP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 33 9.3.1 BSP Operation in Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 35 9.3.2 Autobuffering Unit (ABU) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 40 9.3.3 System Considerations for BSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 49 9.3.4 Buffer Misalignment Interrupt (BMINT) 549 only . . . . . . . . . . . . . . . . . . . . . . 9 54 9.3.5 BSP Operation in Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 55 Time-Division Multiplexed (TDM) Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 9 56 9.4.1 Basic Time-Division Multiplexed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 56 9.4.2 TDM Serial Port Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 56 9.4.3 TDM Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 58 9.4.4 TDM Mode Transmit and Receive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 9 62 9.4.5 TDM Serial Port Interface Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . 9 64 9.4.6 Examples of TDM Serial Port Interface Operation . . . . . . . . . . . . . . . . . . . . . . . 9 64

9.3

9.4

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10 External Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 Discusses the external bus interface and the timing of events involved in memory and I/O accesses. Describes the hold mode and the wake-up sequence from IDLE3 mode. 10.1 10.2 10.3 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 External Bus Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 10.3.1 Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 10.3.2 Bank-Switching Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 External Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 14 10.4.1 Memory Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 14 10.4.2 I/O Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 18 10.4.3 Memory and I/O Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 19 Start-Up Access Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 24 10.5.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 24 10.5.2 IDLE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 26 Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 28 10.6.1 Interrupts During Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 29 10.6.2 Hold and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 29

10.4

10.5

10.6

Design Considerations for Using XDS510 Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 1 Describes the JTAG emulator cable, how to construct a 14-pin connector on your target system, and how to connect the target system to the emulator. A.1 A.2 A.3 A.4 A.5 A.6 Designing Your Target Systems Emulator Connector (14-Pin Header) . . . . . . . . . . . . . A 2 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 4 Emulator Cable Pod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 5 Emulator Cable Pod Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 6 Emulation Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 7 Connections Between the Emulator and the Target System . . . . . . . . . . . . . . . . . . . . . A 10 A.6.1 Buffering Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 10 A.6.2 Using a Target-System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 12 A.6.3 Configuring Multiple Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 13 Physical Dimensions for the 14-Pin Emulator Connector . . . . . . . . . . . . . . . . . . . . . . . . A 14 Emulation Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 16 A.8.1 Using Scan Path Linkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 16 A.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL) . . . . . . . . . . . . . A 18 A.8.3 Using Emulation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 20 A.8.4 Performing Diagnostic Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 24

A.7 A.8

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Development Support and Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 1 Provides device part numbers and support tool ordering information for the TMS320C54x and development support information available from TI and third-party vendors. B.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.1 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Generation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Integration and Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.2 Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.3 Technical Training Organization (TTO) TMS320 Workshops . . . . . . . . . . . . . . . B.1.4 Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.1 Device and Development Support Tool Nomenclature Prefixes . . . . . . . . . . . . B.2.2 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.3 Development Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B B B B B B B B B B B 2 2 2 2 3 4 4 5 5 6 8

B.2

Submitting ROM Codes to TI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 1 Provides information for submitting ROM codes to Texas Instruments. Summary of Updates in This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D 1 Provides a summary of the updates in this version of the document. Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E 1 Defines terms and abbreviations used throughout this book.

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Figures
11 21 31 32 33 34 35 36 37 38 39 310 311 312 313 314 315 316 317 318 319 41 42 43 44 45 46 47 48 49 410 411 Evolution of the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Block Diagram of TMS320C54x Internal Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Memory Maps for the 541 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Memory Maps for the 542 and 543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Memory Maps for the 545 and 546 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Memory Maps for the 548 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Memory Maps for the 549 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Extended Program Memory Maps for the 548 and 549 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Memory Maps for the 5402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 Extended Program Memory for the 5402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 10 Memory Maps for the 5410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 11 Extended Program Memory Maps for the 5410 (Onchip RAM Not Mapped in Program Space and Data Space, OVLY = 0) . . . . . . . . . 3 12 Extended Program Memory Maps for the 5410 (Onchip RAM Mapped in Program Space and Data Space, OVLY = 1) . . . . . . . . . . . . . 3 12 Data Memory Map for the 5420 Relative to CPU Subsystems A and B . . . . . . . . . . . . . . 3 13 Program Memory Maps for the 5420 Relative to CPU Subsystems A and B . . . . . . . . . 3 14 On-Chip ROM Block Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17 On-Chip ROM Program Memory Map (High Addresses) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 19 Extended Program Memory With On-Chip RAM Not Mapped in Program Space (OVLY = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 20 Extended Program Memory With On-Chip RAM Mapped in Program Space and Data Space (OVLY = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 21 On-Chip RAM Block Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 24 On-Chip RAM Block Organization (5402/5410/5420) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 25 Status Register 0 (ST0) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Status Register 1 (ST1) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Processor Mode Status Register (PMST) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 ALU Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11 Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 15 Accumulator B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 15 Barrel Shifter Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20 Multiplier/Adder Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 22 Compare, Select, and Store Unit (CSSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 26 Viterbi Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 27 Exponent Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 29
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51 52 53 54 55 56 57 58 59 510 511 512 513 514 515 516 517 61 62 63 64 65 71 72 73 81 82 83 84 85 86 87 88 89 810 811 812 813 91 92 93 94 95 96
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RPT Instruction With Short-Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 RPT Instruction With 16-Bit-Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Direct-Addressing Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Direct Addressing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 DP-Referenced Direct Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 SP-Referenced Direct Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Indirect-Addressing Instruction Format for a Single Data-Memory Operand . . . . . . . . . . 5 10 Indirect Addressing Block Diagram for a Single Data-Memory Operand . . . . . . . . . . . . . 5 12 Circular Addressing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 17 Circular Buffer Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 17 Indirect-Addressing Instruction Format for Dual Data-Memory Operands . . . . . . . . . . . . 5 20 Indirect Addressing Block Diagram for Dual Data-Memory Operands . . . . . . . . . . . . . . . 5 21 How ARP Indexes the Auxiliary Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 23 Indirect-Addressing Instruction Format for Compatibility Mode . . . . . . . . . . . . . . . . . . . . . 5 24 Memory-Mapped Register Addressing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25 Stack and Stack Pointer Before and After a Push Operation . . . . . . . . . . . . . . . . . . . . . . . 5 27 Word Order in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 29 Program-Address Generation Logic (PAGEN) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Interrupt Flag Register (IFR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 28 Interrupt Mask Register (IMR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 29 Interrupt-Vector Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 36 Flow Diagram of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 37 Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pipelined Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Half-Cycle Accesses to Dual-Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 28 External Flag Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 Timer Control Register (TCR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 22 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 23 Clock Mode Register (CLKMD) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 29 PLL Lockup Time Versus CLKOUT Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 32 Host Port Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 37 Generic System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 39 Select Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 43 HPIC Diagram Host Reads from HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 45 HPIC Diagram Host Writes to HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 46 HPIC Diagram TMS320C54x Reads From HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 46 HPIC Diagram TMS320C54x Writes to HPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 46 HPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 48 One-Way Serial Port Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Serial Port Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Serial Port Control Register (SPC) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Receiver Signal Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Burst Mode Serial Port Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 18 Serial Port Transmit With Long FSX Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 19

Figures

97 98 99 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 101 102 103 104 105 106 107 108 109 1010 1011 1012 1013

Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 20 Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (BSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 21 Burst Mode Serial Port Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 21 Burst Mode Serial Port Receive Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 22 Serial Port Receive With Long FSR Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 23 Burst Mode Serial Port Transmit at Maximum Packet Frequency . . . . . . . . . . . . . . . . . . . 9 23 Burst Mode Serial Port Receive at Maximum Packet Frequency . . . . . . . . . . . . . . . . . . . . 9 24 Continuous Mode Serial Port Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 25 Continuous Mode Serial Port Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 26 SP Receiver Functional Operation (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 27 BSP Receiver Functional Operation (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 28 SP/BSP Transmitter Functional Operation (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 29 SP/BSP Receiver Functional Operation (Continuous Mode) . . . . . . . . . . . . . . . . . . . . . . . 9 30 SP/BSP Transmitter Functional Operation (Continuous Mode) . . . . . . . . . . . . . . . . . . . . . 9 31 BSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 34 BSP Control Extension Register (BSPCE) Diagram Serial Port Control Bits . . . . . . . 9 37 Transmit Continuous Mode with External Frame and FIG = 1 (Format Is 16 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 40 ABU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 42 BSP Control Extension Register (BSPCE) Diagram ABU Control Bits . . . . . . . . . . . . . 9 43 Circular Addressing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 47 Transmit Buffer and Receive Buffer Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 48 Standard Mode BSP Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 51 Autobuffering Mode Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 52 Time-Division Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 56 TDM 4-Wire Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 58 TDM Serial Port Registers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 60 Serial Port Timing (TDM Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 62 TDM Example Configuration Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 65 External Bus Interface Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Software Wait-State Register (SWWSR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Software Wait-State Control Register (SWCR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Software Wait-State Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Bank-Switching Control Register (BSCR) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 Bank Switching Between Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Bank Switching Between Program Space and Data Space . . . . . . . . . . . . . . . . . . . . . . . 10 13 Memory Interface Operation for Read-Read-Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 15 Memory Interface Operation for Write-Write-Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 16 Memory Interface Operation for Read-Read-Write (Program-Space Wait States) . . . . 10 17 Parallel I/O Interface Operation for ReadWriteRead . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 18 Parallel I/O Operation for Read-Write-Read (I/O-Space Wait States) . . . . . . . . . . . . . . . 10 19 Memory Read and I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 20
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Figures

1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 C1

Memory Read and I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 20 Memory Write and I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 21 Memory Write and I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 21 I/O Write and Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 22 I/O Write and Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 22 I/O Read and Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 23 I/O Read and Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 23 External Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 25 IDLE3 Wake-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 27 HOLD and HOLDA Minimum Timing for HM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 30 HOLD and RS Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 31 14-Pin Header Signals and Header Dimensions933 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 2 Emulator Cable Pod Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 5 Emulator Cable Pod Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 6 Emulator Connections Without Signal Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 10 Emulator Connections With Signal Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 11 Target-System-Generated Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 12 Multiprocessor Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 13 Pod/Connector Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 14 14-Pin Connector Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 15 Connecting a Secondary JTAG Scan Path to a Scan Path Linker . . . . . . . . . . . . . . . . . . . A 17 EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns . . . . . . . . . . . . A 21 Suggested Timings for the EMU0 and EMU1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 22 EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 23 EMU0/1 Configuration Without Global Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 24 TBC Emulation Connections for n JTAG Scan Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 25 TMS320 DSP Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 7 TMS320 ROM Code Submittal Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 2

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Tables
11 21 22 23 24 31 32 33 34 41 42 43 44 45 46 51 52 53 54 55 56 57 58 59 510 511 61 62 63 64 65 66 67 68 69 610 Typical Applications for the TMS320 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Bus Usage for Read and Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Program and Data Memory on the TMS320C54x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Host Port Interfaces on the TMS320C54x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 Serial Port Interfaces on the TMS320C54x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14 On-Chip Program Memory Available on 54x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 15 On-Chip Data Memory Available on the TMS320C54x Devices . . . . . . . . . . . . . . . . . . . . . 3 22 CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 26 Data Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 30 Status Register 0 (ST0) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Status Register 1 (ST1) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Processor Mode Status Register (PMST) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 ALU Input Selection for ADD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 12 Multiplier Input Selection for Several Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 23 ALU Operations in Dual 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 27 Instructions That Allow Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Direct-Addressing Instruction Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Indirect-Addressing Instruction Bit Summary Single Data-Memory Operand . . . . . . . 5 10 Indirect Addressing Types With a Single Data-Memory Operand . . . . . . . . . . . . . . . . . . . 5 13 Bit-Reversed Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 19 Indirect-Addressing Instruction Bit Summary Dual Data-Memory Operands . . . . . . . . 5 20 Auxiliary Registers Selected by Xar and Yar Field of Instruction . . . . . . . . . . . . . . . . . . . . 5 20 Indirect Addressing Types With Dual Data-Memory Operands . . . . . . . . . . . . . . . . . . . . . 5 21 Assembler Syntax Comparison for TMS320C2x/C20x/C24x/C5x and 54x . . . . . . . . . . . 5 23 Indirect-Addressing Instruction Bit Summary Compatibility Mode . . . . . . . . . . . . . . . . . 5 24 Instructions With 32-Bit Word Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28 Devices With Additional Program Memory Address Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Loading Addresses Into PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Loading Addresses into XPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Unconditional Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Conditional Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Far Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Unconditional Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 Conditional Call Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 Far Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 Unconditional Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13
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611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 71 72 73 74 75 76 77 78 79 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725
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Conditional Return Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Far Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditions for Conditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Grouping of Conditions for Multiconditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditional Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditions for Conditional Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multicycle Instructions That Become Single-Cycle Instructions When Repeated . . . . . . Nonrepeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5402 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5410 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5420 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation During the Four Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Instructions for Accessing Memory-Mapped Registers . . . . . . . . . . . . . . Instructions That Access DAGEN Registers in the Read Stage . . . . . . . . . . . . . . . . . . . . . Store-Type Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline-Protected Instructions for Updating ARx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for Accessing ARx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for Accessing BK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for SP in Compiler Mode (CPL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline-Protected Instructions to Update SP in Noncompiler Mode (CPL = 0) . . . . . . . . Latencies for SP in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline-Protected Instructions for Updating T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for the T Register Based on Second-Instruction Category . . . . . . . . . . . . . . . . Recommended Instructions for Writing to ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline-Protected Instruction to Update ARP in Compatibility Mode (CMPT = 1) . . . . . Latencies for ARP in Compatibility Mode (CMPT = 1) and CMPT bit . . . . . . . . . . . . . . . . Recommended Instructions to Update DP in Noncompiler Mode (CPL = 0) . . . . . . . . . . Latencies for DP in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for the CPL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for the SXM Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline-Protected Instructions for Writing to ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for ASM Bit Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Instructions for Writing to BRC Before an RPTB Loop . . . . . . . . . . . . . . . Latencies for Updating BRC Before an RPTB Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latencies for Updating BRC From Within an RPTB Loop . . . . . . . . . . . . . . . . . . . . . . . . . .

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7

14 15 16 17 18 19 20 21 38 39 40 41 42 43 44 45 46 48 50 27 28 36 38 39 45 46 47 51 54 55 57 58 60 61 62 63 64 66 68 69 70 72 72 74

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726 727 728 81 82 83 84 85 86 87 88 89 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 91 92 93 94 95 96 97 98 99 910 911

Latencies for OVLY, IPTR, and MP/MC Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 76 Latencies for the DROM Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 78 Latencies for Accumulators A and B When Used as Memory-Mapped Registers . . . . . . 7 81 541/541B Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 542 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 543 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 545/545A Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 546/546A Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 548 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 549 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 5402 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11 5410 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 5420 Peripheral Memory-Mapped Registers For Each DSP Subsystem . . . . . . . . . . . . . 8 15 5402/5410/5420 McBSP Sub-addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 17 5402/5410/5420 DMA Sub-addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 18 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 21 Timer Control Register (TCR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 22 Clock Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 27 Clock Mode Settings at Reset (541B/545A/546A/548/549/5410) . . . . . . . . . . . . . . . . . 8 28 Clock Mode Settings at Reset (5402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 28 Clock Mode Register (CLKMD) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 30 PLL Multiplier Ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL . . . . . . . . . . . . . . 8 31 HPI Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 40 HPI Signal Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 41 HPI Input Control Signals Function Selection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 8 43 HPI Control Register (HPIC) Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 44 HPIC Host/TMS320C54x Read/Write Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 46 Wait-State Generation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 49 Initialization of BOB and HPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 50 Read Access to HPI With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 50 Write Access to HPI With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 51 Sequence for Entering and Exiting IDLE2 and IDLE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 53 HPI Operation During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 54 Serial Ports on the TMS320C54x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Sections that Discuss the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Serial Port Control Register (SPC) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 Serial Port Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 17 Buffered Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 35 Differences Between Serial Port and BSP Operation in Standard Mode . . . . . . . . . . . . . 9 36 BSP Control Extension Register (BSPCE) Bit Summary Serial Port Control Bits . . . 9 38 Buffered Serial Port Word Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 39 Autobuffering Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 40
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912 913 914 915 101 102 103 104 105 106 107 108 A1 A2 B1

BSP Control Extension Register (BSPCE) Bit Summary ABU Control Bits . . . . . . . 9 44 TDM Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 57 Interprocessor Communications Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 65 TDM Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 66 Key External Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Software Wait-State Register (SWWSR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 548/549/5402/5410/5420 Software Wait-State Register (SWWSR) Bit Summary . . 10 7 Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States . . . . . . . . 10 8 Bank-Switching Control Register (BSCR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 Relationship Between BNKCMP and Bank Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 State of Signals When External Bus Interface is Disabled (EXIO = 1) . . . . . . . . . . . . . . 10 11 Counter Down-Time With PLL Multiplication Factors at 40 MHz Operation . . . . . . . . . . 10 26 14-Pin Header Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 3 Emulator Cable Pod Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 6 Development Support Tools Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 8

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Examples

Examples
41 42 43 44 45 51 71 72 73 74 75 76 77 78 79 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 Use of SMUL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 Use of SST Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10 Accumulator Store With Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16 CMPS Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 28 Normalization of Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 29 Sequence of Auxiliary Registers Modifications in Bit-Reversed Addressing . . . . . . . . . . 5 18 Sample Pipeline Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Branch Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Delayed-Branch Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Call Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 Delayed-Call Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 INTR Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 Return Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Delayed-Return Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Return-With-Interrupt-Enable Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 15 Delayed Return-With-Interrupt-Enable Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . 7 16 Return-Fast Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 17 Delayed Return-Fast Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 18 XC Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 19 CC Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 21 CCD Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 22 BC Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 23 BCD Instruction in the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 24 Interrupt Response by the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 26 Instruction Fetch and Operand Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 30 Operand Write and Dual-Operand Read Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 31 Operand Write and Operand Read Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 32 Resolving Conflict When Updating Multiple ARxs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 40 Resolving Conflict When Updating ARx and BK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 42 Resolving Conflict When Updating SP, BK, and ARx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 43 ARx Updated With No Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 48 ARx Updated With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 48 ARx Updated With and Without a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 49 ARx Updated With and Without a 2-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 49 ARx Updated With a 2-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 49 BK Updated With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 50
Contents
xxxiii

Examples

731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 81 82 83 91
xxxiv

SP Load With No Latency in Compiler Mode (CPL =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP Load With a 1-Cycle Latency in Compiler Mode (CPL = 1) . . . . . . . . . . . . . . . . . . . . . . SP Load With and Without a 2-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP Load With a 2-Cycle Latency in Compiler Mode (CPL = 1) . . . . . . . . . . . . . . . . . . . . . . SP Load With a 3-Cycle Latency in Compiler Mode (CPL = 1, DP = 0) . . . . . . . . . . . . . . SP Load With No Latency in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . . . . . . . SP Load With and Without a 1-Cycle Latency in Noncompiler Mode (CPL = 0) . . . . . . . SP Load With a 1-Cycle Latency in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . T Load With No Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Load With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARP Load With No Latency in Compatibility Mode (CMPT = 1) . . . . . . . . . . . . . . . . . . . . . ARP Load With a 2-Cycle Latency in Compatibility Mode (CMPT = 1) . . . . . . . . . . . . . . . ARP Load With a 3-Cycle Latency in Compatibility Mode (CMPT = 1) . . . . . . . . . . . . . . . DP Load With No Latency in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . . . . . . . DP Load With a 2-Cycle Latency in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . DP Load With a 3-Cycle Latency in Noncompiler Mode (CPL = 0) . . . . . . . . . . . . . . . . . . CPL Update With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPL Update With a 2-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPL Update With a 3-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SXM Update With No Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SXM Update With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASM Update With No Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASM Update With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading BRC Before Executing a New Repeat-Block Loop . . . . . . . . . . . . . . . . . . . . . . . . SRCCD Instruction With No Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRCCD Instruction With a 3-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modifying BRC From Within an RPTB Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRAF Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OVLY Setup Followed by an Unconditional Branch (DP = 0) . . . . . . . . . . . . . . . . . . . . . . . OVLY Setup Followed by a Conditional Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OVLY Setup Followed by a Return (DP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MP/MC Setup Followed by an Unconditional Delayed Call . . . . . . . . . . . . . . . . . . . . . . . . . IPTR Setup Followed by a Software Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DROM Setup Followed by a Read Access (DP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DROM Setup Followed by a Dual-Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator Access With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator Access With No Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Updating Accumulator With a 1-Cycle Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Updating Accumulator With No Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Clock Mode From PLL x 3 Mode to Divide-by-2 Mode . . . . . . . . . . . . . . . . . . . Switching Clock Mode From PLL x X Mode to PLL x 1 Mode . . . . . . . . . . . . . . . . . . . . . . . Switching Clock From PLL x 3 Mode to Divide-by-2 Mode, Turning Off the PLL, and Entering IDLE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8

52 52 53 53 53 56 56 56 59 59 63 63 63 65 65 65 67 67 67 68 68 71 71 73 73 74 74 75 76 76 77 77 77 78 78 79 80 81 82 34 35

8 36 9 32

Examples

92 93 94 95 96 97 98 A1 A2 A3 A4

Serial Port Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 32 BSP Transmit Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 53 BSP Receive Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 54 TDM Serial Port Transmit Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 67 TDM Serial Port Transmit Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 67 TDM Serial Port Receive Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 68 TDM Serial Port Receive Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 68 Key Timing for a Single-Processor System Without Buffers . . . . . . . . . . . . . . . . . . . . . . . . . A 8 Key Timing for a Single- or Multiple-Processor System With Buffered Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 8 Key Timing for a Single-Processor System Without Buffering (SPL) . . . . . . . . . . . . . . . . . A 19 Key Timing for a Single- or Multiprocessor-System With Buffered Input and Output (SPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 19

Contents

xxxv

Chapter 1

Introduction
The TMS320C54x devices are fixed-point digital signal processors (DSPs) in the TMS320 family. The 54x meets the specific needs of real-time embedded applications, such as telecommunications. The 54x central processing unit (CPU), with its modified Harvard architecture, features minimized power consumption and a high degree of parallelism. In addition to these features, the versatile addressing modes and instruction set in the 54x improve the overall system performance.

Topic
1.1 1.2 1.3

Page
TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 TMS320C54x Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 TMS320C54x Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1-1

TMS320 Family Overview

1.1 TMS320 Family Overview

The TMS320 family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). The TMS320 architecture is designed specifically for real-time signal processing. The following characteristics make this family the ideal choice for a wide range of processing applications:

1.1.1

Very flexible instruction set Inherent operational flexibility High-speed performance Innovative parallel architecture Cost-effectiveness C-friendly architecture

History, Development, and Advantages of TMS320 DSPs

In 1982, Texas Instruments introduced the TMS32010 the first fixed-point DSP in the TMS320 family. Before the end of the year, Electronic Products magazine awarded the TMS32010 the title Product of the Year. Today, the TMS320 family consists of these generations: C1x, C2x, C2xx, C5x, C54x, and C6x fixed-point DSPs; C3x and C4x floating-point DSPs; and C8x multiprocessor DSPs. Devices within a generation of the TMS320 family have the same CPU structure but different on-chip memory and peripheral configurations. Spinoff devices use new combinations of on-chip memory and peripherals to satisfy a wide range of needs in the worldwide electronics market. By integrating memory and peripherals onto a single chip, TMS320 devices reduce system costs and save circuit board space. Figure 11 illustrates the performance gains that the TMS320 family has made.

1-2

TMS320 Family Overview

Figure 11. Evolution of the TMS320 Family

C6000 (C62x, C67x) C5000 (C54x) C2000 (C20x, C24x) C1/2x C5x
Power-efficient performance

C8x C3x/4x
High performance

Control optimized

1.1.2

Typical Applications for the TMS320 Family

Table 11 lists some typical applications for the TMS320 family of DSPs. The TMS320 DSPs offer more adaptable approaches to traditional signal-processing problems such as vocoding and filtering than standard microprocessor/ microcomputer devices. They also support complex applications that often require multiple operations to be performed simultaneously.

Introduction

1-3

TMS320 Family Overview

Table 11. Typical Applications for the TMS320 DSPs

Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Navigation and global positioning Vibration analysis Voice commands Anticollision radar General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios/TVs Educational toys Music synthesizers Pagers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control

Graphics/Imaging 3-D rotation Animation/digital maps Homomorphic processing Image compression/transmission Image enhancement Pattern recognition Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications

Industrial Numeric control Power-line monitoring Robotics Security access

Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice/Speech Speaker verification Speech enhancement Speech recognition Speech synthesis Speech vocoding Text-to-speech Voice mail

1200- to 33 600-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) DTMF encoding/decoding Echo cancellation

Faxing Line repeaters Personal communications systems (PCS) Personal digital assistants (PDA) Speaker phones Spread spectrum communications Video conferencing X.25 packet switching

1-4

TMS320C54x Overview

1.2 TMS320C54x Overview

The 54x has a high degree of operational flexibility and speed. It combines an advanced modified Harvard architecture (with one program memory bus, three data memory buses, and four address buses), a CPU with applicationspecific hardware logic, on-chip memory, on-chip peripherals, and a highly specialized instruction set. Spinoff devices that combine the 54x CPU with customized on-chip memory and peripheral configurations have been, and continue to be, developed for specialized areas of the electronics market. The 54x devices offer these advantages:

Enhanced Harvard architecture built around one program bus, three data buses, and four address buses for increased performance and versatility Advanced CPU design with a high degree of parallelism and applicationspecific hardware logic for increased performance A highly specialized instruction set for faster algorithms and for optimized high-level language operation Modular architecture design for fast development of spinoff devices Advanced IC processing technology for increased performance and low power consumption Low power consumption and increased radiation hardness because of new static design techniques

Introduction

1-5

TMS320C54x Key Features

1.3 TMS320C54x Key Features

This section lists the key features of the 54x DSPs.

CPU

J J J J J J J J J

Advanced multibus architecture with one program bus, three data buses, and four address buses 40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two independent 40-bit accumulators 17-bit 17-bit parallel multiplier coupled to a 40-bit dedicated adder for nonpipelined single-cycle multiply/accumulate (MAC) operation Compare, select, store unit (CSSU) for the add/compare selection of the Viterbi operator Exponent encoder to compute the exponent of a 40-bit accumulator value in a single cycle Two address generators, including eight auxiliary registers and two auxiliary register arithmetic units Dual-CPU/core architecture on the 5420 192K words 16-bit addressable memory space (64K-words program, 64K-words data, and 64K-words I/O), with extended program memory in the 548, 549, 5402, 5410, and 5420. On-chip configurations as follows (in K words):
Device 541 542 543 545 546 548 549 5402 5410 5420
Dual-access RAM Single-access RAM

Memory

Program ROM 20 2 2 32 32 2 16 4 16 0

Program/Data ROM 8 0 0 16 16 0 16 4 0 0

DARAM SARAM 5 10 10 6 6 8 8 16 8 32 0 0 0 0 0 24 24 0 56 168

1-6

TMS320C54x Key Features

Instruction set

J J J J J J J

Single-instruction repeat and block repeat operations Block memory move instructions for better program and data management Instructions with a 32-bit long operand Instructions with 2- or 3-operand simultaneous reads Arithmetic instructions with parallel store and parallel load Conditional-store instructions Fast return from interrupt

On-chip peripherals

J J J

Software-programmable wait-state generator Programmable bank switching On-chip phase-locked loop (PLL) clock generator with internal oscillator or external clock source. With the external clock source, there are several multiplier values available from one of the following device options:
Option 1 1.0 1.5 2.0 3.0 Option 2 1.0 4.0 4.5 5.0 Option 3 Software-programmable PLL

The 541B, 545A, 546A, 548, 549, 5402, 5410, and 5420 have a software-programmable PLL and two additional saturation modes. The software-programmable PLL is described in section 8.5.2, Software-Programmable PLL, on page 8-27. The saturation modes are described in section 4.1.2, Processor Mode Status Register (PMST), on page 4-6.

Each device offers selection of clock modes from one option list only.

J J J

External bus-off control to disable the external data bus, address bus, and control signals Data bus with a bus holder feature Programmable timer
Introduction
1-7

TMS320C54x Key Features

Ports:
Serial Ports Host Port Interface 0 1 0 1 0 1 1 1 1 1 MultiChannel Buffered 0 0 0 0 0 0 0 2 3 6 Time-Division Multiplexed 0 1 1 0 0 1 1 0 0 0

Device 541 542 543 545 546 548 549 5402 5410 5420

Synchronous 2 0 0 1 1 0 0 0 0 0

Buffered 0 1 1 1 1 2 2 0 0 0

Speed: 25/20/15/12.5/10-ns execution time for a single-cycle, fixed-point instruction (40 MIPS/50 MIPS/66 MIPS/80 MIPS/100 MIPS):

Device 541

Power Supply 5V 3 V / 3.3 V

Speed 25 ns 25 ns/20 ns 15 ns 25 ns 25 ns/20 ns 25 ns/20 ns 25 ns/20 ns 15 ns 25 ns/20 ns 15 ns 20 ns/15 ns 15 ns/12.5 ns 10 ns

Package 100-pin TQFP 100-pin TQFP 100-pin TQFP 144-pin TQFP 128-pin/144-pin TQFP 100-pin TQFP 128-pin TQFP 128-pin TQFP 100-pin TQFP 100-pin TQFP 144-pin TQFP

541B 542

3 V / 3.3 V 5V 3 V / 3.3 V

543 545 545A 546 546A 548 549 VC549

3 V / 3.3 V 3 V / 3.3 V 3 V / 3.3 V 3 V / 3.3 V 3 V / 3.3 V 3.3 V 3.3 V 3.3 V (2.5 core)

t 144-pin TQFP/144-pin Micro Start BGA

144-pin TQFP/144-pin Micro Star BGA

1-8

TMS320C54x Key Features

Table Continued
Device
VC5402

Power Supply 3.3 V (1.8 core) 3.3 V (2.5 core) 3.3 V (1.8 core)

Speed 10 ns 10 ns 10 ns

Package

VC5410
VC5420

t 144-pin TQFP/176-pin Micro Start BGA 144-pin TQFP/144-pin Micro Start BGA
144-pin TQFP/144-pin Micro Star BGA

Power

J J

Power consumption control with IDLE 1, IDLE 2, and IDLE 3 instructions for power-down modes Control to disable the CLKOUT signal

Emulation: IEEE Standard 1149.1 boundary scan logic interfaced to on-chip scan-based emulation logic

Introduction

1-9

Chapter 2

Architectural Overview
This chapter provides an overview of the architectural structure of the 54x, which comprises the central processing unit (CPU), memory, and on-chip peripherals. The 54x DSPs use an advanced modified Harvard architecture that maximizes processing power with eight buses. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. For example, three reads and one write can be performed in a single cycle. Instructions with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. Also, the 54x includes the control mechanisms to manage interrupts, repeated operations, and function calling. Figure 21 shows a functional block diagram of the 54x, which includes the principal blocks and bus structure.

Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

Page
Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Internal Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Program Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.10 IEEE Standard 1149.1 Scanning Logic . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2-1

Block Diagram

Figure 21. Block Diagram of TMS320C54x Internal Hardware

System control interface Program address generation logic (PAGEN) PC, IPTR, RC, BRC, RSA, REA Data address generation logic (DAGEN) ARAU0, ARAU1 AR0AR7 ARP, BK, DP, SP

PAB PB CAB CB DAB DB EAB EB EXP encoder

D MUX

T register

T D A Sign ctr

A PC D Sign ctr A(40) B(40)

T A B C Sign ctr

S Sign ctr

Multiplier (17 17) A B Fractional MUX

MUX 0 A M U B Legend: A Accumulator A B Accumulator B C CB data bus D DB data bus E EB data bus M MAC unit P PB program bus S Barrel shifter T T register U ALU ALU(40) A B MUX

Adder(40)

COMP TRN TC

ZERO

SAT

ROUND

2-2

Memory and external interface

Peripheral interface

B A C D Sign ctr

Barrel shifter

S MSW/LSW select E

Bus Structure

2.1 Bus Structure

The 54x architecture is built around eight major 16-bit buses (four program/ data buses and four address buses):

The program bus (PB) carries the instruction code and immediate operands from program memory. Three data buses (CB, DB, and EB) interconnect to various elements, such as the CPU, data address generation logic, program address generation logic, on-chip peripherals, and data memory.

J J

The CB and DB carry the operands that are read from data memory. The EB carries the data to be written to memory.

Four address buses (PAB, CAB, DAB, and EAB) carry the addresses needed for instruction execution.

The 54x can generate up to two data-memory addresses per cycle using the two auxiliary register arithmetic units (ARAU0 and ARAU1). The PB can carry data operands stored in program space (for instance, a coefficient table) to the multiplier and adder for multiply/accumulate operations or to a destination in data space for data move instructions (MVPD and READA). This capability, in conjunction with the feature of dual-operand read, supports the execution of single-cycle, 3-operand instructions such as the FIRS instruction. The 54x also has an on-chip bidirectional bus for accessing on-chip peripherals. This bus is connected to DB and EB through the bus exchanger in the CPU interface. Accesses that use this bus can require two or more cycles for reads and writes, depending on the peripherals structure. Table 21 summarizes the buses used by various types of accesses.

Architectural Overview

2-3


Bus Structure
Legend:

2-4 Peripheral write Peripheral read Data dual read Program write Program read Access Type Dual read/coefficient read Data read/data write Data single write Data long (32-bit) read Data single read

Table 21. Bus Usage for Read and Write Accesses

hw = lw =

high 16-bit word low 16-bit word

PAB

(hw)

CAB

Address Bus

DAB

(lw)

EAB

PB

(hw)

CB

Data Bus

(lw)

DB

EB

Internal Memory Organization

2.2 Internal Memory Organization

The 54x memory is organized into three individually selectable spaces: program, data, and I/O space. All 54x devices contain both random-access memory (RAM) and read-only memory (ROM). Among the devices, two types of RAM are represented: dual-access RAM (DARAM) and single-access RAM (SARAM). Table 22 shows how much ROM, DARAM, and SARAM are available on the different 54x devices. The 54x also has 26 CPU registers plus peripheral registers that are mapped in data-memory space. The 54x memory types and features are introduced in the sections following this paragraph. For details about configuring and using the various memory blocks, see Chapter 3, Memory.

Table 22. Program and Data Memory on the TMS320C54x Devices

Memory Type ROM: Program Program/ data DARAM SARAM 541 28K 20K 8K 5K 0 542 2K 2K 0 10K 0 543 2K 2K 0 10K 0 545 48K 32K 16K 6K 0 546 48K 32K 16K 6K 0 548 2K 2K 0 8K 24K 549 16K 16K 16K 8K 24K 5402 4K 4K 4K 16K 0 5410 16K 16K 0 8K 56K 5420 0 0 0 32K 168K

You can configure the dual-access RAM (DARAM) and single-access RAM (SARAM) as data memory or program/data memory.

2.2.1

On-Chip ROM
The on-chip ROM is part of the program memory space and, in some cases, part of the data memory space. The amount of on-chip ROM available on each device varies, as shown in Table 22. On devices with a small amount of ROM (2K words), the ROM contains a bootloader that is useful for booting to faster on-chip or external RAM. For bootloading details on all 54x devices except the 548 and 549, see TMS320C54x DSP Reference Set, Volume 4: Applications Guide. For bootloading details on the 548 and 549, see TMS320C548/549 Bootloader Technical Reference. On devices with larger amounts of ROM, a portion of the ROM may be mapped into both data and program space (except the 5410). The larger ROMs are also custom ROMs: you provide the code or data to be programmed into the ROM in object file format, and Texas Instruments generates the appropriate
Architectural Overview
2-5

Internal Memory Organization

process mask to program the ROM. For details on submitting ROM codes to Texas Instruments, see Appendix C, Submitting ROM Codes to TI.

2.2.2

On-Chip Dual-Access RAM (DARAM)

The DARAM is composed of several blocks. Because each DARAM block can be accessed twice per machine cycle, the central processing unit (CPU) and peripherals such as the buffered serial port (BSP) and host port interface (HPI) can read from and write to a DARAM memory address in the same cycle. The DARAM is always mapped in data space and is primarily intended to store data values. It can also be mapped into program space and used to store program code.

2.2.3

On-Chip Single-Access RAM (SARAM)

The SARAM is composed of several blocks. Each block is accessible once per machine cycle for either a read or a write. The SARAM is always mapped in data space and is primarily intended to store data values. It can also be mapped into program space and used to store program code.

2.2.4

On-Chip Memory Security

The 54x maskable memory security option protects the contents of on-chip memories. When you designate this option, no externally originating instruction can access the on-chip memory spaces.

2.2.5

Memory-Mapped Registers
The data memory space contains memory-mapped registers for the CPU and the on-chip peripherals. These registers are located on data page 0, simplifying access to them. The memory-mapped access provides a convenient way to save and restore the registers for context switches and to transfer information between the accumulators and the other registers.

2-6

Central Processing Unit (CPU)

2.3 Central Processing Unit (CPU)

The 54x CPU is common to all the 54x devices. The 54x CPU contains:

2.3.1

40-bit arithmetic logic unit (ALU) Two 40-bit accumulators Barrel shifter 17 17-bit multiplier 40-bit adder Compare, select, and store unit (CSSU) Data address generation unit Program address generation unit

Arithmetic Logic Unit (ALU)

The 54x performs 2s-complement arithmetic with a 40-bit arithmetic logic unit (ALU) and two 40-bit accumulators (accumulators A and B). The ALU can also perform Boolean operations. The ALU uses these inputs:

16-bit immediate value 16-bit word from data memory 16-bit value in the temporary register, T Two 16-bit words from data memory 32-bit word from data memory 40-bit word from either accumulator

The ALU can also function as two 16-bit ALUs and perform two 16-bit operations simultaneously. See section 4.2, Arithmetic Logic Unit (ALU), on page 4-11, for more details about ALU operation.

2.3.2

Accumulators
Accumulators A and B (see Figure 21 on page 2-2) store the output from the ALU or the multiplier/adder block. They can also provide a second input to the ALU; accumulator A can be an input to the multiplier/adder. Each accumulator is divided into three parts:

Guard bits (bits 3932) High-order word (bits 3116) Low-order word (bits 150)

Instructions are provided for storing the guard bits, for storing the high- and the low-order accumulator words in data memory, and for transferring 32-bit accumulator words in or out of data memory. Also, either of the accumulators can be used as temporary storage for the other. See section 4.3, Accumulators A and B, on page 4-15, for more details about the features of these accumulators.
Architectural Overview
2-7

Central Processing Unit (CPU)

2.3.3

Barrel Shifter
The 54x barrel shifter has a 40-bit input connected to the accumulators or to data memory (using CB or DB), and a 40-bit output connected to the ALU or to data memory (using EB). The barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. The shift requirements are defined in the shift count field of the instruction, the shift count field (ASM) of status register ST1, or in the temporary register T (when it is designated as a shift count register). The barrel shifter and the exponent encoder normalize the values in an accumulator in a single cycle. The LSBs of the output are filled with 0s, and the MSBs can be either zero filled or sign extended, depending on the state of the sign-extension mode bit (SXM) in ST1. Additional shift capabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention operations. See section 4.4, Barrel Shifter, on page 4-19, for more details about the function and use of the shifter. See section 4.7, Exponent Encoder, on page 4-29, for more information about the encoders accumulator-normalizing function.

2.3.4

Multiplier/Adder Unit
The multiplier/adder unit performs 17 17-bit 2s-complement multiplication with a 40-bit addition in a single instruction cycle. The multiplier/adder block consists of several elements: a multiplier, an adder, signed/unsigned input control logic, fractional control logic, a zero detector, a rounder (2s complement), overflow/saturation logic, and a 16-bit temporary storage register (T). The multiplier has two inputs: one input is selected from T, a data-memory operand, or accumulator A; the other is selected from program memory, data memory, accumulator A, or an immediate value. The fast, on-chip multiplier allows the 54x to perform operations efficiently such as convolution, correlation, and filtering. In addition, the multiplier and ALU together execute multiply/accumulate (MAC) computations and ALU operations in parallel in a single instruction cycle. This function is used in determining the Euclidian distance and in implementing symmetrical and LMS filters, which are required for complex DSP algorithms. See section 4.5, Multiplier/Adder Unit, on page 4-21, for more details about the multiplier/adder unit.

2-8

Central ProcessingCentral Processing Addressing Unit (CPU) / Data Unit (CPU)

2.3.5

Compare, Select, and Store Unit (CSSU)

The compare, select, and store unit (CSSU) performs maximum comparisons between the accumulators high and low word, allows both the test/control flag bit (TC) in status register ST0 and the transition register (TRN) to keep their transition histories, and selects the larger word in the accumulator to store into data memory. The CSSU also accelerates Viterbi-type butterfly computations with optimized on-chip hardware. See section 4.6, Compare, Select, and Store Unit (CSSU), on page 4-26, for more details about this unit.

2.4 Data Addressing

The 54x offers seven basic data addressing modes:

Immediate addressing uses the instruction to encode a fixed value. Absolute addressing uses the instruction to encode a fixed address. Accumulator addressing uses accumulator A to access a location in program memory as data. Direct addressing uses seven bits of the instruction to encode the lower seven bits of an address. The seven bits are used with the data page pointer (DP) or the stack pointer (SP) to determine the actual memory address. Indirect addressing uses the auxiliary registers to access memory. Memory-mapped register addressing uses the memory-mapped registers without modifying either the current DP value or the current SP value. Stack addressing manages adding and removing items from the system stack.

During the execution of instructions using direct, indirect, or memory-mapped register addressing, the data-address generation logic (DAGEN) computes the addresses of data-memory operands. For a detailed discussion of the data addressing modes, see Chapter 5, Data Addressing.

Architectural Overview

2-9

Program Memory Addressing / Pipeline Operation Program Memory Addressing

2.5 Program Memory Addressing

Program memory is usually addressed on a 54x device with the program counter (PC). With some instructions, however, absolute addressing may be used to access data items that have been stored in program memory. (Absolute addressing is described in Chapter 5, Data Addressing.) The PC, which is used to fetch individual instructions, is loaded by the program-address generation logic (PAGEN). Typically, the PAGEN increments the PC as sequential instructions are fetched. However, the PAGEN may load the PC with a non-sequential value as a result of some instructions or other operations. Operations that cause a discontinuity include branches, calls, returns, conditional operations, single-instruction repeats, multipleinstruction repeats, reset, and interrupts. For calls and interrupts, the current PC is saved onto the stack, which is referenced by the stack pointer (SP). When the called function or interrupt service routine is finished, the PC value that was saved is restored from the stack via a return instruction. For a detailed discussion of the hardware and software factors in program address generation, see Chapter 6, Program Memory Addressing.

2.6 Pipeline Operation

An instruction pipeline consists of a sequence of operations that occur during the execution of an instruction. The 54x pipeline has six levels: prefetch, fetch, decode, access, read, and execute. At each of the levels, an independent operation occurs. Because these operations are independent, from one to six instructions can be active in any given cycle, each instruction at a different stage of completion. Typically, the pipeline is full with a sequential set of instructions, each at one of the six stages. When a PC discontinuity occurs, such as during a branch, call, or return, one or more stages of the pipeline may be temporarily unused. For more details about the pipeline operation, see Chapter 7, Pipeline.

2-10

On-Chip Peripherals

2.7 On-Chip Peripherals

All the 54x devices have the same CPU, but different on-chip peripherals are connected to their CPUs. The 54x devices have these on-chip peripheral options:

General-purpose I/O pins: XF and BIO Timer Clock generator Host port interface 8-bit standard (542, 545, 548, 549) 8-bit enhanced (5402, 5410 see note below) 16-bit enhanced (5420 see note below) Synchronous serial port (541, 545, and 546) Buffered serial port (542, 543, 545, 546, 548, and 549) Multichannel buffered serial port (McBSP) (5402, 5410, and 5420 see note below) Time-division multiplexed (TDM) serial port (542, 543, 548, and 549). Software-programmable wait-state generator Programmable bank-switching module

J J J

Note:

Enhanced Peripherals

For more detailed information on the enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

2.7.1

General-Purpose I/O Pins

Each 54x device has two general-purpose I/O pins: BIO and XF. BIO is an input pin that can be used to monitor the status of external devices. XF is a software-controlled output pin that allows you to signal external devices. See section 8.3, General-Purpose I/O, on page 8-20, for more details about BIO and XF.

2.7.2

Software-Programmable Wait-State Generator

The software-programmable wait-state generator extends external bus cycles up to seven machine cycles (14 machine cycles in the 549 , 5402, 5410, and 5420) to interface with slower off-chip memory and I/O devices. The software wait-state generator is incorporated without any external hardware. For offchip memory accesses, from zero to seven wait states can be specified within the software wait-state register (SWWSR) for each 32K-word block of program and data memory, and for the 64K-word block of I/O space. See section 10.3.1, Wait-State Generator, on page 10-5, for more details.
Architectural Overview
2-11

On-Chip Peripherals

2.7.3

Programmable Bank-Switching Logic

The programmable bank-switching logic can automatically insert one cycle when an access crosses memory bank boundaries inside program memory or data memory. One cycle can also be inserted when an access crosses from program memory to data memory. This extra cycle prevents bus contention by allowing memory devices to release the bus before other devices start driving the bus. The size of memory bank for bank switching is defined by the bank switching control register (BSCR). See section 10.3.2, Bank-Switching Logic, on page 10-8, for more details.

2.7.4

Host Port Interface

The host port interface (HPI) is a parallel port that provides an interface to a host processor. Information is exchanged between the 54x and the host processor through 54x on-chip memory that is accessible to both the host processor and the 54x. Table 23 identifies the HPI-equipped 54x devices. See section 8.6, Host Port Interface, on page 8-37, for more details about HPI operation.

Table 23. Host Port Interfaces on the TMS320C54x Devices

Host Port Interface Standard 8-bit HPI Enhanced 8-bit HPI Enhanced 16-bit HPI 541 0 0 0 542 1 0 0 543 0 0 0 545 1 0 0 546 0 0 0 548 1 0 0 549 1 0 0 5402 0 1 0 5410 0 1 0 5420 0 0 1

2.7.5

Hardware Timer
The 54x features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by 1 at every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits. See section 8.4, Timer, on page 8-21, for more details.

2-12

On-Chip Peripherals

2.7.6

Clock Generator
The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator can be driven internally by a crystal resonator with the internal oscillator or externally by a clock source. The PLL circuit can generate an internal CPU clock by multiplying the clock source by a specific factor; thus, you should use a clock source with a lower frequency than that of the CPU. For more details about the generator, see section 8.5, Clock Generator, on page 8-26.

Architectural Overview

2-13

Serial Ports

2.8 Serial Ports

The serial ports on the 54x vary by device, and are represented by four types: synchronous, buffered, multichannel buffered (McBSP), and time-division multiplexed (TDM). See Table 24 for the number of each type on the various 54x devices. The sections that follow provide an introduction to the four types of serial ports. For more details about these ports, see Chapter 9, Serial Ports. For detailed information about the McBSPs, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

Table 24. Serial Port Interfaces on the TMS320C54x Devices

Serial Ports
Synchronous Buffered Multichannel Buffered TDM

541 2 0 0 0

542 0 1 0 1

543 0 1 0 1

545 1 1 0 0

546 1 1 0 0

548 0 2 0 1

549 0 2 0 1

5402 0 0 2 0

5410 0 0 3 0

5420 0 0 6 0

2.8.1

Synchronous Serial Ports

Synchronous serial ports are high-speed, full-duplexed serial ports that provide direct communication with serial devices such as codecs, analog-to-digital (A/D) converters, and other serial systems. When more than one synchronous serial port resides on a 54x, these ports are identical but independent. Each synchronous serial port can operate at up to one-fourth the machine cycle rate (CLKOUT). The synchronous serial port transmitter and receiver are double buffered and individually controlled by maskable external interrupt signals. Data is framed either as bytes or as words.

2.8.2

Buffered Serial Ports

A buffered serial port (BSP) is a synchronous serial port that is enhanced with an autobuffering unit and is clocked at the full CLKOUT rate. It is full-duplexed and double-buffered to offer flexible data stream length. The autobuffering unit supports high-speed transfers and reduces the overhead of servicing interrupts.

2-14

Serial Ports

2.8.3

Multichannel Buffered Serial Ports (McBSPs)

The McBSP is an enhanced buffered serial port that includes the following standard features: buffered data registers, full duplex communication, and independent clocking and framing for receive and transmit. In addition, the McBSP includes the following enhanced features: internal programmable clock and frame generation, multichannel mode, and general purpose I/O. For detailed information about the McBSPs, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

2.8.4

TDM Serial Ports

A time-division multiplexed (TDM) serial port is a synchronous serial port that is enhanced to allow time-division multiplexing of the data. It can be configured for either synchronous operations or for TDM operations and is commonly used in multiprocessor applications.

Architectural Overview

2-15

External Bus Interface / IEEE Standard 1149.1 Scanning Logic External Bus Interface

2.9 External Bus Interface

The 54x can address up to 64K words of data memory, 64K words of program memory (8M words in the 548, 549, and 5410; 1M words in the 5402; 256K words in the 5420), and up to 64K words of 16-bit parallel I/O ports. Accesses to either external memory or I/O ports take place through the external interface. Individual space-select signals, DS, PS, and IS, allow the selection of physically separate spaces. The interfaces external ready input signal and software-generated wait states allow the processor to interface with memory and I/O devices of many different speeds. The interfaces hold modes allow an external device to take control of the 54x buses; in this way, an external device can access the resources in the program, data, and I/O spaces. External memory can be accessed by most 54x instructions. However, accessing I/O ports requires the use of special instructions: PORTR and PORTW. See Chapter 10, External Bus Operation, for more details about interfacing the 54x to external devices.

2.10 IEEE Standard 1149.1 Scanning Logic

The IEEE Standard 1149.1 scanning-logic circuitry is used for emulation and testing purposes only. This logic provides the boundary scan to and from the interfacing devices. Also, it can be used to test pin-to-pin continuity as well as to perform operational tests on devices peripheral to the 54x. The IEEE Standard 1149.1 scanning logic is interfaced to internal scanning-logic circuitry that has access to all of the on-chip resources. Thus, the 54x can perform on-board emulation using the IEEE Standard 1149.1 serial scan pins and the emulation-dedicated pins. For more information, see the appendix titled Design Considerations for Using XDS510 Emulator.

2-16

Chapter 3

Memory
This chapter describes the 54x memory configuration and operation. In general, the 54x devices have a total memory space of 192K 16-bit words. This space is divided into three specific memory segments: 64K words of program, 64K words of data, and 64K words of I/O. In some 54x devices, the memory structure has been modified through overlay and paging schemes to allow additional memory space. The parallel nature of the 54x architecture and the dual-access capability of the on-chip RAM allow the 54x to perform four concurrent memory operations in any given machine cycle: an instruction fetch, two-operand reads, and an operand write. There are several advantages of operating from on-chip memory:

Higher performance because no wait states are required Lower cost than external memory Lower power than external memory

The main advantage of operating from off-chip memory is the ability to access a larger memory space.

Topic
3.1 3.2 3.3 3.4 3.5

Page
Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 Program and Data Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

3-1

Memory Space

3.1 Memory Space

The 54xs memory is organized into three individually selectable spaces: program, data, and I/O. Within any of these spaces, RAM, ROM, EPROM, EEPROM, or memory-mapped peripherals can reside either on- or off-chip. The program memory space contains the instructions to execute, as well as tables used in execution. The data-memory space stores data used by instructions. The I/O memory space interfaces to external memory-mapped peripherals and can also serve as extra data storage space. Depending on the chip version, several on-chip memory types are available on the 54x: dual-access RAM (DARAM), single-access RAM (SARAM), and ROM. The RAMs are always mapped into data space, but may also be mapped into program space. The ROM may be activated and mapped into program space; it can also be mapped, in part, into data space. There are three CPU status register bits that affect memory configuration. The effects of these bits are device-specific. The MP/MC, OVLY, and DROM bits are located in the processor mode status register (PMST). For more details, see section 4.1, CPU Status and Control Registers, on page 4-2. Figure 31 through Figure 34 show the 54x devices data and program memory maps and how the maps are affected by the MP/MC, OVLY, and DROM bits.

3-2

Memory Space

Figure 31. Memory Maps for the 541

541 Program Memory
0000h OVLY = 0 OVLY = 1 0000h13FFh External 0000h007Fh Reserved 0080h13FFh On-chip DARAM 0000h

541 Data Memory

0000h005Fh 0060h007Fh 0080h13FFh Memory-mapped registers Scratch-pad DARAM On-chip DARAM

2000h

2000h

4000h 1400h8FFFh External

4000h

6000h

6000h

1400hDFFFh External 8000h 8000h

A000h

A000h

MP/MC = 0 9000hFF7Fh On-chip ROM C000h FF80hFFFFh Interrupt vectors (internal) MP/MC = 1 9000hFF7Fh External FF80hFFFFh Interrupt vectors (external) E000h E000h DROM = 0 E000hFFFFh External DROM = 1 E000hFEFFh On-chip ROM FF00hFFFFh Reserved FFFFh FFFFh C000h

Memory

3-3

Memory Space

Figure 32. Memory Maps for the 542 and 543

542/543 Program Memory 542/543 Data Memory

0000h

0000h

OVLY = 0 OVLY = 1 2000h

0000h27FFh External 0000h007Fh Reserved 0080h27FFh On-chip DARAM

0000h005Fh Memory-mapped registers 0060h007Fh Scratch-pad DARAM 2000h 0080h27FFh On-chip DARAM

4000h

4000h

6000h

6000h

8000h 2800hEFFFh External

8000h

2800hFFFFh External A000h A000h

C000h

C000h

E000h

MP/MC = 0 F000hF7FFh Reserved F800hFF7Fh On-chip ROM FF80hFFFFh Interrupt vectors MP/MC = 1 F000hFF7Fh External FF80hFFFFh Interrupt vectors

E000h

FFFFh

FFFFh

3-4

Memory Space

Figure 33. Memory Maps for the 545 and 546

545/546 Program Memory
0000h OVLY = 0 OVLY = 1 0000h17FFh External 0000h007Fh Reserved 0080h17FFh On-chip DARAM 0000h

545/546 Data Memory

0000h005Fh 0060h007Fh 0080h17FFh Memory-mapped registers Scratch-pad DARAM On-chip DARAM

2000h 1800h3FFFh External

2000h

4000h

4000h

6000h

6000h 1800hBFFFh External

8000h MP/MC = 0 4000hFF7Fh On-chip ROM FF80hFFFFh Interrupts (internal) A000h MP/MC = 1 4000hFF7Fh External FF80hFFFFh Interrupts (external)

8000h

A000h

C000h

C000h

DROM = 0 C000hFFFFh External E000h E000h DROM = 1 C000hFEFFh On-chip ROM FF00hFFFFh Reserved

FFFFh

FFFFh

Memory

3-5

Memory Space

Figure 34. Memory Maps for the 548

Hex 0000 Program Reserved (OVLY = 1) or External (OVLY = 0) Hex 0000 Program Reserved (OVLY = 1) or External (OVLY = 0) Hex 0000 005F 0060 007F 0080 On-Chip DARAM (8K Words) 1FFF 2000 On-Chip SARAM (24K Words) 7FFF 8000 External External EFFF F000 Reserved F7FF F800 FF7F FF80 FFFF MP / MC = 1 (Microprocessor Mode) FF7F FF80 FFFF MP / MC = 0 (Microcomputer Mode) External Data

Memory-Mapped Registers
Scratch-Pad RAM

007F 0080

On-Chip DARAM (OVLY = 1) or External (OVLY = 0)

007F 0080

On-Chip DARAM (OVLY = 1) or External (OVLY = 0)

1FFF 2000

On-Chip SARAM (OVLY = 1) or External (OVLY = 0)

1FFF 2000

On-Chip SARAM (OVLY = 1) or External (OVLY = 0)

7FFF 8000

7FFF 8000

On-Chip ROM (2K Words) Interrupts and Reserved (On-Chip) FFFF

Interrupts and Reserved (External)

3-6

Memory Space

Figure 35. Memory Maps for the 549

Hex 0000 Program Reserved (OVLY = 1) or External (OVLY = 0) 007F 0080 On-Chip DARAM (OVLY = 1) or External (OVLY = 0) 1FFF 2000 On-Chip SARAM (OVLY = 1) or External (OVLY = 0) 7FFF 8000 External BFFF C000 On-Chip ROM (16K Words) FEFF FF00 FF7F FF80 FFFF MP / MC = 1 (Microprocessor Mode) Interrupts and Reserved (External) Interrupts and Reserved (On-Chip) FFFF MP / MC = 0 (Microcomputer Mode) FFFF FEFF FF00 BFFF C000 On-Chip ROM (DROM = 1) or External (DROM = 0) Hex 0000 Program Reserved (OVLY = 1) or External (OVLY = 0) Hex 0000 005F 0060 007F 0080 On-Chip DARAM (8K Words) 1FFF 2000 On-Chip SARAM (24K Words) 7FFF 8000 External Data

Memory-Mapped Registers
Scratch-Pad RAM

007F 0080

On-Chip DARAM (OVLY = 1) or External (OVLY = 0)

1FFF 2000

On-Chip SARAM (OVLY = 1) or External (OVLY = 0)

7FFF 8000

External

Reserved (DROM = 1) or External (DROM = 0)

Memory

3-7

Memory Space

Figure 36. Extended Program Memory Maps for the 548 and 549
xx 0000 Page 0 32K Words 01 0000 Page 1 32K Words 02 0000 Page 2 32K Words 7F 0000 Page 127 32K Words

xx 7FFF

01 FFFF

02 FFFF

7F FFFF

00 8000 Page 0 32K Words

01 8000 Page 1 32K Words

02 8000 Page 2 32K Words

7F 8000 Page 127 32K Words

00 FFFF XPC = 0

01 FFFF XPC = 1

02 FFFF XPC = 2

7F FFFF XPC = 127

See Figure 34 and Figure 35 for more information about this on-chip memory region. These pages available when OVLY = 0 when onchip RAM is not mapped in program space or data space. When OVLY = 1 the first 32K words are all on page 0 when onchip RAM is mapped in program space or data space. NOTE: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 xx 7FFF, regardless of page number, are mapped to the on-chip RAM at 00 0000 00 7FFF.

3-8

Memory Space

Figure 37. Memory Maps for the 5402

Hex 0000 Page 0 Program Hex 0000 Reserved (OVLY = 1) External (OVLY = 0) Reserved (OVLY = 1) External (OVLY = 0) Page 0 Program Hex 0000 Data Memory Mapped Registers

005F 0060 Scratch-Pad RAM

007F 0080

007F 0080

007F 0080

On-Chip DARAM (OVLY = 1) External (OVLY = 0)

On-Chip DARAM (OVLY = 1) External (OVLY = 0)

On-Chip DARAM (16K x 16-bits)

3FFF 4000

3FFF 4000

3FFF 4000

External

External

External

EFFF F000 On-Chip ROM (4K x 16-bits) FEFF FF00

EFFF F000 ROM (DROM=1) or External (DROM=0)

Reserved
FF7F FF80 Interrupts (External) FFFF MP / MC = 1 (Microprocessor Mode) FFFF MP / MC = 0 (Microcomputer Mode) FF7F FF80 Interrupts (On-Chip)

FEFF FF00 Reserved (DROM=1) or External (DROM=0)

FFFF

Memory

3-9

Memory Space

Figure 38. Extended Program Memory for the 5402

00 0000 1 0000 Page 1 Lower 32K} External Page 0 1 7FFF 64K Words{ 1 8000 Page 1 Upper 32K External 1 FFFF 2 FFFF 2 7FFF 2 8000 Page 2 Upper 32K External 2 0000 Page 2 Lower 32K} External

...

F 0000 Page 15 Lower 32K} External

... ...

F 7FFF F 8000 Page 15 Upper 32K External

0 FFFF

...

F FFFF

See DMA memory map. The lower 32K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM is mapped to the lower 32K words of all program space pages.

3-10

Memory Space

Figure 39. Memory Maps for the 5410

Hex 0000 Program Hex 010000 Reserved (OVLY = 1) External (OVLY = 0) 007F 0080 On-Chip DARAM (OVLY = 1) External (OVLY = 0) 1FFF 2000 On-Chip SARAM1 (OVLY = 1) External (OVLY = 0) 7FFF 8000 017FFF 018000 Mapped to Lower Page 0 (OVLY = 1) External (OVLY = 0) 1FFF 2000 On-Chip SARAM1 (OVLY = 1) External (OVLY = 0) 007F 0080 On-Chip DARAM (OVLY = 1) External (OVLY = 0) Mapped to Lower Page 0 (OVLY = 1) External (OVLY = 0) Program Hex 0000 Reserved (OVLY = 1) External (OVLY = 0) Program Hex 010000 Program Hex 0000 Data

Memory-Mapped Registers 005F 0060 007F 0080 On-Chip DARAM (8K Words) 1FFF 2000 On-Chip SARAM1 (24K Words) 017FFF 018000 7FFF 8000

ScratchPad RAM

7FFF 8000

External

External

External

BFFF C000

On-Chip SARAM2 On-Chip ROM (16K Words)

On-Chip SARAM2 (DROM = 1) External (DROM = 0)

FF7F FF80 Interrupts and Reserved (External) FFFF Page 0 MP/MC= 1 (Microprocessor Mode)

FF7F FF80 Interrupts and Reserved (On-Chip ROM) 01FFFF Page 1 FFFF Page 0 MP/MC= 0 (Microcomputer Mode) 01FFFF Page 1

FFFF

Memory

3-11

Memory Space

Figure 310. Extended Program Memory Maps for the 5410 (Onchip RAM Not Mapped in Program Space and Data Space, OVLY = 0)
00 0000 01 0000 02 0000 ... 7F 0000

Page 0 64K Words

Page 1 64K Words

Page 2 64K Words

Page 127 64K Words

00 FFFF XPC = 0

01 FFFF XPC = 1

02 FFFF XPC = 2

...

7F FFFF XPC=127

Figure 311.Extended Program Memory Maps for the 5410 (Onchip RAM Mapped in Program Space and Data Space, OVLY = 1)
xx 0000 xx 7FFF Page 0 32K Words On-Chip XPC = xx

00 8000 Page 0 32K Words External 00 FFFF XPC = 0

01 8000 Page 1 32K Words On-Chip 01 FFFF XPC = 1

02 8000 Page 2 32K Words External 02 FFFF XPC = 2 ... ...

7F 8000 Page 127 32K Words External 7F FFFF XPC=127

See Figure 39 for more information about this on-chip memory region. NOTE: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 xx 7FFF, regardless of page number, are mapped to the on-chip RAM at 00 0000 00 7FFF.

3-12

Memory Space

Figure 312. Data Memory Map for the 5420 Relative to CPU Subsystems A and B
Hex 0000 005F 0060 007F 0080 Data Memory Mapped Registers ScratchPad DARAM OnChip DARAM 0 (16k Words)

3FFF 4000 OnChip SARAM 1 (16k Words)

7FFF 8000 OnChip SARAM 2 (32k Words) Prog/Data (DROM=1) External (DROM=0) FFFF

Memory

3-13

Memory Space

Figure 313. Program Memory Maps for the 5420 Relative to CPU Subsystems A and B
Hex 0000 OnChip DARAM 0 (16k Words) Prog/Data (OVLY=1) Program Page 0 Hex 10000 OnChip DARAM 0 (16k Words) Prog/Data (OVLY=1) Program Page 1 Hex 20000 OnChip DARAM 0 (16k Words) Prog/Data (OVLY=1) Program Page 2 Hex 30000 OnChip DARAM 0 (16k Words) Prog/Data (OVLY=1) Program Page 3 Hex 0000 I/O

External (OVLY=0) (EMIF) 3FFF 4000 OnChip SARAM 1 (16k Words) Prog/Data (OVL=1) External (OVLY=0) (EMIF) 7FFF 8000 OnChip SARAM 2 (32k Words) Prog/Data 17FFF 18000 13FFF 14000

External (OVLY=0) (EMIF) 23FFF 24000 OnChip SARAM 1 (16k Words) Prog/Data (OVL=1) External (OVLY=0) (EMIF) 27FFF 28000 OnChip SARAM 3 (32k Words) 2EFFF 2F000

External (OVLY=0) (EMIF) 33FFF 34000 OnChip SARAM 1 (16k Words) Prog/Data (OVL=1) External (OVLY=0) (EMIF) 37FFF 38000

External (OVLY=0) (EMIF)

OnChip SARAM 1 (16k Words) Prog/Data (OVL=1) External (OVLY=0) (EMIF)

64k External I/O Ports (EMIF)

External (EMIF)

OnChip SARAM 4 (4k Words) External (EMIF) External (EMIF)

External (EMIF)

External (EMIF)

FFFF (extended)

1FFFF (extended)

2FFFF (extended)

3FFFF (extended)

FFFF

EMIF (external memory) mode is required for all external accesses. EMIF mode is when XIO pin = 1 and the MP/MC bit is 1. A. OVLY = 1 overlays the data page and all program pages between addresses 0x00000x7FFF. B. DROM = 1 overlays 0x80000xFFFF of program and data memory. C. All internal memory is divided into 8K blocks with the exception of the 4K W block on P2 (0x2F0000x2FFFF).

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Program Memory

3.2 Program Memory

The external program memory on the 54x devices (except on the 548, 549, 5402, 5410, and 5420) addresses up to 64K 16-bit words. 54x devices have on-chip ROM, dual-access RAM (DARAM), and single-access RAM (SARAM) that can be mapped by software into the program space. When the cells are mapped into program space, the device automatically accesses them when addresses fall within their bounds. When the program address generation unit (PAGEN) generates an address outside of the bounds of on-chip memory, the device automatically generates an external access. (For more information about program address generation, see Chapter 6, Program Memory Addressing.) Table 31 shows the on-chip program memory available on the various 54x devices.

Table 31. On-Chip Program Memory Available on 54x Devices

Device 541 542 543 545 546 548 549 5402 5410 5420 ROM 28K 2K 2K 48K 48K 2K 16K 4K 16K DARAM 5K 10K 10K 6K 6K 8K 8K 16K 8K 32K SARAM 24K 24K 56K 168K

Memory

3-15

Program Memory

3.2.1

Program Memory Configurability

The MP/MC and OVLY bits determine which on-chip memories are enabled in program space. At reset, the logic level present on the MP/MC pin is transferred to the MP/MC bit in the PMST register (see section 4.1, CPU Status and Control Registers, on page 4-2). The MP/MC bit determines whether to enable the on-chip ROM. If MP/MC = 1, the device is configured as a microprocessor, and the on-chip ROM is not enabled. If MP/MC pin = 0, the device is configured as a microcomputer, and the on-chip ROM is enabled. The MP/MC pin is sampled only at reset; however, you can disable or enable the on-chip ROM through software by setting or clearing the MP/MC bit in the PMST register. Figure 31 through Figure 34 (pages 3-3 through 3-6) show the program memory configurations on the individual 54x devices.

3-16

Program Memory

3.2.2

On-Chip ROM Organization

The on-chip ROM is subdivided and organized in blocks to enhance performance. For example, the block organization enables you to fetch an instruction from one block of ROM without sacrificing data accesses that come from a different block of ROM. Figure 314 shows the way the ROM is organized in blocks for each 54x device. The gray lines in the figure indicate block boundaries.

Figure 314. On-Chip ROM Block Organization

541 4000h 4000 4FFF 5000h 5000 5FFF 6000h 6000 6FFF 7000h 7000 7FFF 8000h 8000 8FFF 9000h 9000 97FF 9000 9FFF 9800 9FFF A000h A000 AFFF B000h B000 BFFF C000h C000 CFFF D000h D000 DFFF E000h E000 EFFF F000h F000 FFFF F7FF FFFF F000 FFFF F800 FFFF E000 EFFF E000 FFFF F000 FFFF E000 FFFF D000 DFFF C000 CFFF C000 DFFF C000 DFFF B000 BFFF A000 AFFF 542/543 545/546 548 549 5402 5410

ROM is organized in 8K blocks on these devices.

Memory

3-17

Program Memory

3.2.3

Program Memory Address Map and On-Chip ROM Contents

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This feature facilitates moving the vector table out of the boot ROM and then removing the ROM from the memory map. For details on remapping the vectors, see section 6.10.9, Remapping Interrupt-Vector Addresses, on page 6-36. Note: In the on-chip ROM, 128 words are reserved for device-testing purposes. Application code written to be implemented in on-chip ROM must reserve these 128 words at addresses FF00hFF7Fh in program space.

3.2.4

On-Chip ROM Code Contents and Mapping

The 54x devices (except 5420) provide a variety of ROM sizes (4K, 16K, 24K, 28K, or 48K words). On 54x devices with on-chip bootloader ROM, the 2K words (at F800h to FFFFh) may contain one or more of the following, depending on the specific device:

A bootloader program that boots from the serial ports, external memory, an I/O port, or the host port interface (if present) A 256-word -law expansion table A 256-word A-law expansion table A 256-word sine look-up table An interrupt vector table

Figure 315 shows which of these items are on a particular 54x device and shows the addresses of each of the items. The address range for the code, F800hFFFFh, is mapped to the on-chip ROM if the MP/MC bit is 0. Note: You can submit code to Texas Instruments in object file format to program into the 54x on-chip ROM. See Appendix C, Submitting ROM Codes to TI, for details on how to submit ROM code to Texas Instruments.

3-18


Figure 315. On-Chip ROM Program Memory Map (High Addresses)
FD00h FC00h FE00h FB00h FF80h FF00h FA00h F900h F800h Interrupt vector table User-specified code 541/545/546 Reserved 542/543/548/549/5402/5410 A-law expansion table -law expansion table Interrupt vector table Sine look-up table Bootloader code Reserved

Memory

Program Memory

3-19

Program Memory

3.2.5

Extended Program Memory (Available on 548/549/5402/5410/5420)

The 548, 549, 5402, 5410, and 5420 use a paged extended memory scheme in program space to allow access of up to 8192K words of program memory. To implement this scheme, the 548, 549, 5402, 5410, and 5420 include several additional features:

23 address lines, instead of 16 (20 address lines in the 5402, and 18 in the 5420) An extra memory-mapped register, the program counter extension register (XPC) Six extra instructions for addressing extended program space

Program memory in the 548, 549, 5402, 5410, and 5420 is organized into 128 pages (16 pages in the 5402, and 4 in the 5420) that are each 64K words in length, as shown in Figure 316.

Figure 316. Extended Program Memory With On-Chip RAM Not Mapped in Program Space (OVLY = 0)
00 0000 01 0000 02 0000 7F 0000

...

Page 0 64K words

Page 1 64K words

Page 2 64K words

Page 127 64K words

...
00 FFFF 01 FFFF 02 FFFF 7F FFFF

XPC = 0

XPC = 1

XPC = 2

XPC=127

When the on-chip RAM is enabled in program space, each page of program memory is made up of two parts: a common block of 32K words maximum and a unique block of 32K words. The common block is shared by all pages and each unique block is accessible only through its assigned page. Figure 317 shows the common and unique blocks. If the on-chip ROM is enabled (MP/MC = 0), it is enabled only on page 0. It is not mapped to any other page in program memory. The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3-20

Program Memory

Figure 317. Extended Program Memory With On-Chip RAM Mapped in Program Space and Data Space (OVLY = 1)
xx 0000

Page 0 32K words

xx 7FFF

XPC = xx

00 8000

01 8000

02 8000

7F 8000

Page 0 32K words

00 FFFF 01 FFFF

Page 1 32K words

02 FFFF

Page 2 32K words

... ...
7F FFFF

Page 127 32K words

XPC = 0
Note:

XPC = 1

XPC = 2

XPC=127

When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 xx 7FFF, regardless of page number, are mapped to the on-chip RAM at 00 0000 00 7FFF. See Figure 34 on page 3-6 for more information about this on-chip memory region.

To facilitate page switching through software, the 548, 549, 5402, 5410, and 5420 have six special instructions that affect the XPC:

FB[D] Far branch FBACC[D] Far branch to the location specified by the value in accumulator A or accumulator B FCALA[D] Far call to the location specified by the value in accumulator A or accumulator B FCALL[D] Far call FRET[D] Far return FRETE[D] Far return with interrupts enabled

The following two 54x instructions are extended in the 548, 549, 5402, 5410, and 5420 to use 23 bits (20 bits in the 5402, and 18 in the 5420): READA Read program memory addressed by accumulator A and store in data memory WRITA Write data to program memory addressed by accumulator A

All other instructions do not modify the XPC and access only memory within the current page.
Memory
3-21

Data Memory

3.3 Data Memory

The data memory on the 54x contains up to 64K 16-bit words. A number of the 54x devices have on-chip ROM that can be mapped by software into the data space (DROM) in addition to any dual- and single-access RAM (DARAM and SARAM). Table 32 shows the on-chip data memory available on various 54x devices.

Table 32. On-Chip Data Memory Available on the TMS320C54x Devices

Device 541 542 543 545 546 548 549 5402 5410 5420 Program/Data ROM 8K 16K 16K 16K 4K 16K DARAM 5K 10K 10K 6K 6K 8K 8K 16K 8K 32K SARAM 24K 24K 56K 168K

Accesses to the RAM and the data ROM (when it is enabled) are made when addresses fall within the bounds of the corresponding on-chip memories. When the data-address generation logic (DAGEN) generates an address outside of the bounds of on-chip memory, the device automatically generates an external access. (For more information about the generation of data addresses, see Chapter 5, Data Addressing.)

3.3.1

Data Memory Configurability

Data memory can reside both on- and off-chip. The on-chip DARAM is mapped into data memory space. For some 54x devices, you can map a portion of the on-chip ROM (the amount shown in Table 32) into data space by setting the DROM bit located in the PMST register (see section 4.1, CPU Status and Control Registers, on page 4-2). This portion of on-chip ROM is enabled both in the data space (DROM bit) and in the program space (MP/MC bit), allowing an instruction to use the ROM area as a data ROM residing in data space. At reset, the processor clears the DROM bit to 0.

3-22

Data Memory

The data ROM is accessed in a single cycle by an instruction using single datamemory operand addressing, including an instruction with a 32-bit long word operand. In the dual-memory operand addressing, the access requires two cycles if both operands reside in the same block; if the operands reside in different blocks, the access requires a single cycle. For the address boundaries of the ROM blocks, see section 3.2.2, On-Chip ROM Organization, on page 3-17. Figure 31 through Figure 34 (pages 3-3 through 3-6) show the data memory configurations on the individual 54x devices.

3.3.2

On-Chip RAM Organization

On-chip RAM is subdivided and organized in blocks to enhance performance. For example, the block organization enables you to fetch two operands from one block of DARAM and write to another block of DARAM in the same cycle. Figure 318 on page 3-24 shows the RAM block organization for each 54x device. The gray lines in the figure indicate block boundaries. The organization of the first 1K of DARAM on all 54x devices includes the memory-mapped CPU and peripheral registers, 32 words of scratch-pad DARAM, and 896 words of DARAM.

Memory

3-23

3-24

Data Memory

Figure 318. On-Chip RAM Block Organization

7000h

6000h

5000h

4000h

3000h

2000h

1000h

0000h

0B000FFF

08000AFF

100013FF

040007FF

000003FF

Dual-access RAM 541

18001FFF

08000FFF

200027FF

100017FF

000007FF

542/543

Single-access RAM

08000FFF

100017FF

000007FF

545/546

60007FFF 40005FFF 20003FFF 18001FFF 08000FFF 000007FF 100017FF

548/549

Data Memory

Figure 319. On-Chip RAM Block Organization (5402/5410/5420)

5402 0060h 8k 1FFFh 2000h 8k 3FFFh 0080h 07FFh 0800h 0FFFh 1000h 17FFh 1800h 1FFFh 2000h 8k 3FFFh 4000h 8k 5FFFh 6000h 7FFFh n8000h 8k n9FFFh nA000h nBFFFh nC000h 8k nDFFFh nE000h nFFFFh Dualaccess RAM Singleaccess RAM
n = page, where n = 0, 1, 2 . . .127

5410 2k

5420 subsystem A or B

8k 2k 2k 8k 2k 4000h 8k 8k 8000h 8k 8k 8k 8k 8k

FFFFh 8k 18000h

8k 8k

8k 8k

2F000h 4k 2FFFFh

3.3.3

Memory-Mapped Registers
The 64K words of data memory space include the devices memory-mapped registers, which reside in data page 0 (data addresses 0000h007Fh). Data page 0 consists of the following:

The CPU registers (26 total) are accessible with no wait states; see Table 33 on page 3-26.
Memory
3-25

Data Memory

The peripheral registers are used as control and data registers in peripheral circuits. These registers reside within addresses 0020h005F and reside on a dedicated peripheral bus structure. For a list of peripherals on a particular 54x device, see section 8.2, Peripheral Memory-Mapped Registers, on page 8-2. The scratch-pad RAM block (60h7Fh in data memory) includes 32 words of DARAM for variable storage that helps avoid fragmenting the large RAM block.

3.3.4

CPU Memory-Mapped Registers

Table 33 lists the CPU memory-mapped registers. This section gives a brief summary of one or more of the registers.

3.3.4.1

Interrupt Registers (IMR, IFR)

The interrupt mask register (IMR) individually masks off specific interrupts at required times. The interrupt flag register (IFR) indicates the current status of the interrupts. Interrupts are described in detail in section 6.10, Interrupts, on page 6-26.

3.3.4.2

Status Registers (ST0, ST1)

The status registers ST0 and ST1 contain the status of the various conditions and modes for the 54x devices. ST0 contains the flags (OVA, OVB, C, and TC) produced by arithmetic operations and bit manipulations, in addition to the DP and the ARP fields. ST1 reflects the status of modes and instructions executed by the processor. See section 4.1, CPU Status and Control Registers, on page 4-2 for detailed information.

Table 33. CPU Memory-Mapped Registers

Address (Hex) 0 1 25 6 7 Name IMR IFR ST0 ST1 Description Interrupt mask register Interrupt flag register Reserved for testing Status register 0 Status register 1

3-26

Data Memory

Table 33. CPU Memory-Mapped Registers (Continued)

Address (Hex) 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1E1F Name AL AH AG BL BH BG T TRN AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK BRC RSA REA PMST XPC Description Accumulator A low word (bits 150) Accumulator A high word (bits 3116) Accumulator A guard bits (bits 3932) Accumulator B low word (bits 150) Accumulator B high word (bits 3116) Accumulator B guard bits (bits 3932) Temporary register Transition register Auxiliary register 0 Auxiliary register 1 Auxiliary register 2 Auxiliary register 3 Auxiliary register 4 Auxiliary register 5 Auxiliary register 6 Auxiliary register 7 Stack pointer Circular-buffer size register Block-repeat counter Block-repeat start address Block-repeat end address Processor mode status register Program counter extension register (548, 549, 5402, 5410, and 5420) Reserved

3.3.4.3

Accumulators (A, B)
The 54x devices have two 40-bit accumulators: accumulator A and accumulator B. Each accumulator is memory-mapped and partitioned into accumulator low word (AL, BL), accumulator high word (AH, BH), and accumulator guard bits (AG, BG). See section 4.3, Accumulators A and B, on page 4-15 for more details about these accumulator features.
Memory
3-27

Data Memory

3.3.4.4

Temporary Register (T)

The temporary (T) register has many uses. For example, it may hold:

One of the multiplicands for multiply and multiply/accumulate instructions (For more details about the T register and the processes of multiplication, see section 4.5, Multiplier/Adder Unit, on page 4-21.) A dynamic (execution-time programmable) shift count for instructions with shift operation such as the ADD, LD, and SUB instructions A dynamic bit address for the BITT instruction Branch metrics used by the DADST and DSADT instructions for ACS operation of Viterbi decoding

In addition, the EXP instruction stores the exponent value computed into T register, and then the NORM instruction uses the T register value to normalize the number.

3.3.4.5

Transition Register (TRN)

The 16-bit transition (TRN) register holds the transition decision for the path to new metrics to perform the Viterbi algorithm. The CMPS (compare select max and store) instruction updates the contents of TRN register on the basis of the comparison between the accumulator high word and the accumulator low word.

3.3.4.6

Auxiliary Registers (AR0AR7)

The eight 16-bit auxiliary registers (AR0AR7) can be accessed by the CPU and modified by the auxiliary register arithmetic units (ARAUs). The primary function of the auxiliary registers is to generate 16-bit addresses for data space. However, these registers can also act as general-purpose registers or counters. For information about the role the auxiliary registers play in datamemory addressing, see section 5.5, Indirect Addressing, on page 5-10.

3.3.4.7

Stack-Pointer Register (SP)

The 16-bit stack-pointer register (SP) contains the address of the top of the system stack. The SP always points to the last element pushed onto the stack. The stack is manipulated by interrupts, traps, calls, returns, and the PSHD, PSHM, POPD, and POPM instructions. Pushes and pops of the stack predecrement and postincrement, respectively, the 16-bit value in the stack pointer.

3.3.4.8

Circular-Buffer Size Register (BK)

The ARAUs use16-bit circular-buffer size register (BK) in circular addressing to specify the data block size. For information on BK and circular addressing, see section 5.5.3.4, Circular Address Modifications, on page 5-15.

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Data Memory

3.3.4.9

Block-Repeat Registers (BRC, RSA, REA)

The 16-bit block-repeat counter (BRC) register specifies the number of times a block of code is to repeat when a block repeat is performed. The 16-bit blockrepeat start address (RSA) register contains the starting address of the block of program memory to be repeated. The 16-bit block-repeat end address (REA) register contains the ending address of the block of program memory to be repeated. For more information about repeating multiple instructions and the BRC, RSA, and REA, see section 6.8, Repeating a Block of Instructions, on page 6-23.

3.3.4.10 Processor Mode Status Register (PMST)

The processor mode status register (PMST) controls memory configurations of the 54x devices. The PMST is described in detail in section 4.1, CPU Status and Control Registers, on page 4-2.

3.3.4.11 Program Counter Extension Register (XPC, Available on 548/549/5402/5410/5420)

The program counter extension register (XPC) contains the upper 7 bits of the current program memory address. See section 3.2.5, Extended Program Memory on page 3-20, for more information about extended memory.

Memory

3-29

I/O Memory / Program and Data Security I/O Memory

3.4 I/O Memory

The 54x devices offer an I/O memory space in addition to the program- and data-memory spaces. The I/O memory space is a 64K-word address space (0000hFFFFh) and exists only external to the device. Two instructions, PORTR and PORTW, are used to access this space. Read timings vary from those of the program- and data-memory spaces to facilitate access to individual I/O-mapped devices rather than to memories. For details of external bus operation and control for I/O accesses, see Chapter 10, External Bus Operation.

3.5 Program and Data Security

The 54x has two staged security options: on-chip ROM security and ROM/ RAM security. See Table 34 for a summary of the security feature.

Table 34. Data Security

Affect On-Chip Memory Accesses Security ROM ROM Affected for both program and data accesses. Instructions fetched from on-chip ROM may read on-chip ROM for program and data accesses. Instructions fetched from on-chip RAM or external memory will be prohibited from accessing on-chip ROM and will read invalid data (0FFFFh) on the bus for program and data accesses. ROM/RAM Affected for both program and data accesses. Instructions fetched from on-chip ROM and on-chip RAM may read on-chip ROM for program and data accesses. Instructions fetched from external memory will be prohibited from accessing on-chip ROM and will read invalid data (0FFFFh) on the bus for program and data accesses. Affected for both program and data accesses. Instructions fetched from on-chip ROM and on-chip RAM may read on-chip RAM for program and data accesses. Instructions fetched from external memory will be prohibited from accessing on-chip RAM and will read invalid data (0FFFFh) on the bus for program and data accesses. RAM Unaffected by this security option.

3-30

Chapter 4

Central Processing Unit

This chapter describes the 54x central processing unit (CPU) operations. The CPU can perform high-speed arithmetic operations within one instruction cycle because of its parallel architectural design. The following CPU functional components are discussed in this chapter:

40-bit arithmetic logic unit (ALU) Two 40-bit accumulator registers Barrel shifter supporting a 16 to 31 shift range Multiply/accumulate block 16-bit temporary register (T) 16-bit transition register (TRN) Compare, select, and store unit (CSSU) Exponent encoder

The CPU registers are memory-mapped, enabling quick saves and restores.

Topic
4.1 4.2 4.3 4.4 4.5 4.6 4.7

Page
CPU Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Arithmetic LogIc Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Accumulators A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Multiplier/Adder Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Compare, Select, and Store Unit (CSSU) . . . . . . . . . . . . . . . . . . . . . . . 4-26 Exponent Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

4-1

CPU Status and Control Registers

4.1 CPU Status and Control Registers

The 54x has three status and control registers:

Status register 0 (ST0) Status register 1 (ST1) Processor mode status register (PMST)

ST0 and ST1 contain the status of various conditions and modes; PMST contains memory-setup status and control information. Because these registers are memory-mapped, they can be stored into and loaded from data memory; the status of the processor can be saved and restored for subroutines and interrupt service routines (ISRs).

4.1.1

Status Registers (ST0 and ST1)

The individual bits of the ST0 and ST1 registers can be set or cleared with the SSBX and RSBX instructions. For example, the sign-extension mode is set with SSBX 1, SXM, or reset with RSBX 1, SXM. The ARP, DP, and ASM bit fields can be loaded using the LD instruction with a short-immediate operand. The ASM and DP fields can be also loaded with data-memory values by using the LD instruction. The ST0 bits are shown in Figure 41 and described in Table 41. The ST1 bits are shown in Figure 42 and described in Table 42 on page 4-4.

Figure 41. Status Register 0 (ST0) Diagram

1513 ARP 12 TC 11 C 10 OVA 9 OVB 80 DP

Table 41. Status Register 0 (ST0) Bit Summary

Bit Name Reset Value 0 Function Auxiliary register pointer. This 3-bit field selects the auxiliary register to use in the compatibility mode of indirect single-operand addressing (see section 5.5, Indirect Addressing, page 5-10). ARP must always be set to zero when the DSP is in standard mode (CMPT = 0).

15 13 ARP

4-2

CPU Status and Control Registers

Table 41. Status Register 0 (ST0) Bit Summary (Continued)

Bit 12 Name TC Reset Value 1 Function Test/control flag. TC stores the results of the arithmetic logic unit (ALU) test bit operations. TC is affected by the BIT, BITF, BITT, CMPM, CMPR, CMPS, and SFTC instructions. The status (set or cleared) of TC determines if the conditional branch, call, execute, and return instructions execute. TC = 1 if the following conditions are true:

11 C 1

A bit tested by BIT or BITT is a 1. A compare condition tested by CMPM, CMPR, or CMPS exists between a datamemory value and an immediate operand, AR0 and another auxiliary register, or an accumulator high word and an accumulator low word. Bit 31 and bit 30 of an accumulator tested by SFTC have different values from each other.

Carry is set to 1 if the result of an addition generates a carry; it is cleared to 0 if the result of a subtraction generates a borrow. Otherwise, it is reset after an addition and it is set after a subtraction, except for an ADD or SUB with a 16-bit shift. In these cases, the ADD can only set and the SUB only reset the carry bit, but they cannot affect it otherwise. Carry and borrow are defined at the 32nd bit position and are operated at the ALU level only. The shift and rotate instructions (ROR, ROL, SFTA, and SFTL), and the MIN, MAX, ABS, and NEG instructions also affect this bit. Overflow flag for accumulator A. OVA is set to 1 when an overflow occurs in either the ALU or the multipliers adder and the destination for the result is accumulator A. Once an overflow occurs, OVA remains set until either a reset, a BC[D], a CC[D], an RC[D], or an XC instruction is executed using the AOV and ANOV conditions. The RSBX instruction can also clear this bit. Overflow flag for accumulator B. OVB is set to 1 when an overflow occurs in either the ALU or the multipliers adder and the destination for the result is accumulator B. Once an overflow occurs, OVB remains set until either a reset, a BC[D], a CC[D], an RC[D], or an XC instruction is executed using the BOV and BNOV conditions. This RSBX instruction can also clear this bit. Data-memory page pointer. This 9-bit field is concatenated with the seven LSBs of an instruction word to form a direct-memory address of 16 bits for single datamemory operand addressing. This operation is done if the compiler mode bit in ST1 (CPL) = 0. The DP field can be loaded by the LD instruction with a short-immediate operand or from data memory.

10

OVA

OVB

80

DP

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4-3

CPU Status and Control Registers

Figure 42. Status Register 1 (ST1) Diagram

15 BRAF 14 CPL 13 XF 12 HM 11 INTM 10 0 9 OVM 8 SXM 7 C16 6 FRCT 5 CMPT 40 ASM

Table 42. Status Register 1 (ST1) Bit Summary

Bit 15 Name BRAF Reset Value 0 Function Block-repeat active flag. BRAF indicates whether a block repeat is currently active. BRAF = 0 BRAF = 1 14 CPL 0 The block repeat is deactivated. BRAF is cleared when the blockrepeat counter (BRC) decrements below 0. The block repeat is active. BRAF is automatically set when an RPTB instruction is executed.

Compiler mode. CPL indicates which pointer is used in relative direct addressing: CPL = 0 CPL = 1 The relative direct-addressing mode using the data page pointer (DP) is selected. The relative direct-addressing mode using the stack pointer (SP) is selected.

13

XF

XF status. XF indicates the status of the external flag (XF) pin, which is a generalpurpose output pin. The SSBX instruction can set XF and the RSBX instruction can reset XF. Hold mode. HM indicates whether the processor continues internal execution when acknowledging an active HOLD signal: HM = 0 HM = 1 The processor continues execution from internal program memory but places its external interface in the high-impedance state. The processor halts internal execution.

12

HM

11

INTM

Interrupt mode. INTM globally masks or enables all interrupts. INTM = 0 INTM = 1 All unmasked interrupts are enabled. All maskable interrupts are disabled.

The SSBX instruction sets INTM and the RSBX instruction resets INTM. INTM is set to 1 by reset or when a maskable interrupt trap is taken (INTR or external interrupts). INTM is cleared to 0 when a RETE or RETF instruction (return from interrupt) is executed. INTM does not affect the nonmaskable interrupts (RS and NMI). INTM cannot be set by memory-write operations. 10 0 Always read as 0.

4-4

CPU Status and Control Registers

Table 42. Status Register 1 (ST1) Bit Summary (Continued)

Bit 9 Name OVM Reset Value 0 Function Overflow mode. OVM determines what is loaded into the destination accumulator when an overflow occurs: OVM = 0 An overflowed result from either the ALU or the multipliers adder overflows normally in the destination accumulator. The destination accumulator is set to either the most positive value (00 7FFF FFFFh) or the most negative value (FF 8000 0000h) upon encountering an overflow.

OVM = 1

The SSBX and RSBX instructions set and reset OVM, respectively. 8 SXM 1 Sign-extension mode. SXM determines whether sign extension is performed: SXM = 0 SXM = 1 Sign extension is suppressed. Data is sign extended before being used by the ALU.

SXM does not affect the definitions of certain instructions: the ADDS, LDU, and SUBS instructions suppress sign extension regardless of SXM value. The SSBX and RSBX instructions set and reset SXM, respectively. 7 C16 0 Dual 16-Bit/double-precision arithmetic mode. C16 determines the arithmetic mode of the ALUs operation: C16 = 0 C16 = 1 6 FRCT 0 The ALU operates in double-precision arithmetic mode. The ALU operates in dual 16-bit arithmetic mode.

Fractional mode. When FRCT is 1, the multiplier output is left-shifted by one bit to compensate for an extra sign bit. Compatibility mode. CMPT determines the compatibility mode for the ARP: CMPT = 0 ARP is not updated in indirect addressing mode with a single datamemory operand. ARP must always be set to 0 when the DSP is in this mode. ARP is updated in indirect addressing mode with a single datamemory operand, except when the instruction is selecting auxiliary register 0 (AR0).

CMPT

CMPT = 1

40

ASM

Accumulator shift mode. The 5-bit ASM field specifies a shift value within a 16 through 15 range and is coded as a 2s-complement value. Instructions with a parallel store, as well as STH, STL, ADD, SUB, and LD, use this shift capability. ASM can be loaded from data memory or by the LD instruction using a short-immediate operand.

Central Processing Unit

4-5

CPU Status and Control Registers

4.1.2

Processor Mode Status Register (PMST)

The PMST register is loaded with memory-mapped register instructions such as STM. The PMST bits are shown in Figure 43 and described in Table 43.

Figure 43. Processor Mode Status Register (PMST) Diagram

157 IPTR 6 MP/MC 5 OVLY 4 AVIS 3 DROM 2 CLKOFF 1 SMUL 0 SST

Refer to the device-specific datasheet to determine if these bits are supported.

Table 43. Processor Mode Status Register (PMST) Bit Summary

Bit 15 7 Name IPTR Reset Value 1FFh Function Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. You can remap the interrupt vectors to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program-memory space. The RESET instruction does not affect this field.

MP/MC

MP/MC Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip pin ROM to be addressable in program memory space. MP/MC = 0 MP/MC = 1 The on-chip ROM is enabled and addressable. The on-chip ROM is not available.

MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software. 5 OVLY 0 RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are: OVLY = 0 OVLY = 1 The on-chip RAM is addressable in data space but not in program space. The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh), however, is not mapped into program space.

Refer to the device-specific datasheet to determine if these bits are supported.

4-6

CPU Status and Control Registers

Table 43. Processor Mode Status Register (PMST) Bit Summary (Continued)
Bit 4 Name AVIS Reset Value 0 Function Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins. AVIS = 0 The external address lines do not change with the internal program address. Control and data lines are not affected and the address bus is driven with the last address on the bus. This mode allows the internal program address to appear at the pins of the 54x so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside in on-chip memory.

AVIS = 1

DROM

Data ROM. DROM enables on-chip ROM to be mapped into data space. The values for the DROM bit are: DROM = 0 DROM = 1 The on-chip ROM is not mapped into data space. A portion of the on-chip ROM is mapped into data space. See Chapter 3, Memory, for details.

2 1

CLKOFF SMUL

0 N/A

CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level. Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before performing the accumulation in a MAC or MAS instruction. The SMUL bit applies only when OVM = 1 and FRCT = 1. SMUL bit allows the MAC and MAS operations to be consistent with MAC and MAS basic operation defined in ETSI GSM specifications (GSM specs 6.06, 6.10, 6.53). The effect is that the result of 8000h 8000h is saturated to 7FF FFFFh in fractional mode, before performing subsequent addition/subtraction required by a MAC or MAS instruction. In this mode, the MAC instruction is equivalent to MPY + ADD when OVM=1. If the mode is not set and OVM = 1, the result of the multiplication is not saturated before performing the addition/ subtraction, only the results of the MAC and MAS instructions are saturated.

See Example 41 on page 4-9 for examples of saturation on multiplication operations.

Refer to the device-specific datasheet to determine if these bits are supported.

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CPU Status and Control Registers

Table 43. Processor Mode Status Register (PMST) Bit Summary (Continued)
Bit 0 Name SST Reset Value N/A Function Saturation on store. When SST 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation. Saturation on store takes place with the following instructions: STH, STL, STLM, DST, ST||ADD, ST||LD, ST||MACR[R], ST||MAS[R], ST||MPY, and ST||SUB. The following steps are performed when using saturate on store: 1) A 40-bit data value is shifted (right or left) depending on the instruction. The shift is the same as described in the SFTA instruction and depends on the SXM bit. The 40-bit data value is saturated to a 32-bit value; the saturation depends on the SXM bit (the number is always assumed to be positive). If SXM = 0, the following 32-bit value is generated:

2)

J J J
3) 4)

7FFF FFFFh if the value is greater than 7FFF FFFFh

If SXM = 1, the following 32-bit value is generated: 7FFF FFFFh if the value is greater than 7FFF FFFFh 8000 0000h if the value is less than 8000 0000h

The data is stored in memory depending upon instruction. The accumulator contents remain unchanged during the operation.

See Example 42 on page 4-10 for examples of saturation on store operations.

Refer to the device-specific datasheet to determine if these bits are supported.

4-8

CPU Status and Control Registers

Example 41. Use of SMUL Bit

MAC *AR1+, A ;SMUL=1, FRCT=1, OVM=1, SXM=1
Before Instruction A T AR1 Data Memory 100h 8000h FF FFFF FFFFh 8000h 100h Data Memory 100h 8000h A T AR1 After Instruction 00 7FFF FFFEh 8000h 101h

MAC

*AR1+, A

;SMUL=0, FRCT=1, OVM=1, SXM=1

Before Instruction After Instruction A T AR1 Data Memory 8000h 100h 8000h 00 7FFF FFFFh 8000h 102h

A T AR1 Data Memory 100h

FF FFFF FFFFh 8000h 101h

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4-9

CPU Status and Control Registers

Example 42. Use of SST Bit

STH A, 4, *AR1+ ;SXM=1, SST=1
Before Instruction A AR1 Data Memory 100h 5555h 7F FFFF 0000h 100h Data Memory 100h 7FFFh A AR1 After Instruction 7F FFFF 0000h 101h

STL A, 4, *AR1+ ;SXM=1, SST=1

Before Instruction A AR1 Data Memory 101h 0 AAAAh 7F FFFF 0000h 101h Data Memory 101h 0 FFFFh A AR1 After Instruction 7F FFFF 0000h 102h

DST B, *AR3

;SXM=0, SST=1
Before Instruction B AR3 8F FFFF 0000h 103h Data Memory 1234h 5678h 102h 103h 0 FFFFh 0 FFFFh B AR3 After Instruction 8F FFFF 0000h 101h

Data Memory 102h 103h

4-10

Arithmetic Logic Unit (ALU)

4.2 Arithmetic Logic Unit (ALU)

The 40-bit ALU, shown in Figure 44, implements a wide range of arithmetic and logical functions, most of which execute in a single clock cycle. After an operation is performed in the ALU, the result is usually transferred to a destination accumulator (accumulator A or B). Instructions that perform memory-tomemory operations (ADDM, ANDM, ORM, and XORM) are exceptions.

Figure 44. ALU Functional Diagram

CB15 CB0 T DB15 DB0

A 40 40

B T MUX

D MUX Sign ctr

Shifter output (40)

SXM

Sign ctr

SXM

A ACC

ALU MUX 40 A M MAC output U B 40 40

OVM C16 C OVA/OVB ZA/ZB TC

Legend: A Accumulator A B Accumulator B C CB data bus D DB data bus M MAC unit S Barrel shifter T T register U ALU

4.2.1

ALU Input
ALU input takes several forms from several sources. The X input source to the ALU is either of two values:

The shifter output (a 32-bit or 16-bit data-memory operand or a shifted accumulator value)
Central Processing Unit
4-11

Arithmetic Logic Unit (ALU)

A data-memory operand from data bus DB

The Y input source to the ALU is any of three values: The value in one of the accumulators (A or B) A data-memory operand from data bus CB The value in the T register

When a 16-bit data-memory operand is fed through data bus CB or DB, the 40-bit ALU input is constructed in one of two ways: If bits 15 through 0 contain the data-memory operand, bits 39 through 16 are zero filled (SXM = 0) or sign-extended (SXM = 1). If bits 31 through 16 contain the data-memory operand, bits 15 through 0 are zero filled, and bits 39 through 32 are either zero filled (SXM = 0) or sign extended (SXM = 1).

Table 44 shows how the ALU inputs are obtained for the ADD instructions, depending on the type of syntax used. The ADD instructions execute in one cycle, except for cases 4, 7, and 8 that use two words and execute in two cycles.

Table 44. ALU Input Selection for ADD Instructions

4-12

Case 1 2 3 4 5 6 7 8 9 Instruction Syntax ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD *AR1, A Words 1 1 1 2 1 1 2 2 1 1 1 A B DB CB Shift *AR3, TS, A *AR2, 16, B, A *AR1, 8, B, A *AR2, 8, B *AR2, *AR3, A #1234h, 6, A, B #1234h, 16, A, B A, 12, B 10 11 B, ASM, A DADD *AR2, A, B

Arithmetic Logic Unit (ALU)

4.2.2

Overflow Handling
The ALU saturation logic prevents a result from overflowing by keeping the result at a maximum (or minimum) value. This feature is useful for filter calculations. The logic is enabled when the overflow mode bit (OVM) in status register ST1 is set. When a result overflows:

If OVM = 0, the accumulators are loaded with the ALU result without modification. If OVM = 1, the accumulators are loaded with either the most positive 32-bit value (00 7FFF FFFFh) or the most negative 32-bit value (0FF 8000 0000h), depending on the direction of the overflow. The overflow flag (OVA/OVB) in status register ST0 is set for the destination accumulator and remains set until one of the following occurs:

J J J
Note:

A reset is performed. A conditional instruction (such as a branch, a return, a call, or an execute) is executed on an overflow condition. The overflow flag (OVA/OVB) is cleared.

You can saturate the accumulator by using the SAT instruction, regardless of the value of OVM.

4.2.3

The Carry Bit

The ALU has an associated carry bit (C) that is affected by most arithmetic ALU instructions, including rotate and shift operations. The carry bit supports efficient computation of extended-precision arithmetic operations. The carry bit is not affected by loading the accumulator, performing logical operations, or executing other nonarithmetic or control instructions, so it can be used for overflow management. Two conditional operands, C and NC, enable branching, calling, returning, and conditionally executing according to the status (set or cleared) of the carry bit. Also, the RSBX and SSBX instructions can be used to load the carry bit. The carry bit is set on a hardware reset.
Central Processing Unit
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Arithmetic Logic Unit (ALU)

4.2.4

Dual 16-Bit Mode

For arithmetic operations, the ALU can operate in a special dual 16-bit arithmetic mode that performs two 16-bit operations (for instance, two additions or two subtractions) in one cycle. You can select this mode by setting the C16 field of ST1. This mode is especially useful for the Viterbi add/compare/select operation (see section 4.6, Compare, Select, and Store Unit (CSSU), on page 4-26).

4-14

Accumulators A and B

4.3 Accumulators A and B

Accumulator A and accumulator B can be configured as the destination registers for either the multiplier/adder unit or the ALU. In addition, they are used for MIN and MAX instructions or for the parallel instruction LD||MAC, in which one accumulator loads data and the other performs computations. Each accumulator is split into three parts, as shown in Figure 45 and Figure 46.

Figure 45. Accumulator A

3932 AG
Guard bits

3116 AH
High-order bits

150 AL
Low-order bits

Figure 46. Accumulator B

3932 BG
Guard bits

3116 BH
High-order bits

150 BL
Low-order bits

The guard bits are used as a headmargin for computations. Headmargins allow you to prevent some overflow in iterative computations such as autocorrelation. AG, BG, AH, BH, AL, and BL are memory-mapped registers that can be pushed onto and popped from the stack for context saves and restores by using PSHM and POPM instructions. These registers can also be used by other instructions that use memory-mapped registers (MMR) for page 0 addressing. The only difference between accumulators A and B is that bits 3216 of A can be used as an input to the multiplier in the multiplier/adder unit.

4.3.1

Storing Accumulator Contents

You can store accumulator contents in data memory by using the STH, STL, STLM, and SACCD instructions or by using parallel-store instructions. To store the 16 MSBs of the accumulator in memory with a shift, use the STH, SACCD, and parallel-store instructions. For right-shift operations, bits from AG and BG shift into AH and BH. For left-shift operations, bits from AL and BL shift into AH and BH, respectively. To store the 16 LSBs of the accumulator in memory with a shift, use the STL instruction. For right-shift operations, bits from AH and BH shift into AL and BL,
Central Processing Unit
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Accumulators A and B

respectively, and the LSBs are lost. For left-shift operations, the bits in AL and BL are filled with zeros. Since shift operations are performed in the shifter, the contents of the accumulator remain unchanged. Example 43 shows the result of accumulator store operations with shift; it assumes that accumulator A = 0FF 4321 1234h.

Example 43. Accumulator Store With Shift

STH STH STL STL A,8,TEMP A,-8,TEMP A,8,TEMP A,-8,TEMP ; ; ; ; TEMP TEMP TEMP TEMP = = = = 2112h FF43h 3400h 2112h

4.3.2

Accumulator Shift and Rotate Operations

The following instructions shift or rotate the contents of the accumulator through the carry bit:

SFTA (shift arithmetically) SFTL (shift logically) SFTC (shift conditionally) ROL (rotate accumulator left) ROR (rotate accumulator right) ROLTC (rotate accumulator left with TC)

In SFTA and SFTL, the shift count is defined as 16 SHIFT 15. SFTA is affected by the SXM bit. When SXM = 1 and SHIFT is a negative value, SFTA performs an arithmetic right shift and maintains the sign of the accumulator. When SXM = 0, the MSBs of the accumulator are zero filled. SFTL is not affected by the SXM bit; it performs the shift operation for bits 310, shifting 0s into the MSBs or LSBs, depending on the direction of the shift. SFTC performs a 1-bit left shift when both bits 31 and 30 are 1 or both are 0. This normalizes 32 bits of the accumulator by eliminating the most significant nonsign bit. ROL rotates each bit of the accumulator to the left by one bit, shifts the value of the carry bit into the LSB of the accumulator, shifts the value of the MSB of the accumulator into the carry bit, and clears the accumulators guard bits. ROR rotates each bit of the accumulator to the right by one bit, shifts the value of the carry bit into the MSB of the accumulator, shifts the value of the LSB of the accumulator into the carry bit, and clears the accumulators guard bits. The ROLTC instruction (rotate accumulator left with TC) rotates the accumulator to the left and shifts the test control (TC) bit into the LSB of the accumulator.
4-16

Accumulators A and B

4.3.3

Saturation Upon Accumulator Store

The SST bit in PMST determines whether or not the data in an accumulator is saturated before storing it in memory. The saturation is performed after the shift operation. Saturation on store is available with ten instructions:

STH STL STLM DST

ST || ADD ST || LD ST || MAC[R] ST || MAS[R]

ST || MPY ST || SUB

The following steps are performed when saturating upon accumulator store: 1) The 40-bit data value is shifted (right or left) depending on the instruction. The shift is the same as described in the SFTA instruction and depends on the value of the SXM bit. 2) The 40-bit value is saturated to a 32-bit value. The saturation depends on the value of the SXM bit (the number is always assumed to be positive):

J J

SXM = 0. 7FFF FFFFh is generated if the 40-bit value is greater than or equal to 7FFF FFFFh. SXM = 1. 7FFF FFFFh is generated if the 40-bit value is greater than 7FFF FFFFh. 8000 0000h is generated if the 40-bit value is less than 8000 0000h.

3) The data is stored in memory depending on the instruction (either 16-bit LSB, 16-bit MSB, or 32-bit data). The accumulator remains unchanged during this process.

4.3.4

Application-Specific Instructions
Each accumulator is dedicated to specific operations in application-specific instructions with parallel operations. These include symmetrical FIR filter operations using the FIRS instruction, adaptive filter operations using the LMS instruction, Euclidean distance calculations using the SQDST instruction, and other parallel operations:

FIRS performs operations for symmetric FIR filters by using multiply/ accumulates (MACs) in parallel with additions. LMS performs a MAC and a parallel add with rounding to efficiently update the coefficients in an FIR filter. SQDST performs a MAC and a subtract in parallel to calculate Euclidean distance.
Central Processing Unit
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Accumulators A and B

FIRS multiplies accumulator A(3216) with a program-memory value addressed by a program-memory address and adds the result to the value in accumulator B. At the same time, it adds the memory operands Xmem and Ymem, shifts the result left 16 bits, and loads this value into accumulator A. In the LMS instruction, accumulator B stores the interim results of the input sequence convolution and filter coefficients; accumulator A updates the filter coefficients. Accumulator A can also be used as an input for MAC, which contributes to single-cycle execution of instructions with parallel operations. The SQDST instruction computes the square of the distance between two vectors. Accumulator A(3216) is squared and the product is added to accumulator B. The result is stored in accumulator B. At the same time, Ymem is subtracted from Xmem and the difference is stored in accumulator A. The value that is squared is the value of the accumulator before the subtraction, Ymem Xmem, is executed.

4-18

Barrel Shifter

4.4 Barrel Shifter

The barrel shifter is used for scaling operations such as:

Prescaling an input data-memory operand or the accumulator value before an ALU operation Performing a logical or arithmetic shift of the accumulator value Normalizing the accumulator Postscaling the accumulator before storing the accumulator value into data memory

The 40-bit shifter (see Figure 47 on page 4-20) is connected as follows: The input is connected to:

J J J J J

DB for a 16-bit data input operand DB and CB for a 32-bit data input operand Either one of the two 40-bit accumulators

The output is connected to: One of the ALU inputs The EB bus through the MSW/LSW write select unit

The SXM bit controls signed/unsigned extension of the data operands; when the bit is set, sign extension is performed. Some instructions, such as LDU, ADDS, and SUBS operate with unsigned memory operands and do not perform sign extension, regardless of the SXM value. The shift count determines how many bits to shift. Positive shift values correspond to left shifts, whereas negative values correspond to right shifts. The shift count is specified as a 2s-complement value in several ways, depending on the instruction type. An immediate operand, the accumulator shift mode (ASM) field of ST1, or T can be used to define the shift count:

A 4 or 5-bit immediate value specified in the operand of an instruction represents a shift count value in the 16 to 15 range. For example:
ADD A,-4,B ; ; ; ; ; Add accumulator A (right-shifted 4 bits) to accumulator B (one word, one cycle). Shift (logical) accumulator A eight bits left (one word, one cycle)

SFTL

A,+8

The ASM value represents a shift count value in the 16 to 15 range and can be loaded by the LD instruction (with an immediate operand or with a data-memory operand). For example:
ADD A, ASM, B ; Add accumulator A to accumulator B ; with a shift specified by ASM
Central Processing Unit
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Barrel Shifter

The six LSBs of T represent a shift count value in the 16 to 31 range. For example:
NORM A ; Normalize accumulator A (T ; contains the exponent value)

Figure 47. Barrel Shifter Functional Diagram

DB15 DB0 A B 40 16 40 B A D MUX C 16 CB15 CB0

Sign control

SXM

T : 16 through 31 range TC (test bit) Barrel shifter (16 to 31) ASM(40) : 16 through 15 range Instruction register immediate: 16 through 15 or 0 through 15 range ALU 40 CSSU MSW/LSW Write select 16 EB15 EB0

Legend: A Accumulator A B Accumulator B C CB data bus D DB data bus T T register

4-20

Multiplier/Adder Unit

4.5 Multiplier/Adder Unit

The 54x CPU has a 17-bit 17-bit hardware multiplier coupled to a 40-bit dedicated adder. This multiplier/adder unit provides multiply and accumulate (MAC) capability in one pipeline phase cycle. The multiplier/adder unit is shown in Figure 48 on page 4-22. The multiplier can perform signed, unsigned, and signed/unsigned multiplication with the following constraints:

For signed multiplication, each 16-bit memory operand is assumed to be a 17-bit word with sign extension. For unsigned multiplication, a 0 is added to the MSB (bit 16) in each input operand. For signed/unsigned multiplication, one of the operands is sign extended, and the other is extended with a 0 in the MSB (zero filled).

The multiplier output can be shifted left by one bit to compensate for the extra sign bit generated by multiplying two 16-bit 2s-complement numbers in fractional mode. (Fractional mode is selected when the FRCT bit = 1 in ST1.) The adder in the multiplier/adder unit contains a zero detector, a rounder (2s complement), and overflow/saturation logic. Rounding consists of adding 215 to the result and then clearing the lower 16 bits of the destination accumulator. Rounding is performed in some multiply, MAC, and multiply/subtract (MAS) instructions when the suffix R is included with the instruction. The LMS instruction also rounds to minimize quantization errors in updated coefficients. The adders inputs come from the multipliers output and from one of the accumulators. Once any multiply operation is performed in the unit, the result is transferred to a destination accumulator (A or B).

Central Processing Unit

4-21

Multiplier/Adder Unit

Figure 48. Multiplier/Adder Functional Diagram

CB15 CB0 DB15 DB0 PB15 PB0 40 40 From accumulator A From accumulator B

T T D X MUX A P A D C

17

Y MUX

Sign ctr 17 XM

Sign ctr 17 YM 0 A B MUX

Multiplier (17 17)

Legend: A Accumulator A B Accumulator B C CB data bus D DB data bus P PB program bus T T register

FRCT

Fract/int

XA Adder (40)

YA OVM

OVA / OVB Zero detect Round SAT ZA /ZB 40 To accumulator A / B

4.5.1

Multiplier Input Sources

This section lists sources for multiplier inputs and discusses how multiplier inputs can be selected for various instructions. The XM input source to the multiplier is any of the following values:

4-22

The temporary register (T) A data-memory operand from data bus DB Accumulator A bits 32 16

Multiplier/Adder Unit

The YM input source to the multiplier is any of the following values:

A data-memory operand from data bus DB A data-memory operand from data bus CB A program-memory operand from program bus PB Accumulator A bits 32 16

Table 45 shows how the multiplier inputs are obtained for several instructions. There are a total of nine combinations of multiplier inputs that are actually used. For instructions using T as one input, the second input may be obtained as an immediate value or from data memory via a data bus (DB), or from accumulator A. For instructions using single data-memory operand addressing, one operand is fed into the multiplier via DB. The second operand may come from T, as an immediate value or from program memory via PB, or from accumulator A. For instructions using dual data-memory operand addressing, DB and CB carry the data into the multiplier. The last two cases are used with the FIRS instruction and the SQUR and SQDST instructions. The FIRS instruction obtains inputs from PB and accumulator A. The SQUR and SQDST obtain both inputs from accumulator A.

X Multiplexer T DB A Y Multiplexer CB DB Case 1 2 3 4 5 6 7 8 9 Instruction Type MPY PB A #1234h, A MPY[R] *AR2, A MPYA B MACP MPY *AR2, pmad, A *AR2, *AR3, B *AR2, B SQUR MPYA FIRS *AR2 *AR2, *AR3, pmad A, B SQUR

Table 45. Multiplier Input Selection for Several Instructions

Central Processing Unit

4-23

Multiplier/Adder Unit

T provides one operand for multiply and multiply/accumulate instructions; the other memory operand is a single data-memory operand. T also provides an operand for multiply instructions with parallel load or parallel store, such as LD||MAC, LD||MAS, ST||MAC, ST||MAS, and ST||MPY. T can be loaded explicitly by instructions that support a memory-mapped register addressing mode or implicitly during multiply operations. Since bits A(3216) can be an input to the multiplier, some sequences that require storing the result of one computation in memory and feeding this result to the multiplier can be made faster. For some application-specific instructions (FIRS, SQDST, ABDST, and POLY), the contents of accumulator A can be computed by the ALU and then input to the multiplier without any overhead.

4.5.2

Multiply/Accumulate (MAC) Instructions

MAC instructions use the multipliers computational bandwidth to simultaneously process two operands. Multiple arithmetic operations can be performed in a single cycle by the multiplier/adder unit. In the MAC, MAS, and MACSU instructions with dual data-memory operand addressing, data can be transferred to the multiplier during each cycle via CB and DB and multiplied and added in a single cycle. Data addresses for these operands are generated by ARAU0 and ARAU1, the auxiliary register arithmetic units. For information about ARAU0 and ARAU1, see section 5.5.2, ARAU and Address-Generation Operation, on page 5-11. In the MACD and MACP instructions, data can be transferred to the multiplier during each cycle via DB and PB. DB retrieves data from data memory, and PB retrieves coefficients from program memory. When MACD and MACP are used with repeat instructions (RPT and RPTZ), they perform single-cycle MAC operations with sequential access of data and coefficients. Data addresses are generated by ARAU0 and the program address register (PAR). The datamemory address is updated by ARAU0 according to a single data-memory operand in the indirect addressing mode; the program-memory address is incremented by PAGEN. The repeated MACD instruction supports filtering constructs (weighted running average). While the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. MAC and MACP instructions with circular addressing can also support filter implementation. The FIRS instruction implements an efficient symmetric structure for the FIR filter when circular addressing is used.

4-24

Multiplier/Adder Unit

The MPYU and MACSU instructions facilitate extended-precision arithmetic operations. The MPYU instruction performs an unsigned multiplication. The unsigned contents of T are multiplied by the unsigned contents of the addressed data-memory location, and the result is placed in the specified accumulator. The MACSU instruction performs a signed/unsigned multiplication and addition. The unsigned contents of one data-memory location are multiplied by the signed contents of another data-memory location, and the result is added to the accumulator. This operation allows operands greater than 16 bits to be broken down into 16-bit words and then processed separately to generate products that are larger than 32 bits. The square/add (SQURA) and square/subtract (SQURS) instructions pass the same data value to both inputs of the multiplier to square the value. The result is added to (SQURA) or subtracted from (SQURS) the accumulator at the adder level. The SQUR instruction squares a data-memory value or the contents of accumulator A.

4.5.3

MAC and MAS Saturation Upon Multiplication

When saturate-on-multiply is set (SMUL = 1), the MAC instruction is equivalent to MPY + ADD when OVM = 1. The effect is that the multiplication, 8000h 8000h, is saturated to 7FFF FFFFh in fractional mode before performing the subsequent addition (MAC) or subtraction (MAS).

When saturate-on-multiply is not set (SMUL = 0), only the end results of MAC and MAS are saturated. When OVM = 1 and FRCT = 1, the SMUL bit in PMST determines whether or not the result of a multiplication is saturated before the accumulation is performed in MAC and MAS instructions. This feature allows the MAC and MAS operations to be consistent with the MAC and MAS basic operation defined in ETSI GSM specifications (GSM specifications 6.06, 6.10, and 6.53).

Central Processing Unit

4-25

Compare, Select, and Store Unit (CSSU)

4.6 Compare, Select, and Store Unit (CSSU)

The compare, select, and store unit (CSSU) is an application-specific hardware unit dedicated to add/compare/select (ACS) operations of the Viterbi operator. Figure 49 shows the CSSU, which is used with the ALU to perform fast ACS operations.

Figure 49. Compare, Select, and Store Unit (CSSU)

From accumulator A From accumulator B B A MUX From barrel shifter S COMP TRN TC CSSU MSW/LSW select 16

EB15 EB0

The CSSU allows the 54x to support various Viterbi butterfly algorithms used in equalizers and channel decoders. The add function of the Viterbi operator (see Figure 410) is performed by the ALU. This function consists of a double addition function (Met1 D1 and Met2 D2). Double addition is completed in one machine cycle if the ALU is configured for dual 16-bit mode by setting the C16 bit in ST1. With the ALU configured in dual 16-bit mode, all the long-word (32-bit) instructions become dual 16-bit arithmetic instructions.

"

"

T is connected to the ALU input (as a dual 16-bit operand) and is used as local storage in order to minimize memory access. Table 46 shows the instructions that perform dual 16-bit ALU operations.

4-26

Compare, Select, and Store Unit (CSSU)

Figure 410. Viterbi Operator

Old state D1 2J (Met1) D2 New state J (New_Met1) If (Met1 + D1) > (Met2 + D2) then New_Met1 = Met1 + D1 else New_Met1 = Met2 + D2 J + STNB/2 (New_Met2) (Old metrics) (New metrics)

2J + 1 (Met2)

Legend:

STNB Met D

Number of states Path metrics Branch metrics

Table 46. ALU Operations in Dual 16-Bit Mode

Instruction DADD Function (Dual 16-Bit Mode) Lmem, src [, dst] src(3116) + Lmem(3116) dst(3916) src(150) + Lmem(150) dst(150) Lmem(3116) + T dst(3916) Lmem(150) T dst(150) DADST Lmem, dst DRSUB Lmem, src DSADT Lmem, dst DSUB Lmem(3116) src(3116) src(3916) Lmem(150) src(150) src(150) Lmem(3116) T dst(3916) Lmem(150) + T dst(150) Lmem, src src(3116) Lmem(3116) src(3916) src(150) Lmem(150) src(150) Lmem(3116) T dst(3916) Lmem(150) T dst(150) DSUBT Lmem, dst
Legend:

Lmem src

dst x(nm)

Is stored to Long (32-bit) data-memory value Source accumulator (A or B) Destination accumulator (A or B) Read as bits n through m of x

Central Processing Unit

4-27

Compare, Select, and Store Unit (CSSU)

The CSSU implements the compare and select operation via the CMPS instruction, a comparator, and the 16-bit transition register (TRN). This operation compares two 16-bit parts of the specified accumulator and shifts the decision into bit 0 of TRN. This decision is also stored in the TC bit of ST0. Based on the decision, the corresponding 16-bit part of the accumulator is stored in data memory. Example 44 shows the compare and select operation executed by the CMPS instruction.

Example 44. CMPS Instruction Operation

CMPS B,*AR3 ;if (B(31-16)>B(15-0)) then ;B(31-16)->(*AR3); TRN<<1; 0->TRN(0); ;0->TC} ;else B(15-0)->(*AR3); TRN<<1; ;1->TRN(0); 1->TC;

TRN contains information of the path transition decisions to new states. This information can be used for a back-tracking routine that finds the optimal path, which results in decoding the code.

4-28

Exponent Encoder

4.7 Exponent Encoder

The exponent encoder is an application-specific hardware device dedicated to supporting the EXP instruction in a single cycle (see Figure 411). With the EXP instruction, the exponent value in the accumulator can be stored in T as a 2s-complement value within a 8 through 31 range. The exponent is defined as the number of leading redundant bits 8, which corresponds to the number of shifts required in the accumulator to eliminate nonsignificant sign bits. This operation results in a negative value when the accumulator value exceeds 32 bits.

Figure 411.Exponent Encoder

From accumulator A From accumulator B B A EXP encoder 6 To T register

The EXP and NORM instructions use the exponent encoder to normalize the accumulators contents efficiently. NORM supports shifting the accumulator value by the number of bits specified in T in a single cycle. A negative value in T produces a right shift of the accumulators contents, which normalizes any value beyond the 32-bit range of the accumulator. Example 45 demonstrates the normalization of accumulator A.

Example 45. Normalization of Accumulator A

;Normalize accumulator A EXP A ; (the number of leading bits 8)-> T. ST T, EXPONENT ; Store the exponent (T) into data ; memory NORM A ; Normalize accumulator A, (A)<<(T)

Central Processing Unit

4-29

Chapter 5

Data Addressing

The 54x offers seven basic addressing modes:

Immediate addressing uses the instruction to encode a fixed value. Absolute addressing uses the instruction to encode a fixed address. Accumulator addressing uses an accumulator to access a location in program memory as data. Direct addressing uses seven bits of the instruction to encode an offset relative to DP or to SP. The offset plus DP or SP determine the actual address in data memory. Indirect addressing uses the auxiliary registers to access memory. Memory-mapped register addressing modifies the memory-mapped registers without affecting either the current DP value or the current SP value. Stack addressing manages adding and removing items from the system stack.

Topic
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8

Page
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Accumulator Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Memory-Mapped Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Stack Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

5-1

Immediate Addressing

5.1 Immediate Addressing

In immediate addressing, the instruction syntax contains the specific value of the operand. Two types of values can be encoded in an instruction:

Short immediate values can be 3, 5, 8, or 9 bits in length. 16-bit immediate values are always 16 bits in length.

Immediate values can be encoded in 1-word or 2-word instructions. The 3-, 5-, 8-, or 9-bit values are encoded into 1-word instructions; 16-bit values are encoded into 2-word instructions. The length of the immediate value encoded in an instruction depends on the type of instruction used. Table 51 lists the 54x instructions that can encode immediate values in their instruction word(s). The table also gives the bit value that can be encoded in the instruction.

Table 51. Instructions That Allow Immediate Addressing

5-2

3- and 5-Bit Constants LD 8-Bit Constant FRAME LD 9-Bit Constant LD 16-Bit Constant ADD ORM RPT ADDM AND RPT RPTZ ST STM SUB XOR XORM ANDM BITF CMPM LD MAC OR

The syntax for immediate addressing uses a number sign (#) immediately preceding the value or symbol to indicate that it is an immediate value. For example, to load accumulator A with the value 80 in hexadecimal, you would write:
LD #80h, A

Figure 51 and Figure 52 use the RPT instruction to show how an immediate value is encoded in instructions that use immediate addressing. The opcode in the instruction is encoded in the high half of the instruction: bits 815 of a 1-word encoding; bits 015 of the high word of a 2-word encoding. The value of the constant is in the rest of the space.

Immediate Addressing

Figure 51. RPT Instruction With Short-Immediate Addressing

15 1 instruction word 1 14 1 13 1 12 0 11 1 10 1 9 0 8 0 7 6 5 4 3 2 1 0

8-bit constant

Figure 52. RPT Instruction With 16-Bit-Immediate Addressing

15 1 2 instruction words 16-bit constant 14 1 13 1 12 1 11 0 10 0 9 0 8 0 7 1 6 1 5 1 4 1 3 0 2 0 1 0 0 0

Data Addressing

5-3

Absolute Addressing

5.2 Absolute Addressing

There are four types of absolute addressing:

dmad addressing:

J J J J J J J J J J J

MVDK Smem, dmad MVDM dmad, MMR MVKD dmad, Smem MVMD MMR, dmad

pmad addressing:
FIRS Xmem, Ymem, pmad MACD Smem, pmad, src MACP Smem, pmad, src MVDP Smem, pmad MVPD pmad, Smem

PA addressing:
PORTR PA, Smem PORTW Smem, PA

*(lk) addressing is used with all instructions that support the use of a single data-memory (Smem) operand.

Absolute addresses are always encoded with a length of 16 bits, so instructions that encode absolute addresses are always at least two words in length.

5.2.1

dmad Addressing
Data-memory address (dmad) addressing uses a specific value to specify an address in data space. The syntax for dmad addressing uses a symbol or a number to specify an address in data space. For example, to copy the value contained at the address labeled SAMPLE in data space to the memory location in data space pointed to by AR5, you would write:
MVKD SAMPLE, *AR5

In this example, the address referenced by SAMPLE is the dmad value.

5-4

Absolute Addressing

5.2.2

pmad Addressing
Program-memory address (pmad) addressing uses a specific value to specify an address in program space. The syntax for pmad addressing uses a symbol or a number to specify an address in program space. For example, to copy a word in the programmemory location labeled TABLE to a data-memory location specified by AR7, you would write:
MVPD TABLE, *AR7

In this example, the address referenced by TABLE is the pmad value.

5.2.3

PA Addressing
Port address (PA) addressing uses a specific value to specify an external I/O port address. The syntax for PA addressing uses a symbol or a number to specify the port address. For example, to copy a value from the I/O port at port address FIFO to a data-memory location pointed to by AR5, you would write:
PORTR FIFO, *AR5

In the example, FIFO refers to the port address.

5.2.4

*(lk) Addressing
*(lk) addressing uses a specific value to specify an address in data space. The syntax for *(lk) addressing uses a symbol or a number to specify an address in data space. For example, to load accumulator A with the value contained in address BUFFER in data space, you would write:
LD *(BUFFER),A

The syntax for *(lk) addressing allows all instructions that use Smem addressing to access any location in data space without changing the DP or initializing an AR. When this form of absolute addressing is used, the length of the instruction is extended by one word. For example, a 1-word instruction would become a 2-word instruction or a 2-word instruction would become a 3-word instruction. The addition of one word to an instruction affects its usability in delay slots. Note: Instructions using the *(lk) form of absolute addressing cannot be used with repeat single instructions (RPT, RPTZ).

Data Addressing

5-5

Accumulator Addressing

5.3 Accumulator Addressing

Accumulator addressing uses the accumulator as an address. This addressing mode is used to address program memory as data. Two instructions allow you to use the accumulator as an address:

READA Smem WRITA Smem

READA transfers a word from a program-memory location specified by accumulator A to a data-memory location specified by the single data-memory (Smem) operand of the instruction. WRITA transfers a word from a data-memory location specified by the Smem operand of the instruction to a program-memory location specified by accumulator A. In repeat mode, an increment may be used to increment accumulator A. Note: In most 54x devices, the program-memory location is specified by the lower 16 bits of accumulator A. However, because the 548, 549, and 5410, have 23 address lines (20 address lines in the 5402, and 18 in the 5420), the program-memory location in these devices is specified by the lower 23 bits of accumulator A. See section 3.2.5, Extended Program Memory, on page 3-20.

5-6

Direct Addressing

5.4 Direct Addressing

In direct addressing mode, the instruction contains the lower seven bits of the data-memory address (dma). The 7-bit dma is an address offset that is combined with a base address, with the data-page pointer (DP), or with the stack pointer (SP) to form a 16-bit data-memory address. Using this form of addressing, you can access any of 128 locations in random order without changing the DP or the SP. Note: Direct addressing is not the only method of offset addressing. However, the advantage of this mode is that it encodes each instruction and address into a single word. Either DP or SP can be combined with the dma offset to generate the actual address. The compiler mode bit (CPL), located in status register ST1, selects which method is used to generate the address:

When CPL = 0, the dma field is concatenated with the 9-bit DP field to form the 16-bit data-memory address. When CPL = 1, the dma field is added (positive offset) to SP to form the 16-bit data-memory address.

The syntax for direct addressing uses a symbol or a number to specify the offset value. For example, to add the contents of the memory location SAMPLE to accumulator B, provided that the correct base address is in DP (CPL = 0) or SP (CPL = 1), you would write:
ADD SAMPLE, B

The lower seven bits of the address of SAMPLE are stored in the instruction word. Figure 53 shows the opcode format for instructions that use direct addressing. Table 52 describes the bits of the direct-addressing instruction. Figure 54 illustrates how the 16-bit data address is formed.

Data Addressing

5-7

Direct Addressing

Figure 53. Direct-Addressing Instruction Format

15 8 Opcode 7 I=0 6 0 dma

Table 52. Direct-Addressing Instruction Bit Summary

Bit 15 8 7 60 Name Opcode I dma Function This eight-bit field contains the operation code for the instruction. I = 0, the addressing mode used by the instruction is the direct addressing mode. This seven-bit field contains the data-memory address offset for the instruction.

Figure 54. Direct Addressing Block Diagram

DP(9) 7 LSBs from IR (dma) SP(16) DAB(16) (read) CPL CPL 0 1 DAGEN EA = DP : offset(IR) EA = SP + offset(IR) EAB(16) (write) or CAB(16) (32-bit read)

Data bus DB(16)

Data bus EB(16)

Legend: EA IR Effective address Instruction register

5-8

Direct Addressing

5.4.1

DP-Referenced Direct Addressing

In DP-referenced direct addressing, the 7-bit dma in the instruction register is concatenated with the 9-bit DP to form the address. Figure 55 shows how the two values make up the resulting address.

Figure 55. DP-Referenced Direct Address

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value from the DP Value from the IR (dma)

DP-referenced direct addressing divides memory into 512 pages, because the DPs range is from 0 to 511 (29 1). Each page has 128 addressable locations, because the dma ranges from 0 to 127 (27 1). In other words, the DP points to one of 512 possible 128-word data-memory pages; the dma points to the specific location within that page. The only difference between an access to location 0 on page 1 and to location 0 on page 2 is the value of the DP. The DP is loaded by the LD instruction.

5.4.2

SP-Referenced Direct Addressing

In SP-referenced direct addressing, the 7-bit dma in the instruction register is added as a positive offset to the SP to form the effective 16-bit data-memory address. Figure 56 shows how the two values combine to form the resulting address.

Figure 56. SP-Referenced Direct Address

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value from the SP 15 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 5 4 3 2 1 0

Value from the IR (dma)

15

14

13

12

11

10

Effective memory address

The SP points to any address in memory. The dma points to the specific location on the page, allowing you to access a contiguous 128-word (27 1) block in memory from any base address. SP can also add or remove items from the stack. See section 5.7, Stack Addressing, for more information.
Data Addressing
5-9

Indirect Addressing

5.5 Indirect Addressing

In indirect addressing, any location in the 64K-word data space can be accessed via a 16-bit address contained in an auxiliary register. The 54x has eight 16-bit auxiliary registers (AR0AR7). Indirect addressing is used mainly when there is a need to step through sequential locations in memory in fixedsize steps. When memory is addressed with indirect addressing, the auxiliary register and the address can be optionally modified by a decrement, an increment, an offset, or an index. Special modes offer circular and bit-reversed addressing. A circular buffer size register (BK) is used with circular addressing. The AR0 register is used for indexed and bit-reversed addressing modes in addition to being used to point to memory as the other auxiliary registers do. Indirect addressing is flexible enough not only to read or write a single 16-bit data operand from memory with one instruction, but also to access two datamemory locations with one instruction. Accesses of two data-memory locations include reads of two independent memory locations, reads and writes of two consecutive memory locations, and a read of one memory location combined with a write to a memory location.

5.5.1

Single-Operand Addressing
Figure 57 shows the indirect-addressing instruction format for a single datamemory (Smem) operand. Table 53 describes the bits of the instruction.

Figure 57. Indirect-Addressing Instruction Format for a Single Data-Memory Operand

158 Opcode 7 I=1 63 MOD 20 ARF

Table 53. Indirect-Addressing Instruction Bit Summary Single Data-Memory Operand

Bit 15 8 7 63 Name Opcode I MOD Function This eight-bit field contains the operation code for the instruction. I = 1, the addressing mode used by the instruction is the indirect addressing mode. This 4-bit modification field defines the type of indirect addressing. section 5.5.3, SingleOperand Address Modifications, on page 5-13, describes the 16 ways to specify addressing types with the MOD field.

5-10

Indirect Addressing

Table 53. Indirect-Addressing Instruction Bit Summary Single Data-Memory Operand (Continued)
Bit 20 Name ARF Function This 3-bit auxiliary register field defines the auxiliary register used for addressing. ARF depends on the compatibility mode bit (CMPT) in status register ST1: CMPT = 0 Standard mode. In standard mode, ARF always specifies the auxiliary register, regardless of the value in ARP. ARP is not updated. ARP must always be set to zero when the DSP is in this mode. CMPT = 1 Compatibility mode. In compatibility mode, ARP selects the auxiliary register if ARF = 0. Otherwise, ARF selects the auxiliary register and the ARF value is loaded into ARP when the access is completed. *AR0 in the assembly instruction indicates the auxiliary register selected by ARP in compatibility mode.

Note: In some cases, two data operands can be fetched at once. This requires a different instruction format. section 5.5.4, Dual-Operand Address Modifications, on page 5-19, describes this format.

5.5.2

ARAU and Address-Generation Operation

Two auxiliary register arithmetic units (ARAU0 and ARAU1) operate on the contents of the auxiliary registers. The ARAUs perform unsigned, 16-bit auxiliary register arithmetic operations. Some addresses can be obtained by premodifying the auxiliary register. The auxiliary registers can be:

Loaded with an immediate value using the STM instruction Loaded via the data bus by writing to the memory-mapped auxiliary registers Modified by the indirect addressing field of any instruction that supports indirect addressing Modified by the modify auxiliary register (MAR) instruction Used as loop counters using the BANZ[D] instruction
Data Addressing
5-11

Indirect Addressing

Note: Typically, STM or MVDK is used to load auxiliary registers. Both of these instructions allow the next instruction to use the new value in the register. Other instructions that load a new value into an AR produce a pipeline latency. For further information on the pipeline and possible pipeline conflicts, see Chapter, 7 Pipeline. Figure 58 shows the ARAUs used to generate an address in the indirect addressing mode using a single data-memory operand. As the figure shows, the main components used for address generation in indirect addressing are the auxiliary register arithmetic units (ARAU0 and ARAU1) and the auxiliary registers (AR0AR7).

Figure 58. Indirect Addressing Block Diagram for a Single Data-Memory Operand

AR0 BK lk 1 ARP(3) ARAU0 AR0(16) index AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) BK(16) ARAU1 EAB(16) (write) or CAB(16) (32-bit read)

+/ % 0 B AR0 BK 1 DAB(16) (read)

+/ %

Data bus DB(16)

Data bus EB(16)

5-12

Indirect Addressing

5.5.3

Single-Operand Address Modifications

You can modify the addresses you use in instructions before or after they are accessed, or you can leave them unchanged. You can modify them by incrementing or decrementing the address by 1, adding a 16-bit offset, or indexing with the value in AR0. These three types of action combined with taking the action either before or after the access, plus the ways of leaving the address unchanged make a total of 16 addressing types, each assigned to a value of MOD, the 4-bit modification field in the encoding of an instruction using indirect addressing. Table 54 lists the types of single data-memory operand addressing, along with the value of MOD, the assembler syntax, and the function for each type.

Table 54. Indirect Addressing Types With a Single Data-Memory Operand

MOD Field 0000 (0) 0001 (1) 0010 (2) 0011 (3) 0100 (4) 0101 (5) 0110 (6) 0111 (7) 1000 (8) 1001 (9) Operand Syntax *ARx *ARx *ARx+ *+ARx *ARx 0B *ARx 0 *ARx + 0 *ARx + 0B *ARx% *ARx 0% Function addr = ARx addr = ARx ARx = ARx 1 addr = ARx ARx = ARx + 1 addr = ARx + 1 ARx = ARx + 1 addr = ARx ARx = B(ARx AR0) addr = ARx ARx = ARx AR0 addr = ARx ARx = ARx + AR0 addr = ARx ARx = B(ARx + AR0) addr = ARx ARx = circ(ARx 1) addr = ARx ARx = circ(ARx AR0) Description ARx contains the data-memory address. After access, the address in ARx is decremented. After access, the address in ARx is incremented. The address in ARx is incremented before its use.# After access, AR0 is subtracted from ARx with reverse carry (rc) propagation. After access, AR0 is subtracted from ARx.

After access, AR0 is added to ARx.

After access, AR0 is added to ARx with reverse carry (rc) propagation. After access, the address in ARx is decremented with circular addressing. After access, AR0 is subtracted from ARx with circular addressing.

ARx is used as the data-memory address unless otherwise specified. Increment/decrement value is 1 for 16-bit word access and 2 for 32-bit word access. This mode is not allowed in memory-mapped register addressing. This mode is discussed in greater detail in section 5.2.4, *(lk) Addressing, on page 5-5. # This mode is allowed only for write accesses.

Data Addressing

5-13

Indirect Addressing

Table 54. Indirect Addressing Types With a Single Data-Memory Operand (Continued)
MOD Field 1010 (10) 1011 (11) 1100 (12) 1101 (13) Operand Syntax *ARx+% *ARx + 0% *ARx(lk) *+ARx(lk) Function addr = ARx ARx = circ(ARx + 1) addr = ARx ARx = circ(ARx + AR0) addr = ARx + lk ARx = ARx addr = ARx + lk ARx = ARx + lk addr = circ(ARx + lk) ARx = circ(ARx + lk) addr = lk Description After access, the address in ARx is incremented with circular addressing. After access, AR0 is added to ARx with circular addressing. The sum of ARx and the 16-bit long offset (lk) is used as the data-memory address. ARx is not updated. The address in ARx is incremented before its use and added to the signed 16-bit long offset (lk). It is then used as the data-memory address. The address in ARx is incremented before its use and added to a signed 16-bit long offset (lk) with circular addressing. It is then used as the data-memory address. An unsigned 16-bit long offset (lk) is used as the absolute address of data memory (absolute addressing).

1110 (14)

*+ARx(lk)%

1111 (15)

*(lk)

ARx is used as the data-memory address unless otherwise specified. Increment/decrement value is 1 for 16-bit word access and 2 for 32-bit word access. This mode is not allowed in memory-mapped register addressing. This mode is discussed in greater detail in section 5.2.4, *(lk) Addressing, on page 5-5. # This mode is allowed only for write accesses.

5.5.3.1

Increment/Decrement Address Modifications (MOD = 0, 1, 2, or 3)

While an AR is being used, you can modify the AR by incrementing or decrementing its value. The syntaxes for using the AR without modification, postdecrementing the AR by 1, postincrementing the AR by 1, and preincrementing the AR by 1 are shown in Table 54 for MOD = 0, 1, 2, and 3, respectively. Preincrementing (*+ARx) is supported only in instructions that access operands in a write operation.

5.5.3.2

Offset Address Modifications (MOD = 12 or 13)

Offset addressing is a type of indirect addressing in which a predetermined offset, or step size, is added to the contents of an auxiliary register. There are two options for offset addressing. In both cases, a 16-bit long offset, which is part of the instruction, is added to the value in the auxiliary register, and the result is used to address a location in data memory. In the first case, the auxiliary register is not updated. In the second case, the auxiliary register is updated with the new address.

5-14

Indirect Addressing

This type of addressing is useful in accessing a specific element of an array or structure, especially when the auxiliary register is not updated. When the auxiliary register is updated, this type of addressing is especially useful for stepping through an array in fixed-size steps. The syntaxes for offset addressing of an AR without and with updating the AR using offset addressing are shown in Table 54 in MOD 12 and 13, respectively. Notes: 1) Instructions using offset addressing cannot be repeated using the repeat single instruction. 2) Premodification by a 16-bit word offset (*+ARx(lk)) uses an extra cycle because the instruction code has two or three words. The last word is the offset.

5.5.3.3

Indexed Address Modifications (MOD = 5 or 6)

Indexed addressing is a type of indirect addressing in which the contents of AR0 are added to, or subtracted from, any other auxiliary register, ARx. Indexed addressing differs from offset addressing in that the index or step size can be determined during code execution. Because the index is determined during code execution, you can easily make adjustments to the step size. Indexed addressing also offers an advantage over offset addressing: it does not require an additional word for the instruction. The syntaxes for subtracting AR0 from ARx and for adding AR0 to ARx are shown in Table 54 for MOD = 5 and 6, respectively.

5.5.3.4

Circular Address Modifications (MOD = 8, 9, 10, 11, or 14)

Many algorithms, such as convolution, correlation, and FIR filters, require the implementation of a circular buffer in memory. In these algorithms, a circular buffer is a sliding window containing the most recent data. As new data comes in, the buffer overwrites the oldest data. The key to the implementation of a circular buffer is the implementation of circular addressing.

Data Addressing

5-15

Indirect Addressing

The circular-buffer size register (BK) specifies the size of the circular buffer. A circular buffer of size R must start on a N-bit boundary (that is, the N LSBs of the base address of the circular buffer must be 0), where N is the smallest integer that satisfies 2N > R. The value R must be loaded into BK. For example, a 31-word circular buffer must start at an address whose five LSBs are 0 (that is, XXXX XXXX XXX0 00002), and the value 31 must be loaded into BK. As a second example, a 32-word circular buffer must start at an address whose six LSBs are 0 (that is, XXXX XXXX XX00 00002), and the value 32 must be loaded into BK. In some applications, however, it may be possible to use bitreversed addressing to place a 2N buffer on a 2N boundary and offer the effect of circular addressing. The effective base address (EFB) of the circular buffer is determined by zeroing the N LSBs of a user-selected auxiliary register (ARx). The end of buffer address (EOB) of the circular buffer is determined by replacing the N LSBs of ARx with the N LSBs of BK. The index of the circular buffer is simply the N LSBs of ARx and the step is the quantity being added to or subtracted from the auxiliary register. Follow these three rules when you use circular addressing:

Place the first (lowest) address of the circular buffer on a 2N boundary where 2N is larger than the circular buffer size. Use a step less than or equal to the circular buffer size. The first time the circular queue is addressed, the auxiliary register must point to an element in the circular queue.

The algorithm for circular addressing is as follows: If 0 index + step BK: index = index + step. Else if index + step BK: index = index + step BK. Else if index + step 0: index = index + step + BK. Circular addressing can be used for single data-memory or dual data-memory operands. When BK is zero, the circular modifier results in no circular address modification. This is especially useful when a dual operand must perform an address modification equivalent to ARx+0. Figure 59 illustrates the relationships among BK, the auxiliary register (ARx), the bottom of the circular buffer, the top of the circular buffer, and the index into the circular buffer. Figure 510 shows how the circular buffer is implemented and illustrates the relationship between the generated values and the elements in the circular buffer.
5-16

t w t

Indirect Addressing

Figure 59. Circular Addressing Block Diagram

First 1 at location N1 15 ARx H ... H N N1 L ... L 0 BK 15 0 ... 0 N N1 BL ... 0 BL

15 EOB + 1 15 Index N N1 L ... L 0 0 ... 0 H ... H

N1 BL ...

0 BL

Circular addressing algorithm logic New index 15 New ARx N

15 EFB H ... H

N1 0 ... 0

Base (low address) 0 ... 0 L ... L

Legend: EFB H L L BL Effective base address High-order bits Low-order bits New low-order bits Low-order bit of circular buffer size register

N1 L ...

0 L

H ... H

Figure 510. Circular Buffer Implementation

Address 15 Effective base H N H N1 0 0 0 Data Top of circular buffer Element 0 Element 1 15 ARx H N H N1 L 0 L Element (n LSBs of ARx)

15 H

N H

N1 LSBs BK

Last element Last element +1

Data Addressing

5-17

Indirect Addressing

Circular addressing typically uses a decrement or an increment by one (MOD = 8 and 10) or a decrement or an increment by an index (MOD = 9 and 11). Premodification by a 16-bit word offset (*+ARx(lk)%) requires an extra code word so that the instruction code has two or three words. The last word is the offset. An instruction using indirect-offset addressing cannot be repeated using a single repeat operation. The syntaxes for each of the five types of circular addressing are shown in Table 54 for MOD = 8, 9, 10, 11, and 14.

5.5.3.5

Bit-Reversed Address Modifications (MOD = 4 or 7)

Bit-reversed addressing enhances execution speed and program memory for FFT algorithms that use a variety of radixes. In this addressing mode, AR0 specifies one half of the size of the FFT. The value contained in AR0 must be equal to 2N1, where N is an integer, and the FFT size is 2N. An auxiliary register points to the physical location of a data value. When you add AR0 to the auxiliary register using bit-reversed addressing, the address is generated in a bit-reversed fashion, with the carry bit propagating from left to right, instead of the normal right to left. The syntaxes for each of the two bit-reversed addressing modes are shown in Table 54 for MOD 4 and 7, respectively. Assume that the auxiliary registers are eight bits long, that AR2 represents the base address of the data in memory (0110 00002), and that AR0 contains the value 0000 10002. Example 51 shows a sequence of modifications of AR2 and the resulting values of AR2.

Example 51. Sequence of Auxiliary Registers Modifications in Bit-Reversed Addressing

*AR2+0B *AR2+0B *AR2+0B *AR2+0B *AR2+0B *AR2+0B *AR2+0B *AR2+0B ;AR2 ,AR2 ;AR2 ;AR2 ;AR2 ;AR2 ;AR2 ;AR2 = = = = = = = = 0110 0110 0110 0110 0110 0110 0110 0110 0000 1000 0100 1100 0010 1010 0110 1110 (0th (1st (2nd (3rd (4th (5th (6th (7th value) value) value) value) value) value) value) value)

Table 55 shows the relationship of the bit pattern of the index steps and the four LSBs of AR2, which contain the bit-reversed address. See the TMS320C54x DSP Reference Set, Volume 4: Applications Guide for an application of the bit-reversed addressing mode.
5-18

Indirect Addressing

Table 55. Bit-Reversed Addresses

Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Pattern 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit-Reversed Pattern 0000 1000 0100 1100 0010 1010 0110 1110 0001 1001 0101 1101 0011 1011 0111 1111 Bit-Reversed Step 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15

5.5.4

Dual-Operand Address Modifications

Dual data-memory operand addressing is used for instructions that perform two reads or a single read and a parallel store (indicated by two vertical bars, ||) at the same time. These instructions are all one word long and operate in indirect addressing mode only. Two data-memory operands are represented by Xmem and Ymem:

Xmem is a read operand with access through the D bus. Store instructions, for example STH and STL with shift operation, change Xmem to a write operand. Ymem is used as a read operand in instructions with dual reads (accessed through the C bus) or as a write operand in instructions with a parallel store (accessed through the E bus).

If the source operand and the destination operand point to the same location, in instructions with a parallel store (for example, ST||LD), the source is read before writing to the destination. If a dual-operand instruction (for example, ADD) points to the same auxiliary register with different addressing modes specified for both operands, the mode defined by the Xmod field is used for addressing.
Data Addressing
5-19

Indirect Addressing

Figure 511 shows the indirect-addressing instruction format for a dual datamemory operand. Table 56 describes the bits of the instruction. Because only two bits are available for selecting each auxiliary register in this mode, only four of the auxiliary registers can be used, AR2 AR5. Table 57 shows which Xar or Yar value selects which auxiliary registers.

Figure 511.Indirect-Addressing Instruction Format for Dual Data-Memory Operands

158 Opcode 7 6 5 Xar 4 3 2 1 Yar 0 Xmod Ymod

Table 56. Indirect-Addressing Instruction Bit Summary Dual Data-Memory Operands

Bit 15 8 76 54 32 10 Name Opcode Xmod Xar Ymod Yar Function This eight-bit field contains the operation code for the instruction. This 2-bit field defines the type of indirect addressing mode used for accessing the Xmem operand. The 2-bit Xmem auxiliary register selection field defines the auxiliary register that contains the address of Xmem. This 2-bit field defines the type of indirect addressing mode used for accessing the Ymem operand. The 2-bit Ymem auxiliary register selection field defines the auxiliary register that contains the address of Ymem.

Table 57. Auxiliary Registers Selected by Xar and Yar Field of Instruction

Figure 512 shows how an address is generated using dual data-memory operand addressing. Dual data-memory operand addressing uses four auxiliary registers (AR2AR5). The ARAUs, together with these registers, provide the capability to access two operands in a single cycle.
5-20

Xar or Yar Field 00 01 10 11 Auxiliary Register AR2 AR3 AR4 AR5

Indirect Addressing

Figure 512. Indirect Addressing Block Diagram for Dual Data-Memory Operands

AR0 BK lk 1 ARP(3) ARAU0 AR0(16) index AR2(16) AR3(16) AR4(16) AR5(16) ARAU1 EAB(16) (write) or CAB(16) (32-bit read) +/ % 0 AR0 BK 1 DAB(16) (read)

BK(16)

+/ %

Data bus DB(16)

Data bus EB(16)

Table 58 lists the types of dual data-memory operand addressing, along with the value of the modification field (either Xmod or Ymod), the assembler syntax, and the function for each type.

Table 58. Indirect Addressing Types With Dual Data-Memory Operands

Xmod or Ymod Field 00 (0) 01 (1) 10 (2) 11 (3) Operand Syntax *ARx Function Description addr = ARx ARx is the data-memory address. *ARx addr = ARx ARx = ARx 1 After access, the address in ARx is decremented. *ARx+ addr = ARx ARx = ARx + 1 After access, the address in ARx is incremented. After access, AR0 is added to ARx using circular addressing. *ARx+0% addr = ARx ARx = circ(ARx + AR0)
ARx is used as the data-memory address unless otherwise specified. The size of the circular buffer is specified in circular-buffer size register (BK)

Data Addressing

5-21

Indirect Addressing

In each case, the content of the auxiliary register is used as the data-memory operand. After using the address in the auxiliary register, the ARAUs perform the specified mathematical operation. By disabling circular modifications, it is possible to perform indexed addressing or the equivalent of *ARx+0. Clearing the BK to 0 disables circular modification. In instructions that perform dual-operand reads, if the auxiliary register specified by the Yar field accesses one of the memory-mapped registers, the value read will not represent the contents of the register.

See the TMS320C54x DSP Reference Set, Volume 4: Applications Guide for examples of dual-operand indirect addressing.

5.5.4.1

Dual-Operand Increment/Decrement Address Modifications (Xmod or Ymod = 0, 1, or 2)

You can modify the AR by incrementing or decrementing its value. When Xmod or Ymod = 0, ARx is used as the data-memory address with no incrementing or decrementing. When Xmod or Ymod = 1, ARx is decremented after the access is made. When Xmod or Ymod = 2, ARx is incremented after the access is made.

5.5.4.2

Dual-Operand Indexed Address Modifications (Xmod or Ymod = 3 and BK = 0)

When Xmod or Ymod = 3 and BK = 0, AR0 is added to ARx after each access. Otherwise, dual-operand indexed addressing is exactly as described in section 5.5.3.3 on page 5-15.

5.5.4.3

Dual-Operand Circular Address Modifications (Xmod or Ymod = 3 and BK

When Xmod or Ymod = 3 and BK 0, AR0 is added to ARx using circular addressing after each access. Otherwise, dual-operand circular addressing is exactly as described in section 5.5.3.4 on page 5-15.

 0)

5.5.4.4

Single-Operand Instructions That Use the Dual-Operand Format

Some instructions with only one data-memory operand use dual data-memory operand addressing so that they fit in a single word for single-cycle execution. In these instructions, only Xmem is available and the Xmod and Xar fields define the addressing mode for the operand. Four single-operand instructions can be executed in a single cycle:

5-22

BIT Xmem, BITC SACCD src, Xmem, cond SRCCD Xmem, cond STRCD Xmem, cond

Indirect Addressing

Five instructions with optional shift also support this type of addressing for single-word, single-cycle execution:

5.5.5

ADD Xmem, SHFT, src LD Xmem, SHFT, dst STH src, SHFT, Xmem STL src, SHFT, Xmem SUB Xmem, SHFT, src

TMS320C2x/C20x/C24x/C5x Compatibility (ARP) Mode

ARP can be used in indirect addressing. This allows the AR to be defined by ARP to ease code translation from a C2x/C20x/C24x/C5x device. With CMPT = 1 and ARF = 0, ARP is used to determine which AR is used to address memory. Figure 513 shows how the ARP indexes the auxiliary registers. In using ARP, the 54x differs from the C5x in that when the 54x uses the AR pointed to by ARP, the 54x does not update the ARP with the same instruction. Table 59 shows the assembler syntax for the C2x/C20x/C24x/C5x compared to the 54x.

Figure 513. How ARP Indexes the Auxiliary Registers

AR0(16) index AR1(16) AR2(16) AR3(16) ARP AR4(16) AR5(16) AR6(16) AR7(16) BK(16)

Table 59. Assembler Syntax Comparison for TMS320C2x/C20x/C24x/C5x and 54x

Syntax for C2x/C20x/C24x/C5x * Syntax for 54x *AR0 Syntax for C2x/C20x/C24x/C5x *0 Syntax for 54x *AR0 0 * *AR0 *0+ *AR0 + 0 *+ *AR0+ *BR0 *AR0 0B *BR0+ *AR0 + 0B

Data Addressing

5-23

Indirect Addressing

Figure 514 shows the indirect-addressing instruction format for the ARP mode. Table 510 describes the bits of the ARP-mode instruction.

Figure 514. Indirect-Addressing Instruction Format for Compatibility Mode

158 Opcode 7 I=1 63 MOD 20 ARF = 000

Table 510. Indirect-Addressing Instruction Bit Summary Compatibility Mode

Bit 15 8 7 63 Name Opcode I MOD Function This eight-bit field contains the operation code for the instruction. I = 1, the addressing mode used by the instruction is the indirect addressing mode. This 4-bit modification field defines the type of indirect addressing. section 5.5.3, SingleOperand Address Modifications, on page 5-13, describes the 16 ways to specify addressing types with the MOD field. This 3-bit auxiliary register field defines the auxiliary register used for addressing. ARF depends on the compatibility mode bit (CMPT) in status register ST1: CMPT = 0 Standard mode. In standard mode, ARF always specifies the auxiliary register, regardless of the value in ARP. ARP is not updated. ARP must always be set to 0 when the DSP is in this mode. CMPT = 1 Compatibility mode. In compatibility mode, ARP selects the auxiliary register if ARF = 0. Otherwise, ARF selects the auxiliary register and the ARF value is loaded into ARP when the access is completed. *AR0 in the assembly instruction indicates the auxiliary register selected by ARP in compatibility mode.

20

ARF

Note: ARP must always be set to 0 when the DSP is in standard mode (CMPT = 0). At reset, both ARP and CMPT are set to 0 automatically.

5-24

Memory-Mapped Register Addressing

5.6 Memory-Mapped Register Addressing

Memory-mapped register addressing is used to modify the memory-mapped registers without affecting either the current data-page pointer (DP) value or the current stack-pointer (SP) value. Because DP and SP do not need to be modified in this mode, the overhead for writing to a register is minimal. Memory-mapped register addressing works for both direct and indirect addressing. Figure 515 shows how memory-mapped addresses are generated. Addresses are generated by:

Forcing the nine most significant bits (MSBs) of data-memory address to 0, regardless of the current value of DP or SP when direct addressing is used Using the seven LSBs of the current auxiliary register value when indirect addressing is used

Note: In indirect addressing, the nine MSBs of the auxiliary register are forced to 0 after the operation. For example, if AR1 is used to point to a memory-mapped register in memorymapped register addressing mode and it contains a value of FF25h, then AR1 points to the timer period register (PRD), since the seven LSBs of AR1 are 25h and the address of the PRD is 0025h. After execution, the value remaining in AR1 is 0025h.

Figure 515. Memory-Mapped Register Addressing Block Diagram

All bits 0s 9 16 16-bit memory-mapped register address

7 LSBs from instruction register (IR) or current auxiliary register

Note: In addition to registers, any scratch-pad RAM located on data page 0 can be modified by using memory-mapped register addressing.

Data Addressing

5-25

Memory-Mapped Register Addressing

Only eight instructions can use memory-mapped register addressing:

LDM MMR, dst MVDM dmad, MMR MVMD MMR, dmad MVMM MMRx, MMRy POPM MMR PSHM MMR STLM src, MMR STM #lk, MMR

Note: The following indirect addressing modes are not allowed for memorymapped register addressing:

*ARx(lk) *+ARx(lk) *+ARx(lk)% *(lk)

In these cases, the assembler issues a warning.

5-26

Stack Addressing

5.7 Stack Addressing

The system stack is used to automatically store the program counter during interrupts and subroutines. It can also be used at your discretion to store additional items of context or to pass data values. The stack is filled from the highest to the lowest memory address. The processor uses a 16-bit memorymapped register, the stack pointer (SP), to address the stack. SP always points to the last element stored onto the stack. Four instructions access the stack using the stack addressing mode:

PSHD pushes a data-memory value onto the stack. PSHM pushes a memory-mapped register onto the stack. POPD pops a data-memory value from the stack. POPM pops a memory-mapped register from the stack.

A push predecrements and a pop postincrements the address in the SP. Figure 516 shows an example of the stack and SP before and after a push of X2 into the stack (PSHD X2).

Figure 516. Stack and Stack Pointer Before and After a Push Operation
Stack and SP before operation SP 0011 0001 0010 0011 0100 0101 0110 X1 Stack and SP after operation SP 0010 0001 0010 0011 0100 0101 0110 X2 X1

Other operations also affect the stack and the stack pointer. The stack is used during interrupts and subroutines to save and restore the PC contents. When a subroutine is called or an interrupt occurs, the return address is automatically saved in the stack using a push operation. Instructions used for subroutine calls and interrupts are CALA[D], CALL[D], CC[D], INTR, and TRAP. When a subroutine returns, the return address is retrieved from the stack using a pop operation and loaded into the PC. Instructions used for returns from subroutines are RET[D], RETE[D], RETEF[D], and RC[D]. The FRAME instruction also affects the stack. This instruction adds a shortimmediate offset to the stack pointer. The stack is also used in SP-referenced direct addressing (see section 5.4.2, SP-Referenced Direct Addressing, on page 5-9).
Data Addressing
5-27

Data Types

5.8 Data Types

There are two basic data types for accessing memory in the 54x: 16-bit and 32-bit. Most instructions can access 16-bit data. Accessing 32-bit data, however, requires the use of the special instructions listed in Table 511.

Table 511. Instructions With 32-Bit Word Operands

Instruction DADD DADST DLD DRSUB DSADT DST DSUB DSUBT Description Double-precision add/dual 16-bit add to accumulator Double-precision load with T add/dual 16-bit load with T add/subtract Long-word load to accumulator Double-precision subtract/dual 16-bit subtract from long word Long load with T subtract/dual 16-bit load with T subtract/add Store accumulator in long word Double-precision subtract/dual 16-bit subtract from accumulator Long load with T subtract/dual 16-bit load with T subtract

For a 16-bit operand access, a 16-bit word is read from data memory through the D bus and written to data memory through the E bus. For a 32-bit operand access, both the C (for most-significant word) and the D (for least-significant word) buses are used for a read. However, because only the E bus is used for a write, the write operation (DST instruction) is executed in two cycles. With 32-bit accesses, the first word accessed is treated as the most-significant word (MSW), while the second word accessed is the least-significant word (LSW). If the first word accessed is at an even address, then the second word is at the next (higher) address. If the first word accessed is at an odd address, then the second word is at the previous (lower) address. Figure 517 shows this effect.

5-28

Data Types

Figure 517. Word Order in Memory

Accumulator MSW LSW

DST 1000h Write order when addr = 1000h

DST 1001h Write order when addr = 1001h

1000h 1001h

MSW LSW

1000h 1001h

LSW MSW

Data Addressing

5-29

Chapter 6 Figure 62

Program Memory Addressing

This chapter discusses how program-memory addresses are generated and which addresses are loaded into the program counter (PC). This chapter also describes the following program control operations that affect the value loaded in the PC:

Branches Calls Returns Conditional operations Repeats of an instruction or a block of instructions Hardware reset Interrupts

These operations can cause a nonsequential address to be loaded into PC. Section 7.1, Pipeline Operation, and section 7.2, Interrupts and the Pipeline, are helpful in understanding the operation of PC discontinuities. Power-down modes halt program execution.

Topic
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9

Page
Program-Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Repeating a Single Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Repeating a Block of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

6.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.11 Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50

6-1

Program-Memory Address Generation

6.1 Program-Memory Address Generation

Program memory contains code for applications, coefficient tables, and immediate operands. The 54x can address a total of 64K words of program memory using the program address bus (PAB). Table 61 shows devices that have additional program memory address lines that provide external access to as many as 128 64K-word pages.

6-2

Device Additional Address Lines 7 4 2 Provides External Access To: 548, 549, 5410 5402 5420 128 64K-Word Pages 16 64K-Word Pages 4 64K-Word Pages

Table 61. Devices With Additional Program Memory Address Lines

The program-address generation logic (PAGEN) generates the address used to access instructions, coefficient tables, 16-bit immediate operands, or other information stored in program memory, and puts this address on the PAB. PAGEN consists of five registers (see Figure 61):

Program counter (PC) Repeat counter (RC) Block-repeat counter (BRC) Block-repeat start address register (RSA) Block-repeat end address register (REA)

One additional register is used in the 548, 549, 5402, 5410, and 5420 to address extended memory: Program counter extension register (XPC)

Program-Memory Address Generation

Figure 61. Program-Address Generation Logic (PAGEN) Registers

PAGEN PC

Repeat registers
RC BRC RSA REA

54x devices fetch instructions by putting the value of the PC on the PAB and reading the appropriate location in memory. While the memory location is read, PC is incremented for the next fetch. If a program address discontinuity occurs (for example, a branch, a call, a return, an interrupt, or a block repeat), the appropriate address is loaded into the PC. The instruction addressed through the PAB is then loaded into the instruction register (IR). To improve the performance of certain instructions, the program address generation unit is also used to fetch operands from program memory. Operands are fetched from program memory when the device reads from or writes to a coefficient table or when it transfers data between program and data space. Some instructions, such as FIRS, MACD, and MACP, use the program bus to fetch a second multiplicand.

Program Memory Addressing

6-3

Program Counter (PC)

6.2 Program Counter (PC)

The PC is a 16-bit register that contains the internal or external programmemory address used when an instruction is fetched or when a 16-bit-immediate operand or coefficient table in program memory is accessed. To address program memory, the address in the PC is put onto the PAB. The PC can be loaded several ways. Table 62 shows what is loaded into the PC according to the code operation performed.

Table 62. Loading Addresses Into PC

6-4

Code Operation Reset Address Loaded to the PC PC is loaded with FF80h. Sequential execution Branch PC is loaded with PC + 1. PC is loaded with the 16-bit-immediate value directly following the branch instruction. Branch from accumulator PC is loaded with the lower 16-bit word of accumulator A or B. Block repeat loop PC is loaded with the repeat start address (RSA) when PC + 1 equals the repeat end address (REA) + 1, provided that BRAF = 1.

Subroutine call PC + 2 is pushed onto the stack, and PC is loaded with the 16-bit-immediate value directly following the call instruction mnemonic. The return instruction pops the top of the stack back into PC to return to the calling sequence of code. PC + 1 is pushed onto the stack, and PC is loaded with the lower 16-bit word of accumulator A or B. The return instruction pops the top of the stack back into PC to return to the calling sequence of code. PC is pushed onto the stack, and PC is loaded with the address of the appropriate trap vector. The return instruction pops the top of the stack back into PC to return to the interrupting sequence of code. Subroutine call from accumulator

Hardware interrupt, software interrupt, or trap

Program Counter (PC)

The XPC is a 7-bit register that selects the extended page of program memory for the 548, 549, 5402, 5410, and 5420. For more information about extended program memory in these devices, see section 3.2.5, Extended Program Memory, on page 3-20. The XPC can be loaded in several ways in conjunction with the loading of the PC. Table 63 lists operations that load XPC.

Table 63. Loading Addresses into XPC

Code Operation Reset Address Loaded to the PC PC is loaded with FF80h. XPC is loaded with 0h. Sequential execution Far branch PC is loaded with PC + 1. XPC is not automatically incremented. PC is loaded with bits 150 of the immediate value directly following the branch instruction. XPC is loaded bits 2316 of that value. Far branch from accumulator Far subroutine call PC is loaded with bits 150 of accumulator A or B. XPC is loaded with bits 2316 of accumulator A or B. PC + 2 is pushed onto the stack, XPC is pushed onto the stack, PC and XPC are loaded with bits 150 and bits 2316, respectively, of the immediate value specified by the call instruction. PC + 1 is pushed onto the stack, XPC is pushed onto the stack, and the PC and XPC are loaded with bits 150 and bits 2316, respectively, of accumulator A or B.

Far subroutine call from accumulator Far return The return instruction pops the top of the stack into XPC and pops the next value into the PC to return to the calling sequence of code.

Note: The XPC is not loaded by instructions other than those listed in Table 63.

Program Memory Addressing

6-5

Branches

6.3 Branches
Branches break the sequential flow of instructions by transferring control to another location in program memory. Therefore, branches affect the program address generated and stored in PC. The 54x performs both unconditional and conditional branches, and both of these types can be either nondelayed or delayed.

6.3.1

Unconditional Branches
An unconditional branch is always executed when it is encountered. During the execution, PC is loaded with the specified branch-to-program-memory address and execution of the new section of code begins at that address. The address loaded into PC comes from either the second word of the branch instruction or the lower 16 bits of an accumulator (accumulator A or accumulator B). By the time the branch instruction reaches the execute phase of the pipeline, the next two instruction words have already been fetched. How these two instruction words are handled depends in part on whether the branch is nondelayed or delayed:

Nondelayed: The two instruction words are flushed from the pipeline so that they are not executed, and then execution continues at the branchedto address. Delayed: The one 2-word instruction or two 1-word instructions following the branch instruction are executed. This allows you to avoid flushing the pipeline, which requires extra cycles.

Note: The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity (a branch, call, return, or software interrupt). Table 64 shows the unconditional branch instructions in the 54x and the number of cycles needed to execute these instructions (both nondelayed and delayed). Delayed instructions use two cycles fewer than the corresponding nondelayed instructions because they do not flush the pipeline.

6-6

Branches

Table 64. Unconditional Branch Instructions

6.3.2

Conditional Branches

Instruction B[D] Description Number of Cycles (Nondelayed / Delayed) 4/2 6/4 Load PC with the address specified by the instruction BACC[D] Load PC with the address specified by the low 16 bits of the designated accumulator

Conditional branches operate like unconditional branches, but they execute only when one or more user-specified conditions are met. The possible conditions are given in Table 613 on page 6-16. If all the conditions are met, PC is loaded with the second word of the branch instruction, which contains the address to branch to, and execution continues at this address. By the time the conditions have been tested, the two instruction words following the conditional branch instruction have already been fetched and are in the pipeline. How these two instruction words are handled depends in part on whether the branch is nondelayed or delayed:

Nondelayed: If all the conditions are met, these two instruction words are flushed from the pipeline so that they are not executed, and then execution continues at the branched-to address. If the conditions are not met, the two instruction words are executed instead of the branch. Delayed: The one 2-word instruction or two 1-word instructions following the branch instruction are executed. This allows you to avoid flushing the pipeline, which requires extra cycles. The conditions tested are not affected by the instructions following the delayed branch.

Note: The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity (a branch, call, return, or software interrupt). Table 65 shows the conditional branch instructions and the number of cycles needed to execute these instructions. Because conditional branches use conditions determined by the execution of the previous instructions, the conditional branch instruction, BC[D], requires one more cycle than an unconditional one.
Program Memory Addressing
6-7

Branches

Table 65. Conditional Branch Instructions

6.3.3

Far Branches (Available on 548/549/5402/5410/5420)

Table 66. Far Branch Instructions

6-8

Number of Cycles (Condition met / Not met) Delayed 3/3 Instruction BC[D] Description Nondelayed 5/3 Load PC with the address specified by the instruction if the condition specified by the instruction is met BANZ[D] Load PC with the address specified by the instruction if currently selected auxiliary register not equal to 0 (useful for loops) 4/2 2/2

To allow branches to extended memory, the 548, 549,5402, 5410, and 5420 include two far branch instructions:

FB[D] branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified by the the instruction. FBACC[D] branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified in the designated accumulator.

Table 66 shows the far branch instructions in the 548, 549, 5402, 5410, and 5420 (both nondelayed and delayed) and the number of cycles needed to execute these instructions. Delayed instructions use two cycles fewer than the corresponding nondelayed instructions.

Instruction FB[D] Description Number of Cycles (Nondelayed / Delayed) 4/2 6/4 Load the PC and the XPC with the address specified in the instruction Load the PC and the XPC with the address specified by the lower 23 bits of the designated accumulator FBACC[D]

Calls

6.4 Calls
Like branches, calls break the sequential flow of instructions by transferring control to some other location in program memory. However, unlike branches, this transfer is intended to be temporary. When a subroutine or function is called, the address of the next instruction following the call is saved in the stack. This address is used to return to the calling program and resume execution. The 54x performs both unconditional and conditional calls, and both of these types can be either nondelayed or delayed.

6.4.1

Unconditional Calls
An unconditional call is always executed when it is encountered. When the call is executed, the PC is loaded with the specified program-memory address and execution of the called routine begins at that address. The address loaded into PC can come from either the second word of the call instruction or the lower 16 bits of an accumulator (accumulator A or accumulator B). Before the PC is loaded, the return address is saved in the stack. After the subroutine or function is executed, a return instruction loads the PC with the return address from the stack, and execution resumes at the instruction following the call. By the time the unconditional call instruction reaches the execute phase of the pipeline, the next two instruction words have already been fetched. How these two instruction words are handled depends in part on whether the call is nondelayed or delayed:

Nondelayed: The two instruction words are flushed from the pipeline so that they are not executed, the return address is stored to the stack, and then execution continues at the beginning of the called function. Delayed: The one 2-word instruction or two 1-word instructions following the call instruction are executed. This allows you to avoid flushing the pipeline, which requires extra cycles.

Note: The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity (a branch, call, return, or software interrupt). Table 67 shows the unconditional call instructions in the 54x (both nondelayed and delayed) and the number of cycles needed to execute these instructions. Delayed instructions need two cycles fewer than the corresponding nondelayed instructions because they do not flush the pipeline.
Program Memory Addressing
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Calls

Table 67. Unconditional Call Instructions

6.4.2

Conditional Calls

6-10

Instruction CALL[D] Description Number of Cycles (Nondelayed / Delayed) 4/2 Places the return address on the stack and then loads the PC with the address specified by the instruction CALA[D] Places the return address on the stack and then loads the PC with the address specified in the designated accumulator 6/4

Conditional calls operate like unconditional calls, but they execute only when one or multiple conditions are met. The possible conditions are given in Table 613 on page 6-16. If all the conditions are met, the PC is loaded with the second word of the call instruction, which contains the starting address of the function to be called. Before branching to the called function, the processor stores the address of the instruction following the call instruction to the stack. The function must end with a return instruction, which takes the address off the stack and loads PC, allowing the processor to resume execution of the calling program. By the time the conditions of the conditional call instruction have been tested, the two instruction words following the call instruction have already been fetched in the pipeline. How these two instruction words are handled depends in part on whether the call is nondelayed or delayed:

Nondelayed: If all the conditions are met, these two instruction words are flushed from the pipeline so that they are not executed, and then execution continues at the beginning of the called function. If the conditions are not met, the two instructions are executed instead of the call. Delayed: The one 2-word instruction or two 1-word instructions following the call instruction are always executed. This allows you to avoid flushing the pipeline, which requires extra cycles. The conditions tested are not affected by the instructions following the delayed call. If the conditions are not met, the processor executes the two instruction words instead of the call.

Note: The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity (a branch, call, return, or software interrupt).

Calls

Table 68 shows the conditional call instruction and the number of cycles needed to execute this instruction. Because there is a wait cycle for conditions to become stable, the conditional call instruction, CC[D], requires one more cycle than the unconditional one.

Table 68. Conditional Call Instruction

6.4.3

Far Calls (Available on 548 /549/5402/5410/5420)

To allow calls to extended memory, the 548, 549, 5402, 5410, and 5420 include two far call instructions:

Table 69. Far Call Instructions

Number of Cycles (Condition met / Not met) Delayed 3/3 Instruction CC[D] Description Nondelayed 5/3 Places the return address on the stack and then loads the PC with the address specified by the instruction if the condition specified by the instruction is met

The FCALL instruction pushes XPC onto the stack, pushes PC onto the stack, and branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified by the the instruction. The FCALA pushes XPC onto the stack, pushes PC onto the stack, and branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified in the designated accumulator.

Table 69 shows the far call instructions in the 548, 549, 5402, 5410, and 5420 (nondelayed and delayed) and the number of cycles needed to execute these instructions. Note that delayed instructions need two cycles fewer than the corresponding nondelayed instructions.

Instruction FCALL[D] Description Number of Cycles (Nondelayed / Delayed) 4/2 Places XPC and PC on the stack and then loads XPC and PC with the address specified by the instruction Places XPC and PC on the stack and then loads XPC and PC with the address specified in the designated accumulator FCALA[D] 6/4

Program Memory Addressing

6-11

Returns

6.5 Returns
Return instructions provide a way to resume processing of a sequence of instructions that was broken by a call to another function or an interrupt service routine. When the called function or interrupt service routine has completed its execution, it is necessary to resume processing at the point immediately following the call or the point at which the interrupt occurred. Return instructions accomplish this by popping the top value of the stack, which contains the address of the next instruction to be executed, into the program counter (PC). The 54x performs both unconditional and conditional returns, and both of these types can be either nondelayed or delayed. The 548, 549, 5402, 5410, and 5420 offer an additional return instruction: an unconditional far return, both nondelayed and delayed.

6.5.1

Unconditional Returns
An unconditional return is always executed when it is encountered. When the return is executed, PC is loaded with the return address from the stack and execution resumes at the instruction following the instruction that called the function or at the point at which the interrupt occurred. By the time the unconditional return instruction reaches the execute phase of the pipeline, the next two instruction words have already been fetched. How these two instruction words are handled depends in part on whether the return is nondelayed or delayed.

Nondelayed: The two instruction words are flushed from the pipeline so that they are not executed, the return address is taken from the stack or from the RTN register, and then execution continues at that address in the calling function. Delayed: The one 2-word instruction or two 1-word instructions following the return instruction are executed. This lets you avoid flushing the pipeline, which requires extra cycles. The return address is taken from the stack or from the RTN register.

Note: The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity (a branch, call, return, or software interrupt). Table 610 shows the unconditional return instructions in the 54x (nondelayed and delayed) and the number of cycles needed to execute these instructions. Delayed instructions need two cycles fewer than the corresponding nondelayed instructions.
6-12

Returns

Table 610. Unconditional Return Instructions

6.5.2

Conditional Returns
By using the conditional return (RC) instruction, you can give a function or interrupt service routine (ISR) more than one possible return path. The path chosen depends on the data being processed. In addition, you can use a conditional return to avoid conditionally branching to/around the return instruction at the end of the function or ISR. Conditional returns operate like unconditional returns, but they execute only when one or more conditions are met. The possible conditions are given in Table 613 on page 6-16. If all the conditions are met, the processor loads the return address from the stack to PC, and resumes execution of the calling program. The conditional return is a single-word instruction; however, because of the potential PC discontinuity, it operates with the same effective execution time as the conditional branch or call.
Program Memory Addressing
6-13

Instruction RET[D] Description Number of Cycles (Nondelayed / Delayed) 5/3 5/3 Load the PC with the return address at the top of the stack RETE[D] Load the PC with the return address at the top of the stack, and enable maskable interrupts RETF[D] Load the PC with the return address in the RTN register, and enable maskable interrupts 3/1

Enabling interrupts with the RETE and RETF instructions ensures that the return executes before another interrupt is processed. By using the RETF instruction, loading the PC from the RTN register rather than the stack allows a quicker return. This reduces the total number of cycles used by an interrupt routine, which is particularly important for short, frequently used interrupt routines. Note: The RTN register is a CPU-internal register that you cannot read from or write to.

Returns

By the time the conditions of the conditional return instruction have been tested, the two instruction words following the return instruction have already been fetched in the pipeline. How these two instruction words are handled depends in part on whether the return is nondelayed or delayed:

Nondelayed: If all the conditions are met, these two instruction words are flushed from the pipeline so that they are not executed, and then execution of the calling program continues. If the conditions are not met, the two instructions are executed instead of the return. Delayed: The processor executes the two instructions that follow the return instruction. This allows you to avoid flushing the pipeline, which requires extra cycles. The conditions tested are not affected by the instructions following the delayed return.

Note: The two words following a delayed instruction cannot be an instruction that causes a PC discontinuity (a branch, call, return, or software interrupt).

Table 611 shows the conditional return instruction and the number of cycles needed to execute this instruction.

Table 611. Conditional Return Instruction

6.5.3

Far Returns (Available on 548/549/5402/5410/5420)

To allow returns from extended memory, the 548, 549, 5402, 5410, and 5420 include two far-return instructions:

6-14

Number of Cycles (Condition met / Not met) Delayed 3/3 Instruction RC[D] Description Nondelayed 5/3 Load PC with the return address at the top of the stack if the condition specified by the instruction is met

FRET loads XPC from the stack and then loads PC from the stack, allowing program execution to resume at the previous point. FRETE loads XPC from the stack, loads PC from the stack, and enables maskable interrupts.

Returns

Table 612 shows the far return instructions in the 548, 549, 5402, 5410, and 5420 (nondelayed and delayed) and the number of cycles needed to execute these instructions. Note that delayed instructions need two cycles fewer than the corresponding nondelayed instructions.

Table 612. Far Return Instructions

Instruction FRET[D] Description Number of Cycles (Nondelayed / Delayed) 6/4 Loads XPC with the value at the top of the stack and loads PC with the next value on the stack Loads XPC with the value at the top of the stack, loads PC with the next value on the stack, and enables maskable interrupts FRETE[D] 6/4

Program Memory Addressing

6-15

Conditional Operations

6.6 Conditional Operations

The 54x includes instructions that execute only if one or more conditions are met. Table 613 lists the conditions that you can use with these instructions and their corresponding operand symbols.

Table 613. Conditions for Conditional Instructions

6-16

Condition A=0 Description Operand AEQ BEQ Accumulator A equal to 0 Accumulator B equal to 0 B=0 A

00 B00
A<0 B<0 A

Accumulator A not equal to 0 Accumulator B not equal to 0 Accumulator A less than 0 Accumulator B less than 0

ANEQ BNEQ ALT BLT

v0 Bv0
A>0 B>0 A

Accumulator A less than or equal to 0 Accumulator B less than or equal to 0 Accumulator A greater than 0 Accumulator B greater than 0

ALEQ BLEQ AGT BGT

w0 Bw0

Accumulator A greater than or equal to 0 Accumulator B greater than or equal to 0 Accumulator A overflow detected Accumulator B overflow detected

AGEQ BGEQ AOV BOV

AOV = 1 BOV = 1 AOV = 0 BOV = 0 C=1 C=0

No accumulator A overflow detected No accumulator B overflow detected ALU carry set to 1

ANOV BNOV C

ALU carry cleared to 0

NC TC

TC = 1 TC = 0

Test/control flag set to 1

Test/control flag cleared to 0 BIO signal is low

NTC BIO

BIO low

BIO high none

BIO signal is high

NBIO UNC

Unconditional operation

Conditional Operations

6.6.1

Using Multiple Conditions

Multiple conditions can be listed as operands of the conditional instructions. If multiple conditions are listed, all conditions must be met for the instruction to execute. Only certain combinations of conditions are acceptable (see Table 614). For each combination, the conditions must be selected from Group 1 or Group 2 as follows:

Group 1: You can select one condition from category A and one condition from category B. The two conditions cannot be from the same category. For example, you can test EQ and OV at the same time but you cannot test GT and NEQ at the same time. The accumulator must be the same for both conditions; you cannot test conditions for both accumulators with the same instruction. For example, you can test AGT and AOV at the same time, but you can not test AGT and BOV at the same time. Group 2: You can select one condition from each of three categories (A, B, and C). No two conditions can be from the same category. For example, you can test TC, C, and BIO at the same time, but you cannot test NTC, C, and NC at the same time.

Table 614. Grouping of Conditions for Multiconditional Instructions

Group 1 Category A EQ NEQ LT LEQ GT GEQ Category B OV NOV Category A TC NTC Group 2 Category B C NC Category C BIO NBIO

6.6.2

Conditional Execute (XC) Instruction

Where code branches conditionally over a 1- or 2-word code segment, you can replace the branch with a 1-cycle conditional execute instruction (XC). There are two forms for the XC instruction. One form is a conditional execute of a 1-word instruction (XC 1, cond). The second form is a conditional execute of one 2-word instruction or two 1-word instructions (XC 2, cond). Conditions for XC are the same as the conditions for conditional branches, calls, and returns (see Table 613).
Program Memory Addressing
6-17

Conditional Operations

The condition must be stable two full cycles before the XC instruction is executed. This ensures that the decision is made before the instruction following XC is decoded. Avoid changing the XC condition in the two 1-word instructions prior to XC. If no interrupts occur, these instructions have no effect on XC. However, if an interrupt occurs, it can trap between the instructions and XC, affecting the condition before XC is executed. See Chapter 7, Pipeline, for information about pipeline latencies.

6.6.3

Conditional Store Instructions

Some CPU registers can be conditionally stored in data memory using the conditional store instructions, listed in Table 615. The conditions used with conditional store instructions are listed in Table 616. In a conditional store instruction, the address is modified and the memory operand is read regardless of the condition. If the condition is met, the corresponding register is stored in data memory. If the condition is not met, the operand is written into the same memory location from which it was read, so, the value of that memory location remains the same. The conditional store instructions are single memory-operand instructions, but they use the dual memory-operand indirect addressing mode to put the instruction into one 16-bit word. Therefore, these instructions execute in one cycle. Conditionally storing the block-repeat counter (BRC) allows you to store an index in a repeat-block loop.

Table 615. Conditional Store Instructions

6-18

Instruction SACCD STRCD CPU Register Accumulator A or B Temporary register (T) SRCCD Block-repeat counter (BRC)

Conditional Operations

Table 616. Conditions for Conditional Store Instructions

Operand AEQ BEQ Condition A=0 B=0 A Description Accumulator A equal to 0 Accumulator B equal to 0 ANEQ BNEQ ALT BLT

00 B00
A<0 B<0 A

Accumulator A not equal to 0 Accumulator B not equal to 0 Accumulator A less than 0 Accumulator B less than 0

ALEQ BLEQ AGT BGT

v0 Bv0
A>0 B>0 A

Accumulator A less than or equal to 0 Accumulator B less than or equal to 0 Accumulator A greater than 0 Accumulator B greater than 0

AGEQ BGEQ

w0 Bw0

Accumulator A greater than or equal to 0 Accumulator B greater than or equal to 0

Program Memory Addressing

6-19

Repeating a Single Instruction

6.7 Repeating a Single Instruction

The 54x includes two instructions, RPT and RPTZ, that cause the next instruction to be repeated. The number of times for the instruction to be repeated is obtained from an operand of the instruction, and is equal to this operand + 1. This value is stored in the 16-bit repeat counter (RC) register. You cannot program the value in the RC register; it is loaded by the repeat instructions (RPT or RPTZ) only. The maximum number of executions of a given instruction is 65 536. An absolute program or data address is automatically incremented when the single-repeat feature is used. Once a repeat instruction is decoded, all interrupts, including NMI but not RS, are disabled until the completion of the repeat loop. However, the 54x does respond to the HOLD signal while executing an RPT/RPTZ loopthe response depends on the value of the HM bit of ST1. The repeat function can be used with some instructions, such as multiply/ accumulate and block moves, to increase the execution speed of these instructions. These multicycle instructions (see Table 617) effectively become single-cycle instructions after the first iteration of a repeat instruction.

Table 617. Multicycle Instructions That Become Single-Cycle Instructions When Repeated

6-20

Instruction FIRS Description # Cycles 3 3 3 2 2 4 2 2 3 5 5 Symmetrical FIR filter MACD MACP MVDK Multiply and move result in accumulator with delay Multiply and move result in accumulator Data-to-data move MVDM MVDP MVKD Data-to-MMR move Data-to-program move Data-to-data move MVMD MVPD MMR-to-data move Program-to-data move Program-to-data move READA WRITA Data-to-program move
Number of cycles when instruction is not repeated

Single data-memory operand instructions cannot be repeated if a long offset modifier or an absolute address is used (for example, *ARn(lk), *+ARn(lk), *+ARn(lk)% and *(lk)). Instructions listed in Table 618 cannot be repeated using RPT.

Repeating a Single Instruction

Table 618. Nonrepeatable Instructions

Instruction ADDM ANDM B[D] Description Add long constant to data memory AND data memory with long constant Unconditional branch BACC[D] BANZ[D] BC[D] Branch to accumulator address Branch on auxiliary register not 0 Conditional branch CALA[D] CALL[D] CC[D] Call to accumulator address Unconditional call Conditional call CMPR DST Compare with auxiliary register Long word (32-bit) store FB[D] Far branch unconditionally FBACC[D] FCALA[D] FCALL[D] FRET[D] Far branch to location specified by accumulator Far call subroutine at location specified by accumulator Far call unconditionally Far return FRETE[D] IDLE Enable interrupts and far return from interrupt Idle instructions Interrupt trap INTR LD ARP LD DP Load auxiliary register pointer (ARP) Load data page pointer (DP) MVMM ORM Move memory-mapped register (MMR) to another MMR OR data memory with long constant Conditional return Software reset RC[D] RESET RET[D] Unconditional return

Program Memory Addressing

6-21

Repeating a Single Instruction

Table 618. Nonrepeatable Instructions (Continued)

6-22

Instruction RETE[D] RETF[D] RND RPT Description Return from interrupt Fast return from interrupt Round accumulator Repeat next instruction Block repeat RPTB[D] RPTZ Repeat next instruction and clear accumulator Reset status register bit Set status register bit Software trap RSBX SSBX TRAP XC Conditional execute XORM XOR data memory with long constant

Repeating a Block of Instructions

6.8 Repeating a Block of Instructions

The repeat-block instructions are used to repeat a block of code N + 1 times, where N is the value loaded into the block-repeat counter register (BRC). This block of code can contain one or more instructions. Unlike the repeat single operation, which disables all maskable interrupts, the repeat block operation can be interrupted. The instructions used for this operation are RPTB and RPTBD (a delayed instruction). The RPTB instruction executes in four cycles. RPTBD allows the execution of one 2-word instruction or two 1-word instructions following the RPTBD instruction instead of flushing the pipeline; thus, RPTBD effectively executes in 2 cycles. When the RPTBD instruction is used, delayed instructions cannot be in the two words following the RPTBD instruction. The repeat block feature provides zero-overhead looping. Zero-overhead looping is controlled by the block-repeat active flag (BRAF) in ST1 and the following memory-mapped registers:

BRC contains the value N, which is one less than the number of times the block is to be repeated. The block-repeat start address register (RSA) holds the address of the first instruction of the block of code to be repeated. The block-repeat end address register (REA) holds the address of the last instruction word of the block of code to be repeated.

BRAF is set to 1 to activate the block repeat. The block repeat feature can be activated only if the number of iterations is greater than 0. The following steps start a loop: Step 1: You load BRC with a loop count in the 0 through 65 535 range. Step 2: The instruction loads the address of the first instruction to be repeated. This instruction is the one immediately following RPTB of the second instruction following RPTBD. The repeat-block (RPTB) or repeat block with delay (RPTBD) instruction automatically loads RSA with the address of the instruction following the RPTB instruction, or with the address of the second instruction following the RPTBD instruction.

Program Memory Addressing

6-23

Repeating a Block of Instructions

Step 3: The instruction loads REA with the address following the last word of the last instruction to be repeated in the block, which is also the long-immediate operand given in the instruction. This action also sets BRAF. REA is loaded with the 16-bit-immediate operand of the RPTB or RPTBD instruction, and the BRAF bit is set. The value for the 16-bit-immediate operand of RPTB or RPTBD is L 1, where L is the address of the instruction following the last word of the last instruction in the loop. Every time the PC is updated during loop execution, REA is compared to the PC value. If the values are equal, BRC is decremented. If BRC is greater than or equal to 0, RSA is loaded into the PC to restart the loop. If not, BRAF is reset to 0 and the processor resumes execution past the end of the loop. BRC is decremented during the instruction decode phase of the last repeat block instruction. For this reason, be careful when using the SRCCD instruction within a loop. To save the current loop counter value (the predecremented BRC), the SRCCD instruction must be placed a minimum of three instructions before the end of the loop. There is only one set of block repeat registers, so multiple block repeats cannot be nested without saving the context of the outside loops. The simplest way of establishing nested loops is to use the RPTB[D] instruction for the innermost loop only, and use the BANZ[D] for all outer loops.

6-24

Reset Operation

6.9 Reset Operation

Reset (RS) is a nonmaskable external interrupt that can be used at any time to place the 54x into a known state. For correct system operation after power-up, RS must be asserted (low) for several clock cycles to ensure that the data, address, and control lines are configured properly. Approximately five clock cycles after RS is de-asserted (goes high), the processor fetches the instruction at FF80h and begins executing code. See section 10.5, Start-Up Access Sequences, on page10-24, for the reset sequence. The following actions occur during a reset operation:

IPTR is set to 1FFh. RS is de-asserted. The MP/MC bit in PMST is set to the value of the MP/MC pin. PC is set to FF80h. XPC is cleared (548, 549, 5402, 5410, and 5420). FF80h is driven on the address bus, regardless of the state of MP/MC. The data bus goes into the high-impedance state. The control lines are made inactive. The IACK signal is generated. INTM is set to 1 to disable all maskable interrupts. IFR is cleared to clear the interrupt flags. The single repeat counter (RC) is cleared. A synchronized reset (SRESET) signal is sent to initialize the peripherals. The following status bits are set to their initial values:

J J J J J J

ARP = 0 ASM = 0 AVIS = 0 BRAF = 0 C=1 C16 = 0

J J J J J J

CLKOFF = 0 CMPT = 0 CPL = 0 DP = 0 DROM = 0 FRCT = 0

J J J J J J

HM = 0 INTM = 1 OVA = 0 OVB = 0 OVLY = 0 OVM = 0

J J J

SXM = 1 TC = 1 XF = 1

Notes: 1) The remaining status bits are not initializedyour code must initialize them appropriately. 2) Reset does not initialize the stack pointer (SP). Your code must initialize it. 3) If MP/MC = 0, the device begins executing code from the on-chip ROM. Otherwise, it begins executing code from off-chip memory.

Program Memory Addressing

6-25

Interrupts

6.10 Interrupts
Interrupts are hardware- or software-driven signals that cause the 54x to suspend its main program and execute another function called an interrupt service routine (ISR). Typically, interrupts are generated by hardware devices that need to give data to or take data from the 54x (for example, ADCs, DACs, and other processors). Interrupts can also be used to signal that a particular event has taken place (for example, the timer is finished counting). The 54x supports both software and hardware interrupts:

A software interrupt is requested by a program instruction (INTR, TRAP, or RESET). A hardware interrupt is requested by a signal from a physical device. Two types exist:

J J

External hardware interrupts are triggered by signals at external interrupt ports. Internal hardware interrupts are triggered by signals from the on-chip peripherals.

When multiple hardware interrupts are triggered at the same time, the 54x services them according to a set priority ranking in which 1 has the highest priority. To determine the priorities for the hardware interrupts, refer to the table for your particular 54x device in section 6.10.10, Interrupt Tables, on page 6-38. Each of the 54x interrupts, whether hardware or software, can be placed in one of the following two categories:

Maskable interrupts. These are hardware or software interrupts that can be blocked (masked) or enabled (unmasked) using software. The 54x supports up to 16 user-maskable interrupts (SINT15SINT0). Each device uses a subset of these 16 interrupts. For example, the 541 uses only nine of these interrupts (the others are tied high internally). Some of these have two names because they can be initiated by software or hardware; for the 541, the hardware names for these interrupts are:

J J J

INT3 through INT0 RINT0, XINT0, RINT1, and XINT1 (serial port interrupts) TINT (timer interrupt)

Nonmaskable interrupts. These interrupts cannot be blocked. The 54x always acknowledges this type of interrupt and branches from the main program to an ISR. The 54x nonmaskable interrupts include all software interrupts and two external hardware interrupts: RS (reset) and NMI. (RS and NMI can also be asserted using software.)

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Interrupts

RS is a nonmaskable interrupt that affects all 54x operating modes. See section 6.9, Reset Operation, on page 6-25. NMI is a nonmaskable interrupt. Interrupts are globally disabled when NMI is asserted. NMI is different from RS because it does not affect any of the 54x modes. The 54x handles interrupts in three phases: 1) Receive interrupt request. Suspension of the main program is requested via software (program code) or hardware (a pin or an on-chip peripheral). If the interrupt source is requesting a maskable interrupt, the corresponding bit in the interrupt flag register (IFR) is set when the interrupt is received. 2) Acknowledge interrupt. The 54x must acknowledge the interrupt request. If the interrupt is maskable, predetermined conditions must be met in order for the 54x to acknowledge it. For nonmaskable hardware interrupts and for software interrupts, acknowledgment is immediate. 3) Execute interrupt service routine (ISR). Once the interrupt is acknowledged, the 54x executes the branch instruction you place at a predetermined address (the vector location) and performs the ISR.

6.10.1 Interrupt Flag Register (IFR)

IFR is a memory-mapped CPU register that identifies and clears active interrupts (see Figure 62). An interrupt sets its corresponding interrupt flag in IFR until it is recognized by the CPU. Any of the following four events clear an interrupt flag:

The 54x is reset (RS is low). An interrupt trap is taken. A 1 is written to the appropriate bit in IFR. The INTR instruction is executed using the appropriate interrupt number.

A 1 in any IFR bit indicates a pending interrupt. To clear an interrupt, write a 1 to the interrupts corresponding bit in the IFR. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR.

Program Memory Addressing

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Interrupts

Figure 62. Interrupt Flag Register (IFR) Diagram

(a) 541 IFR
1512 Resvd 11 Resvd 10 Resvd 9 Resvd 8 INT3 7 XINT1 6 RINT1 5 XINT0 4 RINT0 3 TINT 2 INT2 1 INT1 0 INT0

(b) 542 IFR

1512 Resvd 11 Resvd 10 Resvd 9 HPINT 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

TXINT TRINT BXINT0 BRINT0

(c) 543 IFR

1512 Resvd 11 Resvd 10 Resvd 9 Resvd 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

TXINT TRINT BXINT0 BRINT0

(d) 545 IFR

1512 Resvd 11 Resvd 10 Resvd 9 HPINT 8 INT3 7 XINT1 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

RINT1 BXINT0 BRINT0

(e) 546 IFR

1512 Resvd 11 Resvd 10 Resvd 9 Resvd 8 INT3 7 XINT1 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

RINT1 BXINT0 BRINT0

(f) 548 IFR

1512 11 10 9 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

Resvd BXINT1 BRINT1 HPINT

TXINT TRINT BXINT0 BRINT0

(g) 549 IFR

1514
Resvd

13

12

11

10

2
INT2

1
INT1

0
INT0

BMINT1 BMINT0 BXINT1 BRINT1 HPINT INT3 TXINT TRINT BXINT0 BRINT0 TINT

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Interrupts

(h) 5402 IFR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

INT3

TINT1 or DMAC0 BXINT0 BRINT0 TINT0 DMAC1

(i) 5410 IFR

15 14 13 12 11 10 9 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

(j) 5420 IFR

15 14 13 12 11 10 9 8 RSVD 7 6 5 4 3 TINT 2 RSVD 1 INT1 0 INT0

Resvd

IPINT DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

6.10.2 Interrupt Mask Register (IMR)

Figure 63 shows how the 54x uses a memory-mapped IMR for masking external and internal interrupts. If INTM = 0 in ST1, a 1 in any IMR bit enables the corresponding interrupt. Neither NMI nor RS is included in the IMR, because IMR has no effect on these interrupts. You can read or write to the IMR.

Figure 63. Interrupt Mask Register (IMR) Diagram

(a) 541 IMR
1512 Resvd 11 Resvd 10 Resvd 9 Resvd 8 INT3 7 XINT1 6 RINT1 5 XINT0 4 RINT0 3 TINT 2 INT2 1 INT1 0 INT0

(b) 542 IMR

1512 Resvd 11 Resvd 10 Resvd 9 HPINT 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

TXINT TRINT BXINT0 BRINT0

(c) 543 IMR

1512 Resvd 11 Resvd 10 Resvd 9 Resvd 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

TXINT TRINT BXINT0 BRINT0

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Interrupts

(d) 545 IMR

1512 Resvd 11 Resvd 10 Resvd 9 HPINT 8 INT3 7 XINT1 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

RINT1 BXINT0 BRINT0

(e) 546 IMR

1512 Resvd 11 Resvd 10 Resvd 9 Resvd 8 INT3 7 XINT1 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

RINT1 BXINT0 BRINT0

(f) 548 IMR

1512 11 10 9 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

Resvd BXINT1 BRINT1 HPINT

TXINT TRINT BXINT0 BRINT0

(g) 549 IMR

1514
Resvd

13

12

11

10

2
INT2

1
INT1

0
INT0

BMINT1 BMINT0 BXINT1 BRINT1 HPINT INT3 TXINT TRINT BXINT0 BRINT0 TINT

(h) 5402 IMR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

INT3

TINT1 or DMAC0 BXINT0 BRINT0 TINT0 DMAC1

(i) 5410 IMR

15 14 13 12 11 10 9 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

(j) 5420 IMR

15 14 13 12 11 10 9 8 RSVD 7 6 5 4 3 TINT 2 RSVD 1 INT1 0 INT0

Resvd

IPINT DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

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Interrupts

6.10.3 Phase 1: Receive Interrupt Request

Request Acknowledgment Interrupt service routine

An interrupt is requested by a hardware device or by a software instruction. When an interrupt request occurs, the corresponding flag (if any) is activated in the IFR (see section 6.10.1, Interrupt Flag Register (IFR), on page 6-27). This flag is activated whether or not the interrupt is later acknowledged by the processor. The flag is automatically cleared when its corresponding interrupt is taken.

Hardware interrupt requests. External hardware interrupts are requested by signals at external interrupt ports, and internal hardware interrupts are requested by signals from the on-chip peripherals. For example, on the 541, hardware interrupts can be requested by or through:

J J J J -

Pins INT3 through INT0 Pins RS (reset) and NMI The serial ports interrupts (RINT0 and XINT0 or RINT1 and XINT1) The timer interrupt (TINT)

Table 619 through Table 624 (pages 6-38 through 6-43) list the interrupt sources for each 54x device. Software interrupt requests. A software interrupt is requested by one of the following program instructions:

J J

INTR. This instruction allows you to execute any interrupt service routine. The instruction operand (K) indicates which interrupt vector location the CPU branches to. Table 619 through Table 624 (pages 6-38 through 6-43) show the operand K used to refer to each vector location. When an INTR interrupt is acknowledged, the interrupt mode bit (INTM) in ST1 is set to 1 to disable maskable interrupts. TRAP. This instruction performs the same function as the INTR instruction without setting the INTM bit. Table 619 through Table 624 (pages 6-38 through 6-43) show the operand K used to refer to each vector location. RESET. This instruction performs a nonmaskable software reset that can be used any time to put the 54x into a known state. The RESET instruction affects ST0 and ST1, but does not affect PMST. For a summary of the registers and bits affected, see the description of the
Program Memory Addressing
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Interrupts

RESET instruction in TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set or Volume 3: Algebraic Instruction Set. When the RESET instruction is acknowledged, INTM is set to 1 to disable maskable interrupts. The initialization of IPTR and the peripheral registers is different from the initialization done by a hardware reset (see section 6.9, Reset Operation, on page 6-25).

6.10.4 Phase 2: Acknowledge Interrupt

Request Acknowledgment Interrupt service routine

After an interrupt has been requested by hardware or software, the CPU must decide whether to acknowledge the request. Software interrupts and nonmaskable hardware interrupts are acknowledged immediately. Maskable hardware interrupts are acknowledged only after certain conditions are met:

Priority is highest. When more than one hardware interrupt is requested at the same time, the 54x services them according to a set priority ranking in which 1 indicates the highest priority. Table 619 through Table 624 show the priorities for the hardware interrupts. INTM bit is 0. The interrupt mode bit (INTM), which is in ST1, enables or disables all maskable interrupts:

J J

When INTM = 0, all unmasked interrupts are enabled. When INTM = 1, all unmasked interrupts are disabled.

INTM is set to 1 automatically when an interrupt is taken. If the program exits the interrupt service routine (ISR) using the RETE instruction (return from interrupt with automatic reenable), INTM is reenabled (cleared). INTM can also be set with a hardware reset (RS) or by executing an SSBX INTM instruction (disable interrupt). INTM is reset by executing the RSBX INTM instruction (enable interrupt). INTM does not actually modify IMR or IFR.

IMR mask bit is 1. Each of the maskable interrupts has its own mask bit in the IMR. To enable an interrupt, set its mask bit to 1. See section 6.10.2, Interrupt Mask Register (IMR), on page 6-29.

The CPU acknowledges a maskable hardware interrupt, it jams the instruction bus with the INTR instruction. This instruction forces PC to the appropriate address and fetches the software vector. As the CPU fetches the first word of the software vector, it generates the IACK signal, which clears the appropriate interrupt flag bit.
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Interrupts

For enabled interrupts, when IACK occurs, the interrupt number is indicated by address bits A6A2 on the rising edge of CLKOUT. If the interrupt vectors reside in on-chip memory and you want to observe the addresses, the 54x must operate in address visibility mode (AVIS = 1) so that the interrupt number can be decoded. If an interrupt occurs while the 54x is on hold and HM = 0, the address cannot be present when IACK becomes active.

6.10.5 Phase 3: Execute Interrupt Service Routine (ISR)

Request Acknowledgment Interrupt service routine

After acknowledging the interrupt, the CPU: 1) Stores the program counter (PC) value (the return address) to the top of the stack in data memory Note: The program counter extension register, XPC, does not get pushed to the top of the stack; that is, it does not get saved on the stack. Therefore, if an ISR is located on a different page from the vector table, you must push the XPC on the stack prior to branching to the ISR. A FRET [E] can be used to return from the ISR. 2) Loads the PC with the address of the interrupt vector 3) Fetches the instruction located at the vector address. (If the branch is delayed and you also stored one 2-word instruction or two 1-word instructions, the CPU also fetches these words.) 4) Executes the branch, which leads it to the address of your ISR. (If the branch is delayed, the additional instruction(s) are executed before the branch.) 5) Executes the ISR until a return instruction concludes the ISR 6) Follows the stack pointer (SP) to the top of the stack, and pops the return address off the stack and into PC 7) Continues executing the main program To determine which vector address has been assigned to each of the interrupts, refer to the table for your specific 54x device in section 6.10.10, Interrupt Tables, on page 6-38. Interrupt addresses are spaced four locations apart so
Program Memory Addressing
6-33

Interrupts

that a delayed branch instruction and two 1-word instructions or one 2-word instruction can be accommodated in those locations.

6.10.6 Interrupt Context Save

When an interrupt service routine is executed, certain registers must be saved onto the stack. When the program returns from the ISR (by an RC[D], RETE[D], or RETF[D]), your software code must restore the contents of these registers. You can manage stack storage as long as the stack does not exceed the memory space. This stack is also used for subroutine calls; the 54x supports subroutine calls within the ISR. Because the CPU registers and peripheral registers are memory-mapped, the PSHM and POPM instructions can transfer these registers to and from the stack. In addition, the PSHD and POPD instructions can transfer data-memory values to and from the stack. There are a number of special considerations that you must follow when doing context saves and restores. The first consideration is that when you use the stack to save the context you must perform the restore in the exact reverse order. The second consideration is that BRC should be restored prior to restoring the BRAF bit in ST1. If you fail to follow this order, the BRAF bit will be cleared, if BRC = 0 before BRC is restored.

6.10.7 Interrupt Latency

The 54x completes all instructions in the pipeline except the instructions in the prefetch and fetch stages before executing an interrupt, so the maximum interrupt latency depends on the contents of the pipeline. See section 7.2, Interrupts and the Pipeline, on page 7-25 for more information about pipeline latencies associated with interrupts. Instructions that are extended by wait states for slower-memory access and repeated instructions require extra time to process an interrupt. The single-repeat instructions (RPT and RPTZ) require that all executions of the next instruction be completed before allowing an interrupt to execute to protect the context of the repeated instructions. This protection is necessary, because these instructions run parallel operations in the pipeline, and the context of these operations cannot be saved in the ISR. Since the hold function takes precedence over interrupts, it can also delay an interrupt trap. If an interrupt occurs when the CPU is on hold (HOLD is asserted) and the interrupt vector must be fetched from external memory, the interrupt is not taken until HOLDA is de-asserted (after the hold state ends). However, if the processor is in the concurrent hold mode (HM = 0) and the interrupt vector table is located in internal memory, the CPU takes the interrupt, regardless of HOLD.
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Interrupts

Interrupts cannot be processed between the RSBX INTM instruction and the next instruction in a program sequence. If an interrupt occurs during the decode phase of RSBX INTM, the CPU always completes RSBX INTM as well as the following instruction before the pending interrupt is processed. Waiting for these instructions to complete ensures that a return (RET) can be executed in an ISR before the next interrupt is processed to protect against stack overflow. If an ISR ends with an RETE instruction (return from ISR with enable), the RSBX INTM instruction is unnecessary. Similar to an RSBX INTM instruction, an SSBX INTM instruction and the instruction that follows it cannot be interrupted. Note: Reset (RS) is not delayed by multicycle instructions. NMI can be delayed by multicycle instructions and by HOLD.

6.10.8 Interrupt Operation: A Quick Summary

Once an interrupt has been passed to the CPU, the CPU operates in the following manner (see Figure 65 on page 6-37):

If a maskable interrupt is requested: 1) The corresponding bit in the IFR is set. 2) The acknowledgment conditions (INTM = 0 and IMR bit =1) are tested. If the conditions are true, the CPU acknowledges the interrupt, generating an IACK signal; otherwise, it ignores the interrupt and continues with the main program. 3) When the interrupt has been acknowledged, its flag bit in the IFR is cleared to 0 and the INTM bit is set to 1 (to block other maskable interrupts). 4) The PC is saved on the stack. 5) The CPU branches to and executes the interrupt service routine (ISR). 6) The ISR is concluded by a return instruction, which pops the return address off the stack.

7) The CPU continues with the main program. If a nonmaskable interrupt is requested: 1) The CPU immediately acknowledges the interrupt, generating an IACK signal. 2) If the interrupt was requested by RS, NMI, or the INTR instruction, the the INTM bit is set to 1 to block maskable hardware interrupts.
Program Memory Addressing
6-35

Interrupts

3) If the INTR instruction has requested one of the maskable interrupts, the corresponding flag bit is cleared to 0. 4) The PC is saved on the stack. 5) The CPU branches to and executes the ISR. 6) The ISR is concluded by a return instruction, which pops the return address of the stack. 7) The CPU continues with the main program. Note: The INTR instruction disables maskable interrupts by setting the interrupt mode bit (INTM), but the TRAP instruction does not affect INTM.

6.10.9 Re-mapping Interrupt-Vector Addresses

The interrupt vectors can be remapped to the beginning of any 128-word page in program memory except in reserved areas. The interrupt-vector address is generated by concatenating the interrupt-pointer (IPTR) field of PMST with the interrupt-vector number (031) shifted by 2. Consider the example of Figure 64: if INT0 is asserted low and IPTR = 0001h, the interrupt vector is fetched from 00C0h. The interrupt-vector number for INT0 is 16 or 10h.

Figure 64. Interrupt-Vector Address Generation

IPTR = 0 0000 0001 INT = 40h (INT0)

Vector Bit Address

0 0

0 0

1 7

1 6 C

0 5

0 4

0 3

0 0

0 0

15 14 13 12

11 10 9 8

2 1

At reset, the IPTR bits are set to 1 (IPTR = 1FFh); this value maps the vectors to page 511 in program-memory space. Therefore, the reset vector for hardware resets always resides at location 0FF80h. The interrupt vectors can be mapped to another location by loading IPTR with a value other than 1FFh. For example, the interrupt vectors can be moved to start at location 0080h by loading IPTR with 0001h. Note: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector for hardware resets is always fetched at location FF80h in program space.

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Interrupts

Figure 65. Flow Diagram of Interrupt Operation

Interrupt request received

Interrupt maskable? Yes No

No

INTM = 0? Yes

No

IMR mask bit = 1? Yes Interrupt acknowledged; IACK generated

Hardware interrupt or INTR instruction?

Yes

No PC saved on software stack

INTM set to 1

Interrupt service routine run

Return instruction restores PC

Main program continues

Program Memory Addressing

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Interrupts

6.10.10 Interrupt Tables

Table 619 through Table 624 show the interrupt trap number, priority, and location for each 54x device.

Table 619. 541 Interrupt Locations and Priorities
TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 Priority 1 2 3 4 5 6 7 8 9 Name Location (Hex) 0 4 8 Function RS/SINTR Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 C 10 14 18 1C 20 24 28 10 11 2C 30 34 38 12 13 14 15 16 17 18 19 20 21 22 23 24 Software interrupt #29; reserved Software interrupt #30; reserved External user interrupt #0 External user interrupt #1 External user interrupt #2 Internal timer interrupt 3C 40 44 48 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 4C 50 54 58 RINT0/SINT4 XINT0/SINT5 Serial port 0 receive interrupt Serial port 0 transmit interrupt Serial port 1 receive interrupt RINT1/SINT6 XINT1/SINT7 INT3/SINT8 10 11 5C 60 Serial port 1 transmit interrupt External user interrupt #3 Reserved 2531 647F 6-38


Table 620. 542 Interrupt Locations and Priorities
TRAP/INTR Number (K) 2631 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 0 Priority 12 10 11 9 8 7 6 5 4 3 2 1 HPINT/SINT9 INT3/SINT8 TXINT/SINT7 TRINT/SINT6 BXINT0/SINT5 BRINT0/SINT4 TINT/SINT3 INT2/SINT2 INT1/SINT1 INT0/SINT0 SINT30 SINT29 SINT28 SINT27 SINT26 SINT25 SINT24 SINT23 SINT22 SINT21 SINT20 SINT19 SINT18 SINT17 NMI/SINT16 RS/SINTR Name Location (Hex) 687F 5C 4C 3C 2C 1C 64 60 58 54 50 48 44 40 38 34 30 28 24 20 18 14 10 C 8 4 0 Reserved HPI interrupt External user interrupt #3 TDM serial port transmit interrupt TDM serial port receive interrupt Buffered serial port transmit interrupt Buffered serial port receive interrupt Internal timer interrupt External user interrupt #2 External user interrupt #1 External user interrupt #0 Software interrupt #30, reserved Software interrupt #29, reserved Software interrupt #28 Software interrupt #27 Software interrupt #26 Software interrupt #25 Software interrupt #24 Software interrupt #23 Software interrupt #22 Software interrupt #21 Software interrupt #20 Software interrupt #19 Software interrupt #18 Software interrupt #17 Nonmaskable interrupt Reset (hardware and software reset) Function

Program Memory Addressing

Interrupts

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Interrupts

Table 621. 543 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2531 Priority 1 2 3 4 5 6 7 8 9 10 11 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 TRINT/SINT6 TXINT/SINT7 INT3/SINT8 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 647F Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29, reserved Software interrupt #30, reserved External user interrupt #0 External user interrupt #1 External user interrupt #2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt #3 Reserved

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Table 622. 545 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2631 Priority 1 2 3 4 5 6 7 8 9 10 11 12 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 RINT1/SINT6 XINT1/SINT7 INT3/SINT8 HPINT/SINT9 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 687F Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29, reserved Software interrupt #30, reserved External user interrupt #0 External user interrupt #1 External user interrupt #2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt Serial port receive interrupt Serial port transmit interrupt External user interrupt #3 HPI interrupt Reserved

Program Memory Addressing

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Table 623. 546 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2531 Priority 1 2 3 4 5 6 7 8 9 10 11 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 RINT1/SINT6 XINT1/SINT7 INT3/SINT8 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 647F Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29, reserved Software interrupt #30, reserved External user interrupt #0 External user interrupt #1 External user interrupt #2 Internal timer interrupt Buffered serial port receive interrupt Buffered serial port transmit interrupt Serial port receive interrupt Serial port transmit interrupt External user interrupt #3 Reserved

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Table 624. 548 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 2831 Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 TRINT/SINT6 TXINT/SINT7 INT3/SINT8 HPINT/SINT9 BRINT1/SINT10 BXINT1/SINT11 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70h7F Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29, reserved Software interrupt #30, reserved External user interrupt #0 External user interrupt #1 External user interrupt #2 Internal timer interrupt Buffered serial port 0 receive interrupt Buffered serial port 0 transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt #3 HPI interrupt Buffered serial port 1 receive interrupt Buffered serial port 1 transmit interrupt Reserved

Program Memory Addressing

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Table 625. 549 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Priority 1 2 3 4 5 6 7 8 9 10 11 12 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 TRINT/SINT6 TXINT/SINT7 INT3/SINT8 HINT/SINT9 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30 External user interrupt #0 External user interrupt #1 External user interrupt #2 Internal timer interrupt Buffered serial port 0 receive interrupt Buffered serial port 0 transmit interrupt TDM serial port receive interrupt TDM serial port transmit interrupt External user interrupt #3 HPI interrupt

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Interrupts

Table 625. 549 Interrupt Locations and Priorities (Continued)

TRAP/INTR Number (K) 26 27 28 29 3031 Priority 13 14 15 16 Name BRINT1/SINT10 BXINT1/SINT11 BMINT0/SINT12 BMINT1/SINT13 Location (Hex) 68 6C 70 74 787F Function Buffered serial port 1 receive interrupt Buffered serial port 1 transmit interrupt BSP #0 misalignment detection interrupt (549 only) BSP #1 misalignment detection interrupt (549 only) Reserved

Table 626. 5402 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Priority 1 2 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30

Program Memory Addressing

6-45

Interrupts

Table 626. 5402 Interrupt Locations and Priorities (Continued)

TRAP/INTR Number (K) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 120127 Priority 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT0/SINT3 BRINT0/SINT4 BXINT0/SINT5 DMAC0/SINT7 TINT1/DMAC1/ SINT7 INT3/SINT8 HPINT/SINT9 BRINT1/DMAC2/ SINT10 BXINT1/DMAC3/ SINT11 DMAC4/SINT12 DMAC5/SINT13 Reserved Location (Hex) 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 787F Function External user interrupt #0 External user interrupt #1 External user interrupt #2 Timer0 interrupt McBSP #0 receive interrupt McBSP #0 transmit interrupt DMA channel 0 interrupt Timer1 interrupt (default) or DMA channel 1 interrupt. External user interrupt #3 HPI interrupt McBSP #1 receive interrupt (default) or DMA channel 2 interrupt McBSP #1 transmit interrupt (default) or DMA channel 3 interrupt DMA channel 4 interrupt DMA channel 5 interrupt Reserved

Table 627. 5410 Interrupt Locations and Priorities
TRAP/INTR Number (K) 0 1 2 3 4 Priority 1 2 Name Location (Hex) 0 4 8 C 10 Function RS/SINTR Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 NMI/SINT16 SINT17 SINT18 SINT19 6-46

Interrupts

Table 627. 5410 Interrupt Locations and Priorities (Continued)
TRAP/INTR Number (K) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Priority 3 4 5 6 7 8 9 10 11 12 13 14 Name Location (Hex) 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C Function SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 BRINT2/DMAC0 BXINT2/DMAC1 INT3/SINT8 HPINT/SINT9 BRINT1/DMAC2/ SINT10 BXINT1/DMAC3/ SINT11 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30 External user interrupt #0 External user interrupt #1 External user interrupt #2 Timer0 interrupt McBSP #0 receive interrupt (default) McBSP #0 transmit interrupt (default) McBSP #2 receive interrupt (default) or DMA channel 0 interrupt MCBSP #2 transmit interrupt (default) or DMA channel 1 interrupt. External user interrupt #3 HPI interrupt McBSP #1 receive interrupt (default) or DMA channel 2 interrupt. McBSP #1 transmit interrupt (default) or DMA channel 3 interrupt.

Program Memory Addressing

6-47

Interrupts

Table 627. 5410 Interrupt Locations and Priorities (Continued)
TRAP/INTR Number (K) 28 29 120127 Priority 15 16 Name Location (Hex) 70 74 787F Function DMAC4/SINT12 DMAC5/SINT13 Reserved DMA channel 4 interrupt DMA channel 5 interrupt Reserved

Table 628. 5420 Interrupt Locations and Priorities

TRAP/INTR Number (K) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Priority 1 2 3 4 5 Name RS/SINTR NMI/SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0/SINT0 INT1/SINT1 INT2/SINT2 Location (Hex) 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 Function Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30 External user interrupt #0 External user interrupt #1 Reserved

6-48

Interrupts

Table 628. 5420 Interrupt Locations and Priorities (Continued)

TRAP/INTR Number (K) 19 20 21 22 23 24 25 26 27 28 29 30 124127 Priority 6 7 8 9 10 11 12 13 14 15 16 17 Name TINT/SINT3 BRINT0/SINT4 BXINT0/SINT5 BRINT2/DMAC0 BXINT2/DMAC1 INT3/SINT8 HPINT/SINT9 BRINT1/DMAC2 BXINT1/DMAC3 DMAC4/SINT12 DMAC5/SINT13 IPINT/SINT14 Location (Hex) 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C7F Function External timer McBSP #0 receive interrupt (default) McBSP #0 transmit interrupt (default) McBSP #2 receive interrupt (default) or DMA channel 0 interrupt MCBSP #2 transmit interrupt (default) or DMA channel 1 interrupt. Reserved HPI interrupt (from DSPINT in HPIC) McBSP #1 receive interrupt (default) or DMA channel 2 interrupt. McBSP #1 transmit interrupt (default) or DMA channel 3 interrupt. DMA channel 4 interrupt DMA channel 5 interrupt Interprocessor interrupt Reserved

Program Memory Addressing

6-49

Power-Down Modes

6.11 Power-Down Modes

The 54x has power-down modes in which it enters a dormant state and dissipates less power than normal operation while maintaining the CPU contents. This allows operations to continue unaltered when the power-down mode is terminated. You can invoke one of the power-down modes either by executing the IDLE 1, IDLE 2 or IDLE 3 instructions, or by driving the HOLD signal low with the HM status bit set to 1. Power-down operation is summarized in Table 629 and described in detail in sections 6.11.1 through 6.11.5.

Table 629. Operation During the Four Power-Down Modes

Operation/Feature CPU halted CPU clock stopped Peripheral clock stopped Phase-locked loop (PLL) stopped External address lines put in high-impedance state External data lines put in high-impedance state External control signals put in high-impedance state Power-down terminated by: HOLD driven high Unmasked internal hardware interrupts Unmasked external hardware interrupts NMI RS No Yes Yes Yes Yes No No Yes Yes Yes No No Yes Yes Yes Yes No No No No IDLE1 Yes Yes No No No No No IDLE2 Yes Yes Yes No No No No IDLE3 Yes Yes Yes Yes No No No HOLD Yes No No No Yes Yes Yes

Depending on the state of the HM bit, the CPU continues to execute unless the execution requires an external memory access.

6.11.1 IDLE1 Mode

The IDLE1 mode halts all CPU activities except the system clock. Because the system clock remains applied to the peripheral modules, the peripheral circuits continue operating and the CLKOUT pin remains active. Thus, peripherals such as serial ports and timers can take the CPU out of its power-down state. Use the IDLE 1 instruction to enter the IDLE1 mode. To terminate IDLE1, use a wake-up interrupt. If INTM = 0 when the wake-up interrupt takes place, the
6-50

Power-Down Modes

54x enters the ISR when IDLE1 is terminated. If INTM = 1, the 54x continues with the instruction following the IDLE 1 instruction. All wake-up interrupts must set to enable the corresponding bits in the IMR register regardless of the INTM value. The only exceptions are the nonmaskable interrupts, RS and NMI.

6.11.2 IDLE2 Mode

The IDLE2 mode halts the on-chip peripherals as well as the CPU. Because the on-chip peripherals are stopped in this mode, they cannot be used to generate the interrupt to wake up the 54x as with IDLE1. However, power is significantly reduced because the device is completely stopped. Use the IDLE 2 instruction to enter the IDLE2 mode. To terminate IDLE2, activate any of the external interrupt pins (RS, NMI, and INTx) with a 10-ns minimum pulse. If INTM = 0 when the wake-up interrupt takes place, the 54x enters the ISR when IDLE2 is terminated. If INTM = 1, the 54x continues with the instruction following IDLE 2 instruction. All wake-up interrupts must be set to enable the corresponding bits in the IMR register regardless of the INTM value. Reset all peripherals when IDLE2 terminates, especially if they are externally clocked. When RS is the wake-up interrupt in IDLE2, a 10-ns minimum pulse of RS can activate the reset sequence.

6.11.3 IDLE3 Mode

The IDLE3 mode functions like IDLE2 but it also halts the PLL. IDLE3 is used for a complete shutdown of the 54x. This mode reduces power dissipation more than IDLE2. Furthermore, the IDLE3 state allows you to reconfigure the PLL externally if the system requires the 54x to operate at a lower speed to save power. Use the IDLE 3 instruction to enter the IDLE3 mode. To terminate IDLE3, activate any of the external interrupt pins (RS, NMI, and INTx) with a 10-ns minimum pulse. If INTM = 0 when the wake-up interrupt takes place, the 54x enters the ISR when IDLE3 is terminated. If INTM = 1, the 54x continues with the instruction following the IDLE 3 instruction. All wake-up interrupts should be set to enable the corresponding bits on the IMR register, regardless of the INTM value. Reset all peripherals when IDLE3 terminates, especially if they are externally clocked. To terminate IDLE3, the external interrupt must be a minimum of 10 ns to activate the wake-up sequence. The 54x can accept multiple interrupts during the wake-up sequence; the interrupt with highest priority is serviced first after IDLE3. See section 10.5.2, IDLE3, on page 10-26, and section 8.5.2, Software-Programmable PLL (Available on TMS320C545/546/548), on page 8-27 for more details on PLL lockup time requirements.
Program Memory Addressing
6-51

Power-Down Modes

When RS is the wake-up interrupt in IDLE3, a 10-ns minimum pulse of RS can activate the reset sequence. However, RS should be kept active for 50 ms so that the PLL can secure and provide stable system clock to internal logic.

6.11.4 Hold Mode

The Hold mode is another power-down mode. It enables you to put the address, data, and control lines into the high-impedance state. Depending on the value of the HM bit, you can also use this mode to halt the CPU. This power-down mode is initiated by the HOLD signal. The effect of HOLD depends on the value of HM. If HM = 1, the CPU stops executing and address, data, and control lines go into the high-impedance state for further power reduction. If HM = 0, the address, data, and control signals are put into the high-impedance state, but the CPU continues to execute internally. You can use HM = 0 with the HOLD signal when your system does not require externalmemory accesses. The 54x continues to operate normally unless an off-chip access is required by an instruction; then the processor halts until HOLD is released. This mode does not stop the operation of on-chip peripherals (such as timers and serial ports); they continue to operate regardless of the HOLD level or the condition of the HM bit. This mode is terminated when HOLD becomes inactive.

6.11.5 Other Power-Down Capabilities

The 54x has two other functions that affect the power-down operation: external bus off and CLKOUT off.

External bus off allows the 54x to disable the internal clock of external interfaces, thus placing the interface into a lower power-consumption mode. The external interface clock is disabled by setting bit 0 of the bank-switching control register (BSCR) to 1. At reset, this bit is cleared to 0 and the external interface clock is enabled. See section 10.3.2, Bank-Switching Logic, on page 10-8, for more information. CLKOUT off allows the 54x to disable CLKOUT using software instructions. The CLKOFF bit of PMST determines whether CLKOUT is enabled or disabled. See section 4.1.2, Processor Mode Status Register (PMST), on page 4-6. At reset, CLKOUT is enabled.

6-52

Chapter 7

Pipeline
This chapter describes the 54x pipeline operation and lists the pipeline latency cycles for operations with various registers.

Topic
7.1 7.2 7.3 7.4 7.5

Page
Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Interrupts and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 Dual-Access Memory and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 Single-Access Memory and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . 7-33 Pipeline Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35

Pipeline

7-1

Pipeline Operation

7.1 Pipeline Operation

The 54x CPU has a six-level deep instruction pipeline. The six stages of the pipeline are independent of each other, which allows overlapping execution of instructions. During any given cycle, from one to six different instructions can be active, each at a different stage of completion. The six levels and functions of the pipeline structure are:

Program prefetch. Program address bus (PAB) is loaded with the address of the next instruction to be fetched. Program fetch. An instruction word is fetched from the program bus (PB) and loaded into the instruction register (IR). This completes an instruction fetch sequence that consists of this and the previous cycle. Decode. The contents of the instruction register (IR) are decoded to determine the type of memory access operation and the control sequence at the data-address generation unit (DAGEN) and the CPU. Access. DAGEN outputs the read operands address on the data address bus, DAB. If a second operand is required, the other data address bus, CAB, is also loaded with an appropriate address. Auxiliary registers in indirect addressing mode and the stack pointer (SP) are also updated. This is considered the first of the 2-stage operand read sequence. Read. The read data operand(s), if any, are read from the data buses, DB and CB. This completes the two-stage operand read sequence. At the same time, the two-stage operand write sequence begins. The data address of the write operand, if any, is loaded into the data write address bus (EAB). For memory-mapped registers, the read data operand is read from memory and written into the selected memory-mapped registers using the DB. Execute. The operand write sequence is completed by writing the data using the data write bus (EB). The instruction is executed in this phase.

Figure 71 shows the six stages of the pipeline and the events that occur in each stage. The first two stages of the pipeline, prefetch and fetch, are the instruction fetch sequence. In one cycle, the address of a new instruction is loaded. In the following cycle, an instruction word is read. In case of multiword instructions, several such instruction fetch sequences are needed.
7-2

Pipeline Operation

Figure 71. Pipeline Stages

Loads PAB with the PCs contents Loads IR with the contents of PB Decodes the IRs contents Loads DB with the data1 read operand Loads CB with the data2 read operand Loads EAB with the data3 write address, if required

Prefetch

Fetch

Decode

Access

Read

Execute/write

Loads PB with the fetched instruction word

Loads DAB with the data1 read address, if required Loads CAB with the data2 read address, if required Updates auxiliary registers and stack pointer Time

Executes the instruction and loads EB with write data

During the third stage of the pipeline, decode, the fetched instruction is decoded so that appropriate control sequences are activated for proper execution of the instruction. The next two pipeline stages, access and read, are an operand read sequence. If required by the instruction, the data address of one or two operands are loaded in the access phase and the operand or operands are read in the following read phase. Any write operation is spread over two stages of the pipeline, the read and execute stages. During the read phase, the data address of the write operand is loaded onto EAB. In the following cycle, the operand is written to memory using EB. Each memory access is performed in two phases by the 54x pipeline. In the first phase, an address bus is loaded with the memory address. In the second phase, a corresponding data bus reads from or writes to that memory address. Figure 72 shows how various memory accesses are performed by the 54x pipeline. It is assumed that all memory accesses in the figure are performed by single-cycle, single-word instructions to on-chip dual-access memory. The on-chip dual-access memory can actually support two accesses in a single pipeline cycle. This is discussed in section 7.3, Dual-Access Memory and the Pipeline, on page 7-27.
Pipeline
7-3


7-4

Pipeline Operation

(f) Instruction performing operand read and operand write (for example, ST A, *AR2 || LD *AR3, B; one cycle)

(e) Instruction performing dual-operand write, (for example, DST A, *AR1; two cycles)

(d) Instruction performing single-operand write (for example, STH A, *AR1; one cycle)

(c) Instruction performing dual-operand read (for example, MAC *AR2+, *AR3+, A or DLD *AR2, A; one cycle)

(b) Instruction performing single operand read (for example, LD *AR1, A; one cycle)

(a) Instruction word fetch (one cycle)

Figure 72. Pipelined Memory Accesses

Prefetch

Load PAB

Prefetch Prefetch Prefetch Prefetch Prefetch Prefetch Fetch

Read from PB

Decode

Fetch Fetch Fetch Fetch Fetch Fetch

Decode Decode Decode Decode Decode Decode Access

Load DAB Load DAB and CAB Load DAB Load EAB
Access Access Access Access Access Access Read

Read from DB and CB

Read from DB

Read from DB Loads EAB Write to EAB Load EAB Load EAB
Execute Read Read Read Read Read Read

Execute/Write Execute/Write Execute/Write Execute/Write Execute/Write Execute/Write

Write to EB Write to EB Write to EB

Pipeline Operation

The following sections provide examples that demonstrate how the pipeline works while executing different types of instructions. Unless otherwise noted, all instructions shown in the examples are considered single-cycle, singleword instructions residing in on-chip memory. The pipeline is depicted in these examples as a set of staggered rows in which each row corresponds to one instruction word moving through the stages of the pipeline. Example 71 is a sample pipeline diagram.

Example 71. Sample Pipeline Diagram

Address a1, a2 a3 a4 ... b1 1
Prefetch

Instruction B b1 This is a four-cycle, two-word branch instruction i3 This is any one-cycle, one-word instruction i4 This is any one cycle, one-word instruction ... j1 3 4 5 6 7 8
Decode Access Read Execute

10

Fetch

PAB = a1

PB = B

IR = B
Fetch

Prefetch

Decode

Access

Read

Execute

b1

PAB = a2

PB = b1
Prefetch

IR = b1
Fetch

b1

Decode

Access

Read

Execute

Pipeline flush

PAB = a3

PB = i3

Prefetch

Fetch

Decode

Access

Read

Execute

Pipeline flush

PAB = a4

PB = i4

Prefetch

Fetch

Decode

Access

Read

Execute

j1

PAB = b1

PB = j1

IR = j1

j1

Each row in the example is labeled on the left as an instruction, an operand, a multicycle instruction, or a pipeline flush. The numbers across the top represent single instruction cycles. Some cycles do not show all pipeline stages this is done intentionally to avoid displaying unnecessary information.

Each box in the example contains relevant actions that occur at that pipeline stage. The name of each pipeline stage is shown above the box in which the action occurs. Shading represents all instruction fetches and pipeline flushes that are necessary to complete the instruction whose operation is shown.
Pipeline
7-5

Pipeline Operation

7.1.1

Branch Instructions in the Pipeline

Example 72 and Example 73 show the pipelines behavior during the execution of a branch (B) instruction and a delayed-branch (BD) instruction, respectively. Because a branch instruction consists of two instruction words, it should take at least two instruction cycles to execute completely. However, a standard branch instruction actually takes four cycles to execute. This is illustrated in Example 72.

Example 72. Branch Instruction in the Pipeline

Address a1, a2 a3 a4 ... b1 1
Prefetch

Instruction B b1 i3 i4 ... j1 3
Decode

10

Fetch

Access

Read

Execute

PAB = a1

PB = B

IR = B
Fetch

Prefetch

Decode

Access

Read

Execute

b1

PAB = a2

PB = b1
Prefetch

IR = b1
Fetch

b1

Decode

Access

Read

Execute

Pipeline flush

PAB = a3

PB = i3

Prefetch

Fetch

Decode

Access

Read

Execute

Pipeline flush

PAB = a4

PB = i4

Prefetch

Fetch

Decode

Access

Read

Execute

j1

PAB = b1

PB = j1

IR = j1

j1

For the branch instruction in Example 72 to execute completely, the following events occur: Cycle 1: Cycles 2 and 3: The PAB is loaded with the address of a branch instruction. Two words of the branch instruction are fetched.

7-6

Pipeline Operation

Cycles 4 and 5:

Two more instructions, i3 and i4, are fetched. Although the two instructions after the branch instruction, i3 and i4, are fetched by the 54x, they are not allowed to move past the decode stage and are eventually discarded. After the second word of the branch instruction (represented by b1 in the left column) is decoded, PAB is loaded with this new value (in cycle 5). The two-word branch instruction enters the execution stage of the pipeline in cycles 6 and 7. Also, j1 is fetched from address b1 in cycle 6. These cycles are also consumed by the same branch instruction since the next two instructions, i3 and i4, were not allowed to complete their execution; this is why a branch instruction takes four cycles to execute. j1 completes execution.

Cycles 6 and 7:

Cycles 8 and 9:

Cycle 10:

Example 73 shows the pipelines behavior for a delayed-branch instruction.

Example 73. Delayed-Branch Instruction in the Pipeline

Address a1, a2 a3 a4 ... b1 1
Prefetch

Instruction BD b1 i3 i4 ... j1 3
Decode

10

Fetch

Access

Read

Execute

BD

PAB = a1

PB = BD
Prefetch

IR = BD
Fetch

BD

Decode

Access

Read

Execute

b1

PAB = a2

PB = b1
Prefetch

IR = b1
Fetch

b1

Decode

Access

Read

Execute

i3

PAB = a3

PB = i3

i3

Prefetch

Fetch

Decode

Access

Read

Execute

i4

PAB = a4

PB = i4

i4

Prefetch

Fetch

Decode

Access

Read

Execute

j1

PAB = b1

PB = j1

IR = j1

j1

Pipeline

7-7

Pipeline Operation

In this case, the pipeline behaves in the same manner as it did for the regular branch instruction. However, the two instructions following the branch, i3 and i4, are allowed to complete their execution. Therefore, only cycles 6 and 7 are consumed by the delayed-branch instruction, making the delayed branch into a 2-cycle instruction.

7.1.2

Call Instructions in the Pipeline

A standard call instruction takes four cycles to execute. Although a standard call is a two-word instruction and seems to need only two cycles, it actually flushes the pipeline for two cycles, taking four cycles to execute. Example 74 shows the pipelines behavior during the execution of a call instruction.

Example 74. Call Instruction in the Pipeline

Address a1, a2 a3 a4 ... b1 1
Prefetch

Instruction CALL b1 i3 i4 ... j1 3

10

Fetch

Decode

Access

Read

Execute

CALL

PAB = a1

PB = CALL

IR = CALL
Fetch

SP

EAB = SP EB = RTN RTN = a3

Access Read

Prefetch

Decode

Execute

b1

PAB = a2

PB = b1
Prefetch

IR = b1
Fetch

b1

Decode

Access

Read

Execute

Pipeline flush

PAB = a3

PB = i3

Prefetch

Fetch

Decode

Access

Read

Execute

Pipeline flush

PAB = a4

PB = i4

Prefetch

Fetch

Decode

Access

Read

Execute

j1

PAB = b1

PB = j1

IR = j1

j1

7-8

Pipeline Operation

In Example 74, the following events occur: Cycle 1: Cycles 2 and 3: Cycle 4: PAB is loaded with the address of the call instruction. Two words of the call instruction are fetched. SP is decremented (represented by SP ), because the return address is placed on the stack. The instruction i3 is fetched; however, it is not allowed to move past the decode stage. The write address bus (EAB) is loaded with SPs contents and the on-chip return register (RTN) is loaded with the return address, a3. After the second word of the call instruction (b1) is decoded, PAB is loaded with the new value in cycle 5 (shown in row j1). The RTN contents are written to the stack using EB in cycle 6. The instruction, j1, at address b1 is fetched in cycle 6. The two-word call instruction enters the execution stage of the pipeline in cycles 6 and 7. These cycles are consumed by the call instruction, because the next two instructions are not allowed to complete their execution. j1 completes execution.

Cycle 5:

Cycles 6 and 7:

Cycles 8 and 9:

Cycle 10:

Pipeline

7-9


Pipeline Operation

7-10

Example 75. Delayed-Call Instruction in the Pipeline

j1

i4

i3

b1

CALLD PAB = a1

Address a1, a2 a3 a4 ... b1

Prefetch

PAB = a2

Prefetch

PB = CALLD

Fetch

In this case, the pipeline behaves in the same manner as with the normal call instruction. However, in this case the following two instructions, i3 and i4, are allowed to complete their execution. Therefore, only cycles 6 and 7 are consumed by the delayed-call instruction, making it a 2-cycle instruction. Example 75 shows the pipeline behavior for a delayed-call instruction.
PAB = a3 PB = b1
Prefetch

IR = CALLD

Instruction CALLD b1 i3 i4 ... j1

Decode

Fetch

PAB = a4

Prefetch

PB = i3

IR = b1

Decode

Access

SP

Fetch

EAB = SP EB = RTN RTN = a3

PAB = b1
Prefetch

PB = i4

Decode

IR = i3

Access

Fetch

Read

PB = j1
Execute Decode

IR = i4

Access

Fetch Read

Execute

Decode Access Read

IR = j1 b1

Execute

Access Read

i3

Execute

Read

i4

Execute

10

j1


Example 76. INTR Instruction in the Pipeline
j1 Pipeline flush Pipeline flush INTR
PAB = a1

Address a1, a2 a3 a4 ... vect

Prefetch

PB = INTR

PAB = a2

Prefetch

Fetch

The INTR instruction behaves like a CALL instruction. However, because INTR is a 1-word instruction, it can compute the vector table address and prefetch it one cycle earlier. As shown in Example 76, INTR takes only three cycles to execute.

Instruction INTR n i2 i3 ... j1

IR = INTR RTN = a2

PAB = a3

Prefetch

PB = i2

Decode

Fetch

PAB = vect

Prefetch

PB = i3

Decode

Access

SP

Fetch

EAB = SP

PB = j1

Decode

Access

Fetch

Read

EB = RTN

Execute

Decode

Access

Read

Execute

Access

Read

Pipeline
Execute Read

Pipeline Operation

Execute

j1

7-11


Example 77. Return Instruction in the Pipeline
j1 Dummy cycle Dummy cycle Pipeline flush Pipeline flush RET PAB = a1 Address a1 a2 a3 ... b1
Prefetch

7-12

Pipeline Operation

7.1.3

Return Instructions in the Pipeline

PAB = a2

Prefetch

Fetch

PB = RET

PAB = a3

Because a return is a single-word instruction, you would expect it to take at least one cycle to completely execute. In reality, a standard return instruction takes five cycles to execute. Example 77 shows the pipelines behavior during the execution of a return instruction.

Prefetch

PB = i2

Decode

Fetch

IR = RET

Instruction RET i2 i3 ... j1

SP++ DAB=SP

No prefetch

Prefetch

PB = i3

Decode

Access

Fetch

DB = b1

No prefetch

Prefetch

Decode

Access

Fetch

No fetch

Read

PAB = b1 PB = j1
Prefetch Execute Decode Access Fetch

No fetch

Read

RET

Execute

Decode

Access

Fetch Read

Execute

Decode Access Read

Execute

Access Read

Execute

Read

10

Execute

11

j1

Pipeline Operation

In Example 77, the following events occur: Cycle 1: Cycle 2: Cycles 3 and 4: The PAB is loaded with the address of the return instruction. The return instruction opcode is fetched. Two more instructions, i2 and i3, are fetched. Although these two instructions are fetched by the device, they are not allowed to move past the decode stage and are discarded. In cycle 4, SP is incremented (represented by SP ++) and DAB is loaded with the contents of SP in order to read the return address from the stack. The top of the stack is read using DB. The return instruction enters the execution stage of the pipeline. The address fetched from the stack is loaded onto PAB. This allows for fetching the next instruction, j1, from the return address. These cycles are consumed by the return instruction, because the next two instructions, i3 and i4, do not complete their execution.

Cycle 5: Cycle 6:

Cycles 7 and 8:

Cycles 9 and 10: Because no instructions were fetched in cycles 4 and 5, cycles 9 and 10 are dummy cycles. Cycle 11 j1 completes execution.

Pipeline

7-13


Example 78. Delayed-Return Instruction in the Pipeline
j1 i3 i2 Pipeline flush Pipeline flush RETD
Prefetch

7-14

Pipeline Operation

Address a1 a2 a3 ... b1

PAB = a1

Prefetch

PAB = a2

PB = RETD

Fetch

In a delayed-return instruction, the 54x pipeline behaves in the same way as with the normal return instruction. However, the following two instructions, i3 and i4, are allowed to complete their execution, so only cycles 6, 7, and 8 are consumed by the delayed-return instruction, making it a 3-cycle instruction as shown in Example 78.

Example 78 shows the pipelines behavior during the execution of a delayedreturn instruction.

Prefetch

PB = i2

Decode

PAB = a3

IR = RETD

Fetch

Instruction RETD i2 i3 ... j1

SP++ DAB = SP

No prefetch

Prefetch

Decode

PB= i3

Access

Fetch

DB = b1

No prefetch

Prefetch

Decode

Access

Fetch

No fetch

Read

PAB = b1 PB = j1
Prefetch Execute Decode

IR = i2

Access

RETD

Fetch

No fetch

Read

Execute

Decode

IR = i3

Access

Fetch Read

Execute

Decode Access Read

Execute

Access Read

i2

Execute

Read

10

i3

Execute

11

j1

Pipeline Operation

Example 79 and Example 710 show the pipeline behavior for a return-withinterrupt-enable (RETE) instruction and a delayed return-with-interruptenable (RETED) instruction, respectively. The pipeline behavior for these instructions is similar to that of the standard return and delayed-return instructions, respectively, and these instructions also take same number of cycles to execute. The difference is that these two instructions enable interrupts globally by resetting the INTM bit during the execute stage of the pipeline.

Example 79. Return-With-Interrupt-Enable Instruction in the Pipeline

Address a1 a2 a3 ... b1 1
Prefetch

Instruction RETE i2 i3 ... j1 3 4

10

11

Fetch

Decode

Access

Read

Execute

RETE

PAB = a1

PB = RETE

IR = RETE
Fetch

SP++ DAB = SP
Decode

DB = b1
Access

INTM = 0
Read

Prefetch

Execute

Pipeline flush

PAB = a2

PB = i2

Prefetch

Fetch

Decode

Access

Read

Execute

Pipeline flush

PAB = a3

PB = i3

Prefetch

Fetch

Decode

Access

Read

Execute

Dummy cycle

No prefetch

No fetch

Prefetch

Fetch

Decode

Access

Read

Execute

Dummy cycle

No prefetch

No fetch

Prefetch

Fetch

Decode

Access

Read

Execute

j1

PAB = b1 PB = j1

j1

Pipeline

7-15


Pipeline Operation

7-16

Example 710. Delayed Return-With-Interrupt-Enable Instruction in the Pipeline

j1 i3 i2

Pipeline flush

Pipeline flush

RETED

Address a1 a2 a3 ... b1

Prefetch

PAB = a1

PB = RETED

Prefetch

PAB = a2

Fetch

IR = RETED

Prefetch

PB = i2

Decode

PAB = a3

Fetch

Instruction RETED i2 i3 ... j1

SP++ DAB = SP

No prefetch

Prefetch

PB = i3

Decode

Access

Fetch

DB = b1

No prefetch

Prefetch

Decode

Access

Fetch

No fetch

Read

INTM = 0

Prefetch Execute Decode

IR = i2

Access

PAB = b1
Fetch

No fetch

Read

PB = j1
Execute Decode

IR = i3

Access

Fetch Read

Execute

Decode Access Read

Execute

Access Read

i2

Execute

Read

10

i3

Execute

11

j1

Pipeline Operation

Example 711 and Example 712 show pipeline behavior for a return-fast (RETF) instruction and for a delayed return-fast (RETFD) instruction, respectively. The RETF instruction, unlike the RETE instruction, does not read the return address from the stack. Instead, it reads it from the RTN register. This allows the instruction to load PAB with the return address two cycles earlier than a RETE instruction can. As shown in the examples, the RETF instruction takes only three cycles to execute; the delayed version of the instruction, RETFD, executes in one cycle.

Address a1 a2 a3 ... b1 1
Prefetch

Example 711. Return-Fast Instruction in the Pipeline

Instruction RETF i2 i3 ... j1 3
Decode

Fetch

Access

Read

Execute

RETF

PAB = a1

PB = RETF

IR = RETF
Fetch

SP++ Read RTN

Decode

INTM = 0
Read

Prefetch

Access

Execute

Pipeline flush

PAB = a2

PB = i2

Prefetch

Fetch

Decode

Access

Read

Execute

Pipeline flush

PAB = a3

PB = i3

Prefetch

Fetch

Decode

Access

Read

Execute

j1

PAB = b1

PB = j1

j1

Pipeline

7-17


Pipeline Operation

7-18

Example 712. Delayed Return-Fast Instruction in the Pipeline

j1 i3 i2

RETFD

Address a1 a2 a3 ... b1

PAB = a1

Prefetch

PAB = a2

Prefetch

PB = RETFD

Fetch

Instruction RETFD i2 i3 ... j1

PAB = a3

IR = RETFD

Prefetch

PB = i2

Decode

Fetch

SP++ Read RTN

PAB = b1
Prefetch

PB = i3

Decode

Access

Fetch

PB = j1
Decode Access Fetch Read

INTM = 0

Execute

Decode Access Read

Execute

Access Read

i2

Execute

Read

i3

Execute

j1

Pipeline Operation

7.1.4

Conditional Execute Instructions in the Pipeline

Because XC is single-word instruction, it takes at least one instruction cycle to completely execute. Example 713 shows pipeline behavior during the execution of XC.

Example 713. XC Instruction in the Pipeline

Address a1 a2 a3 a4 a5 a6 1
Prefetch

Instruction i1 i2 i3 XC 2, cond i5 i6 3

10

11

Fetch

Decode

Access

Read

Execute

i1

PAB = a1

PB = i1

IR = i1
Fetch

i1

Prefetch

Decode

Access

Read

Execute

i2

PAB= a2

PB = i2

IR = i2
Fetch

i2

Prefetch

Decode

Access

Read

Execute

i3

PAB = a3

PB = i3

IR = i3
Fetch

i3

Prefetch

Decode

Access

Read

Execute

XC

PAB = a4

PB = XC
Prefetch

IR = XC
Fetch

Evaluate
Decode

Access

Read

Execute

i5 or NOP

PAB = a5

PB = i5

Conditional execution of i5
Decode Access

Prefetch

Fetch

Read

Execute

i6 or NOP

PAB = a6

PB = i6

Conditional execution of i6

In Example 713, the following events occur: Cycle 4: Cycle 5: Cycle 7:

The PAB is loaded with the address of the XC instruction. The XC instruction opcode is fetched. When the XC instruction moves into the access stage of the pipeline in cycle 7, any conditions specified by the XC instruction are evaluated. If the tested conditions are true, the next two instructions, i5 and i6, are decoded and allowed to execute. However, if the tested conditions are false, i5 and i6 are not decoded.

Pipeline

7-19

Pipeline Operation

To execute XC in one cycle, the CPU evaluates test conditions in the access stage of the pipeline. This means that the two 1-word instructions (or one 2-word instruction) immediately prior to the XC instruction will not have completely executed before the conditions are tested. Because the condition codes are affected only by instructions in the execute stage, those two instructions have no effect on the operation of XC.

7.1.5

Conditional-Call and Conditional-Branch Instructions in the Pipeline

Because a call instruction consists of two instruction words, you would expect it to take at least two cycles to execute completely. A standard conditional-call instruction actually takes either five cycles to execute if the call is taken or three cycles to execute if the call is not taken. Example 714 shows pipeline behavior during the execution of a conditionalcall instruction (CC). A conditional-call instruction is similar in its pipeline behavior to an unconditional-call instruction. The only exception is that the test conditions for a conditional-call instruction are evaluated in the execute stage of the pipeline. As shown in Example 714, when the test conditions are evaluated in cycle 7, the previous instruction, i1, has completely executed. Furthermore, the next two instructions after CC, i4 and i5, are also fetched. If the test conditions are evaluated to be false, these two instructions proceed through the pipeline. Otherwise, they are discarded. The instruction prefetch in cycle 7 is also dependent on the evaluated conditions. If the conditions are true, PAB is loaded with the call address (b1); otherwise, it is loaded with the next incremental address (a6). If the evaluated conditions are true, i4 and i5 do not execute in cycles 10 and 11. In this case, the CC instruction becomes a 5-cycle instruction. However, if the evaluated conditions are false, i4 and i5 execute, making CC a 3-cycle instruction. Example 715 shows pipeline behavior during the execution of a delayed conditional-call (CCD) instruction. The pipeline behaves in the same manner as it does for the CC instruction. However, the following two instructions, i3 and i4, are allowed to complete their execution regardless of whether the tested conditions are true or not. Only cycles 7, 8, and 9 are consumed by the CCD instruction, making it a 3-cycle instruction.

7-20

Pipeline Operation

Example 714. CC Instruction in the Pipeline

Address a1 a2,a3 a4 a5 a6 ... b1
1 Prefetch i1 PAB = a1 2 Fetch PB = i1

Instruction i1 CC b1, cond i4 i5 i6 ... j1

3 Decode IR = i1 4 Access 5 Read 6 Execute i1 7 8 9 10 11 12

Prefetch CC PAB = a2

Fetch PB = CC

Decode IR = CC

Access SP

Read EAB = SP RTN = a4 Access

Execute EB = RTN Evaluate Read Execute

Prefetch b1 PAB = a3

Fetch PB = b1

Decode IR = b1

Prefetch Pipeline flush PAB = a4

Fetch PB = i4

Decode IR = i4

Access

Read

Execute

Prefetch i4 or pipeline flush No prefetch

Fetch No fetch Prefetch

Decode

Access

Read

Execute

IR = i4 and conditional execution of i4

Fetch PB = i5

Decode

Access

Read

Execute

i5 or pipeline flush

PAB = a5

IR = i5 and conditional execution of i5

Prefetch i6 or j1 PAB = a6 or b1

Fetch PB = i6 or j1

Decode IR = i6 or j1

Access

Read

Execute i6 or j1

Pipeline

7-21

Pipeline Operation

Example 715. CCD Instruction in the Pipeline

Address a1 a2, a3 a4 a5 a6 : b1
1 Prefetch i1 PAB = a1 2 Fetch PB = i1

Instruction i1 CCD b1, cond i4 i5 i6 : j1

3 Decode IR = i1 4 Access 5 Read 6 Execute i1 7 8 9 10 11 12

Prefetch CCD PAB = a2

Fetch PB = CCD

Decode IR = CCD

Access SP

Read EAB = SP RTN = a4

Execute EB = RTN Evaluate Read Execute

Prefetch b1 PAB = a3

Fetch PB = b1

Decode IR = b1

Access

Prefetch Pipeline flush PAB = a4

Fetch PB = i4 Prefetch

Decode IR = i4 Fetch No fetch Prefetch

Access

Read

Execute

Decode IR = i4 Fetch PB = i5 Prefetch

Access

Read

Execute i4

i4

No prefetch

Decode IR = i5 Fetch PB = i6 or j1

Access

Read

Execute i5

i5

PAB = a5

Decode IR = i6 or j1

Access

Read

Execute i6 or j1

i6 or j1

PAB = a6 or b1

Example 716 and Example 717 show the pipelines behavior during the execution of a conditional branch (BC) instruction and a delayed conditional branch (BCD) instruction.

The behavior of the conditional branch (BC) and the delayed conditional branch (BCD) instructions in the pipeline is similar to that of the CC and CCD instructions, respectively. The difference is that no return address is written to the stack in this case. As shown in Example 716, a BC instruction takes either three or five cycles to execute, depending on whether or not the branch is taken. A BCD instruction executes in three cycles.
7-22

Pipeline Operation

Example 716. BC Instruction in the Pipeline

Address a1 a2,a3 a4 a5 a6 ... b1
1 Prefetch i1 PAB = a1 2 Fetch PB = i1

Instruction i1 BC b1, cond i4 i5 i6 ... j1

3 Decode IR = i1 4 Access 5 Read 6 Execute i1 7 8 9 10 11 12

Prefetch BC PAB = a2

Fetch PB = BC Prefetch

Decode IR = BC Fetch PB = b1 Prefetch

Access

Read

Execute Evaluate

Decode IR = b1 Fetch PB = i4 Prefetch

Access

Read

Execute

b1

PAB = a3

Decode

Access

Read

Execute

Pipeline flush

PAB = a4

Fetch No fetch Prefetch

Decode

Access

Read

Execute

i4 or pipeline flush

No prefetch

IR = i4 and conditional execution of i4 Fetch PB = i5 Prefetch Decode Access Read Execute

i5 or pipeline flush

PAB = a5

IR = i5 and conditional execution of i5 Fetch PB = i6 or j1 Decode IR = i6 or j1 Access Read Execute i6 or j1

i6 or j1

PAB = a6 or b1

Pipeline

7-23

Pipeline Operation

Example 717. BCD Instruction in the Pipeline

Address a1 a2,a3 a4 a5 a6 ... b1
1 Prefetch i1 PAB = a1 2 Fetch PB = i1

Instruction i1 BCD b1, cond i4 i5 i6 ... j1

3 Decode IR = i1 4 Access 5 Read 6 Execute i1 7 8 9 10 11 12

Prefetch BCD PAB = a2

Fetch PB = BCD Prefetch

Decode IR = BCD Fetch PB = b1 Prefetch

Access

Read

Execute Evaluate

Decode IR = b1 Fetch PB = i4 Prefetch

Access

Read

Execute

b1

PAB = a3

Decode IR = i4 Fetch No fetch Prefetch

Access

Read

Execute

Pipeline flush

PAB = a4

Decode IR = i4 Fetch PB = i5 Prefetch

Access

Read

Execute i4

i4

No prefetch

Decode IR = i5 Fetch PB = i6 or j1

Access

Read

Execute i5

i5

PAB = a5

Decode IR = i6 or j1

Access

Read

Execute i6 or j1

i6 or j1

PAB = a6 or b1

7-24

Interrupts and the Pipeline

7.2 Interrupts and the Pipeline

Example 718 shows the pipeline behavior when an interrupt is taken. As shown in Example 718, if an interrupt is serviced at the end of cycle 3, an INTR instruction is automatically placed into the decode stage of the pipeline during the next cycle (4). The instruction, i2, is not decoded because the INTR instruction is placed into the pipeline at that stage. During the next three cycles, the instructions that have already been decoded are executed. Cycles 7, 8, and 9 are taken by the INTR instruction. The first instruction in the ISR, RETFD, is executed in cycle 10. Cycles 11 and 12 are consumed by the two 1-word instructions that constitute the two delay slots of the RETFD instruction. In the following cycle, instruction i2 is executed, completing the return from the ISR. As shown in the figure, interrupt overhead (the number of cycles required to branch to an ISR) is only three cycles. The return from the interrupt takes only one cycle because RETFD is a single-cycle instruction. Because only four words are reserved for each interrupt in the interrupt vector table, if an ISR requires more than four instruction words, it must be located elsewhere. In this case, a branch type instruction in the interrupt vector table. This would result in a slightly higher interrupt overhead.

Pipeline

7-25

Interrupts and the Pipeline

Example 718. Interrupt Response by the Pipeline

Address a1 a2 a3 a4 : vect1 vect2 vect3
1 Prefetch i1 PAB = a1 2 Fetch PB = i1 Prefetch INTR (inserted) PAB = a2 3 Decode IR = i1 Fetch PB = i2 Prefetch Pipeline flush PAB = a3 Decode IR = INTR RTN = a2 Fetch PB = i3 Prefetch Pipeline flush PAB = a4 Fetch PB = i4 Prefetch RETFD PAB = vect1 Fetch PB = RETFD Prefetch j1 PAB = vect2 Decode IR = RETFD Fetch PB = j1 Prefetch j2 PAB = vect3 Access SP++ Rd RTN Decode IR = j1 Fetch PB = j2 Prefetch i2 PAB = a2 Decode IR = j2 Fetch PB= i2 Decode IR = i2 Access Access Access Read Execute INTM = 0 Read Execute j1 Read Execute j2 Read Execute i2 Decode Access Read Execute Access SP Decode

Instruction i1 i2 i3 i4 : RETFD j1 j2
4 Access

; Interrupt taken after executing this instruction

; First instruction in the interrupt vector table

5 Read

6 Execute i1 Read EAB = SP Access

10

11

12

13

Execute EB = RTN Read Execute

7-26

Dual-Access Memory and the Pipeline

7.3 Dual-Access Memory and the Pipeline

The 54x features on-chip memory that supports two accesses in a single cycle. This dual-access memory is organized as several independent memory blocks. Simultaneous accesses to different blocks are supported with no conflicts: while one instruction in the pipeline accesses one block, another instruction at the same stage in the pipeline can access a different block without conflict. Furthermore, each memory block supports two accesses in a single cycle: two instructions, each in different stages of the pipeline, can access the same block simultaneously. However, a conflict can occur when two simultaneous accesses are performed on the same block. The 54x CPU resolves these conflicts automatically; this is discussed later in this section. Table 71 shows the block size and number of blocks for each 54x device. For more information about DARAM organization, see section 3.3.2, On-Chip RAM Organization, on page 3-23.

Table 71. DARAM Blocks

Device 541 542 543 545 546 548 549 5402 5410 5420 (each subsystem) Block Size 1K words 2K words 2K words 2K words 2K words 2K words 2K words 8K words 2K words 8K words Number of Blocks 5 5 5 3 3 4 4 2 4 2

Note that the first block is slightly smaller due to the memory-mapped registers and the scratchpad RAM.

Each dual-access memory block supports two accesses in one cycle by performing one access in the first half-cycle and the other in the next half-cycle. Table 72 lists the accesses performed in each half-cycle, and Figure 73 shows how the different types are performed. Address bus loads are omitted from the diagram for simplicity.
Pipeline
7-27

Dual-Access Memory and the Pipeline

Table 72. Accessing DARAM Blocks

This type of access ... Instruction fetch using PAB/PB First data operand read using DAB/DB Second data operand read using CAB/CB Data operand write using EAB/EB Is performed in the ... First half-cycle First half-cycle Second half-cycle Second half-cycle

Figure 73. Half-Cycle Accesses to Dual-Access Memory

(a) Instruction word fetch
Prefetch Fetch Read PB Decode Access Read Execute

(b) Instruction performing single-operand read

Prefetch Fetch Decode Access Read Read DB Execute

(c) Instruction performing dual-operand read

Prefetch Fetch Decode Access Read CB Read Read DB Execute

(d) Instruction performing single-operand write

Prefetch Fetch Decode Access Read Execute Write EB

7-28

Dual-Access Memory and the Pipeline

(e) Instruction performing dual-operand write (two cycles)

Prefetch Fetch Decode Access Read Execute Write EB Prefetch Fetch Decode Access Read Execute Write EB

(f) Instruction performing operand read and operand write

Prefetch Fetch Decode Access Read Read DB Execute Write EB

Because two types of access are scheduled and only one access is performed in each half-cycle, conflicts can occur. These conflicts are automatically resolved by the CPU either by rearranging the order of accesses or by delaying an access by one cycle. The following sections describe these resolved memory access conflicts. Keep in mind that these conflicts appear only if all accesses are being performed on the same dual-access memory block.

7.3.1

Resolved Conflict Between Instruction Fetch and Operand Read

If a dual-access memory block is mapped in both program and data spaces, an instruction fetch will conflict with a data operand read access if they are performed on the same memory block. The 54x resolves this conflict automatically by delaying the instruction fetch by one cycle, as shown in Example 719. In the figure, it is assumed that instructions i2 and i3 do not access the dual-access memory block where the code resides.

Pipeline

7-29

Dual-Access Memory and the Pipeline

Example 719. Instruction Fetch and Operand Read

LD *AR2+, A; i2 i3 i4 Prefetch LD*AR2+, A Prefetch i2 Fetch Read PB Prefetch i3 Fetch Read PB Decode Access Read Execute Decode AR2 is pointing to the same DARAM block where the code resides.

Fetch

Decode

Access

Read Read DB Access

Execute

Read

Execute

Dummy cycle (instruction fetch is supposed to occur here)

i4 (delayed instruction fetch)

Legend:

Where instruction fetch is supposed to occur

7.3.2

Resolved Conflict Between Operand Write and Dual-Operand Read

Another conflict arises if a single-operand write instruction is followed by an instruction that does not perform a write access and this instruction is followed by a dual-operand read instruction. This is shown in Example 720, in which AR3 and AR5 point to the same dual-access memory block. There is a conflict between the operand write access (EB bus) and the second data read access (CB bus). This conflict is resolved automatically by delaying the write access by one cycle. The actual execution time of these instructions does not increase, because the delayed write access is performed while the second instruction is in the execute stage. If any read access (via DB or CB) is from the same memory location in on-chip memory where the write access should occur, the CPU bypasses reading the actual memory location; instead, it reads the data directly from an internal bus. This allows the pipeline to perform a write access in a later pipeline stage than that in which the next instruction reads from the same memory location.

7-30

Read PB Prefetch

Prefetch

Fetch

Decode

Access

Read

Execute

Fetch

Decode

Access

Read

Execute

Read PB

Where a memory access actually occurs

Dual-Access Memory and the Pipeline

Example 720. Operand Write and Dual-Operand Read Conflict

STL A, *AR3+ LD #0, A ADD *AR4+, *AR5+, A

; AR3 and AR5 both point to the same dual-access memory block. Prefetch Fetch Decode Access Read Execute Write EB

STL A, *AR3+ (write access delayed until next cycle)

Prefetch LD #0, A (write access of previous instruction occurs here)

Fetch

Decode

Access

Prefetch ADD *AR4+, AR5, A

Fetch

Decode

Legend:

Where an access is supposed to occur

Where an access actually occurs

7.3.3

Resolved Conflict Among Operand Write, Operand Write, and Dual-Operand Read
If the second instruction in the case described above is an operand-write type instruction, then the write access requested by the first instruction cannot be moved to the next cycle. The CPU resolves the conflict by inserting a dummy cycle after the first instruction. This is illustrated in Example 721, in which AR3 and AR5 point to the same dual-access memory block.

Read Access Read CB

Execute

Write EB

Read Read DB

Execute

Pipeline

7-31

Dual-Access Memory and the Pipeline

Example 721. Operand Write and Operand Read Conflict

STL A, *AR3+ STH A, *AR2 ADD *AR4+, *AR5+, A

; AR3 and AR5 both point to the same dual-access memory block Prefetch Fetch Decode Access Read Execute Write EB

STL A, *AR3+

Prefetch Dummy cycle

Fetch

Decode

Access

Read

Execute

Prefetch STH A, *AR2

Fetch

Decode

Access

Read

Execute Write EB

Prefetch ADD *AR4+, *AR5+, A

Fetch

Decode

Access Read CB

Read Read DB

Execute

Legend:

Where read or write occurs

7-32

Single-Access Memory and the Pipeline

7.4 Single-Access Memory and the Pipeline

The 54x also features on-chip single-access memory that supports one access per cycle to each memory block. There are two different types of singleaccess memory that are available on 54x devices:

Single access read-write memory (SARAM) Single-access read-only memory (ROM or DROM)

Both types of single-access memory behave similarly in terms of pipelined accesses, with the exception that ROM and DROM cannot be written to. These memory blocks are contiguous in memory with the first block beginning at the start address of SARAM or ROM. For more information about memory blocking, see section 3.2.2, On-Chip ROM Organization, on page 3-17, and section 3.3.2, On-Chip RAM Organization, on page 3-23. Simultaneous accesses with no conflicts are supported by single-access memory as long as the access are to different memory blocks; while one instruction in a pipeline stage accesses one memory block, another instruction can access a different memory block in the same cycle without any conflict. A conflict can occur when two simultaneous accesses are performed on the same memory block. In case of such a conflict, only one access is performed in that cycle and the second access is delayed until the following cycle. This results in a one-cycle pipeline latency. A pipeline conflict due to single access memory may occur in several different situations.

Dual-Operand instructions. Many instructions have two memory operands to read or write data. If both operands are pointing to the same singleaccess memory block, a pipeline conflict occurs. The CPU automatically delays the execution of that instruction by one cycle to resolve the conflict. For example:
MAC *AR2+, *AR3+%,A,B ; This instruction will take two ; cycles if both operands are in ; same SARAM or DROM block.

32-bit operand instructions. Instructions that read 32-bit memory operands still take only one cycle to execute, even if their operand is in singleaccess memory. Single-access memory blocks are designed to allow a 32-bit read to occur in one cycle. Instructions that write 32-bit operands take two cycles to execute.
DLD *AR2, A ; This instruction only takes 1 cycle even ; if the operand is in singleaccess memory.
Pipeline
7-33

Single-Access Memory and the Pipeline

Read-write conflict. If an instruction that writes to a single-access memory block is followed by an instruction that reads from the same single-access memory block, a conflict occurs because both instructions try to access the same memory block simultaneously. In this case, the read access is delayed automatically by one cycle. For example:
STL A, *AR1+ LD *AR3, B ; ; ; ; AR1 and AR3 points at the same SARAM block. This instruction takes 1 additional cycle due to a memory access conflict.

On the other hand, a dual-operand instruction that has a read operand and a write operand does not cause this conflict because the two accesses are done in two different pipeline stages. For example:
ST A, *AR2+ ||ADD *AR3+, B ; ; ; ; This instruction does not take any extra cycles, even if AR2/AR3 point at the same single access memory block.

Code-data conflict. Another type of memory access conflict can occur when SARAM or ROM is mapped in both program and data spaces. In this case, if instructions are fetched from a memory block and data accesses (read or write) are also performed on the same memory block, the instruction fetch is delayed by one cycle. For example:
LD *AR1+, A ; ; ; ; This read data access delays a subsequent instruction fetch. This write data access delays a subsequent instruction fetch

STH A, *AR2

This situation causes significantly higher pipeline latency than the cases described previously. This is because each time there is a read or write access to the memory block, the pipeline is stalled for one cycle. It is generally recommended that each single-access memory block be reserved for either data or program storage to avoid hits each time a data access is made to that block.

7-34

Pipeline Latencies

7.5 Pipeline Latencies

The 54x pipeline allows multiple instructions to access CPU resources simultaneously. Because CPU resources are limited, conflicts can occur when one CPU resource is accessed by more than one pipeline stage. Some of these pipeline conflicts are resolved automatically by the CPU by delaying accesses. Other conflicts are unprotected and must be resolved by the programmer. In general, unprotected conflicts are resolved by rearranging instructions or by inserting NOP instruction (no operation performed). They can also be avoided by using only instructions that do not create any pipeline conflicts or by observing necessary delays before certain registers are accessed.

7.5.1

Recommended Instructions for Accessing Memory-Mapped Registers

Unprotected pipeline conflicts can occur when any one of the following memory-mapped registers is accessed:

Auxiliary registers (AR0 AR7) Block size register (BK) Stack pointer (SP) Temporary register (T) Processor mode status register (PMST) Status registers (ST0 and ST1) Block-repeat counter register (BRC) Memory-mapped accumulator registers (AG, AH, AL, BG, BH, BL)

However, certain instructions can access these registers without causing pipeline conflicts if you observe appropriate latency cycles. Table 73 lists these instructions. Table 73 is valid only if programmers limit themselves to those instructions that are listed in column 3 in order to perform functions listed in column 2. Otherwise, refer to the following sections to find the latency of each individual instruction. Furthermore, this table is provided as a quick reference for pipeline latencies. It does not describe all possible pipeline latencies, nor does it provide detailed information about latencies.

Pipeline

7-35

Pipeline Latencies

Table 73. Recommended Instructions for Accessing Memory-Mapped Registers

Cat 1 Function Writing to ARx/BK without using an accumulator Instruction(s) STM MVDK MVMM MVMD STLM STH STL Store type POPM Latency ARx update: None BK update: The next word must not use circular addressing The next 2 words (ARx) or 3 words (BK) must not use the same register. The next 1 word (ARx) or 2 words (BK) must not use the same register. Additional Restrictions None

Writing to ARx/BK using an accumulator

Popping ARx/BK from stack

Writing to SP without using an accumulator

STM MVDK MVMM MVMD STLM STH STL Store type STM MVDK LD Smem,T LD Smem,T || ST STLM STH STL STM MVDK STLM STH STL Store type

None if CPL = 0 The next 1 word must not use SP if CPL = 1#. The next 2 (if CPL = 0) or 3 (if CPL = 1) words must not use SP#. None

Writing to SP using an accumulator

Writing to T without using an accumulator

Writing to T using an accumulator

The next word must not use T.

8 9

Writing to BRC without using an accumulator Writing to BRC using an accumulator

None The next instruction must not be a RPTB[D].

Category Any other store-type instruction. See Table 75 on page 7-40 for a list of store-type instructions. # Interrupts cause an update of SP. This update of SP can interfere with a previous write to SP. Therefore, special considerations must be made when using interrupts while executing instructions that update SP.

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The next instruction must not write to any ARx, BK, or SP using STM, MVDK, or MVMD. Do not precede a category 3 instruction with any category 2 or 5 instruction that writes to any ARx, BK, or SP. None The next instruction must not write to ARx, BK, or SP using STM, MVDK, or MVMD. None None None None

Pipeline Latencies

Table 73. Recommended Instructions for Accessing Memory-Mapped Registers (Continued)

Cat 10 Function Writing to ARP Instruction(s) LD #k, ARP Latency None Additional Restrictions None

Category Any other store-type instruction. See Table 75 on page 7-40 for a list of store-type instructions. # Interrupts cause an update of SP. This update of SP can interfere with a previous write to SP. Therefore, special considerations must be made when using interrupts while executing instructions that update SP.

Pipeline

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Table 73. Recommended Instructions for Accessing Memory-Mapped Registers (Continued)

Cat 11 Function Writing to DP Instruction(s) LD #k, DP LD Smem, DP RSBX SSBX Latency None Additional Restrictions None

12

Writing to CPL

The next 3 words must not use direct addressing mode. The next word must not be affected by SXM status. None

None

13

Writing to SXM

RSBX SSBX

None

14

Writing to ASM

LD #k, ASM LD Smem, ASM RSBX SSBX

None

15

Writing to BRAF

The next 5 words must not contain the last instruction word in the RPTB loop. The next 2 words must not contain the last instruction word in the RPTB loop. The next 6 cycles must not include an instruction fetch from the on-chip memorys address range. The next 3 words must not access the DROMs address range. The next instruction must not use T. The next instruction must not use direct addressing mode (CPL = 1).

None

16

Writing BRC to memory

SRCCD

None

17

Writing to OVLY, MP/MC, or IPTR

ANDM ORM XORM

An external-bus cycle may cause additional latency.

18

Writing to DROM bit

ANDM ORM XORM EXP

An external-bus cycle may cause additional latency. None

19

Calculating an exponent Stack manipulation in compiler mode (CPL = 1)

20

FRAME POPM/POPD PSHM/PSHD

None

Category Any other store-type instruction. See Table 75 on page 7-40 for a list of store-type instructions. # Interrupts cause an update of SP. This update of SP can interfere with a previous write to SP. Therefore, special considerations must be made when using interrupts while executing instructions that update SP.

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Pipeline Latencies

Table 73. Recommended Instructions for Accessing Memory-Mapped Registers (Continued)

Cat 21 Function Reading AG, AH, AL, BG, BH, or BL as memory-mapped registers Instruction(s) Latency Additional Restrictions None

Any instruction that can The previous instrucread from memory tion must not modify accumulator A or accumulator B.

Category Any other store-type instruction. See Table 75 on page 7-40 for a list of store-type instructions. # Interrupts cause an update of SP. This update of SP can interfere with a previous write to SP. Therefore, special considerations must be made when using interrupts while executing instructions that update SP.

7.5.2

Updating ARx, BK, or SPA Resolved Conflict

Table 74 lists 54x instructions that update data-address generation logic (DAGEN) registers in the read stage of the pipeline. The DAGEN registers are the auxiliary registers (ARx), the block size register (BK), and the stack pointer (SP). All other instructions that write to these registers perform their writes in the execute stage and are store-type instructions. They are listed in Table 75.

Table 74. Instructions That Access DAGEN Registers in the Read Stage
Instruction Type Constant initialization Move type 1 Instructions STM ST MVDD POPM POPD DELAY MVDK MVMD #lk, MMR #lk, Smem, Xmem, Ymem MMR Smem, Smem, Smem, dmad MMR, dmad

Move type 2

This operand must be pointing to one of the DAGEN registers. DP must be 0 to access DAGEN registers.

Pipeline

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Pipeline Latencies

Table 75. Store-Type Instructions

Instruction MVKD MVDM MVPD STH STH STH STH STLM STL STL dmad, Smem dmad, MMR dmad, Smem src, Smem src, ASM, Smem src, SHFT, Xmem src, SHIFT, Smem src, MMR src, Smem src, ASM, Smem Instruction STL STL ST || ADD ST || LD ST || LT ST || MAC[R] ST || MAS[R] ST || MPY ST || SUB SACCD src, Xmem, cond src, SHFT, Xmem src, SHIFT, Smem Instruction SRCCD STRCD CMPS ST ST ADDM ANDM ORM XORM Xmem, cond Xmem, cond src, Smem T, Smem TRN, Smem Smem, #lk Smem, #lk #lk, Smem Smem, #lk

When a store-type instruction is immediately followed by an instruction that updates ARx, BK, or SP in the read stage, a conflict can occur, because both instructions try to access DAGEN registers. The DAGEN register set can be written to only once in a given cycle, so the CPU delays the read stage access by one cycle. This access is performed when the second instruction is in the execute stage of the pipeline. This generally does not affect the execution time of that instruction. Example 722, Example 723, and Example 724 show this conflict.

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Example 722. Resolving Conflict When Updating Multiple ARxs

(a) Updating AR1 in execute stage and AR2 in read stage

STLM STM

A, AR1 #1, AR2

; ; ; ;

This instruction updates AR1 in the Execute stage. This instruction tries to update AR2 in its read stage, creating a conflict with the previous instruction. The AR2 update is delayed by one cycle.
1
Prefetch

2
Fetch

3
Decode

4
Access

5
Read

6
Execute

STLM A, AR1
Prefetch Fetch Decode Access

Write to AR1
Read Execute

STM #1, AR2 (1st word) (write delayed by 1 cycle)

Prefetch Fetch Decode

STM #1, AR2 (2nd word)

Legend:

Where a write conflict occurs

Where the write actually occurs

Write to AR2
Access

Write to AR2
Read Execute

Pipeline

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Example 722. Resolving Conflict When Updating Multiple ARxs (Continued)

(b) Updating AR1 in execute stage, AR2 in read stage, and AR3 in read stage

STH ; STM ; STM

A, AR1 #1, AR2

; This instruction updates AR1 in the execute stage. ; This instruction tries to update AR2 in its read stage, ; causing a conflict. The update is delayed by one cycle. ; This instruction updates AR3 in its read stage. It : creates no conflict since the previous instruction was ; a two-word instruction. 2
Fetch

#2, AR3

1
Prefetch

3
Decode

4
Access

5
Read

6
Execute

10

STH A, AR1
Prefetch Fetch Decode Access

Write to AR1
Read Execute

STM #1, AR2 (1st word) (write delayed by 1 cycle)

Prefetch Fetch Decode

STM #1, AR2 (2nd word)

Prefetch Fetch

STM #2, AR3 (1st word)

Prefetch Fetch Decode

STM #2, AR3 (2nd word)

Legend:

Where a write conflict occurs

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Write to AR2
Access Decode

Write to AR2
Read Execute

Access

Read

Execute

Write to AR3
Access Read Execute

Where the write actually occurs

Pipeline Latencies

Example 723. Resolving Conflict When Updating ARx and BK

STLM MVDK B, BK ; This instruction updates BK in the execute stage. 200h, AR1 ; This instruction tries to update AR1 in it read ; stage. The CPU delays this update by one cycle to ; resolve the conflict.
1
Prefetch

2
Fetch

3
Decode

4
Access

5
Read

6
Execute

STLM B, BK
Prefetch Fetch Decode Access

Write to BK

MVDK 200h, AR1 (1st word) (write delayed by 1 cycle)

Prefetch Fetch Decode

MVDK 200h, AR1 (2nd word)

Legend:

Where a write conflict occurs

Where the write actually occurs

Write to AR1
Access

Read

Execute

Write to AR1
Read Execute

Pipeline

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Example 724. Resolving Conflict When Updating SP, BK, and ARx
STLM ; POPM ; STM A, SP BK ; This instruction updates SP in the execute stage. ; This instruction tries to update BK in its read stage. ; The CPU delays this update by one cycle. ; This instruction tries to update AR1 in its read stage, ; conflicting with the previous instruction. ; The update is delayed by one cycle. 2
Fetch

#1, AR1

1
Prefetch

3
Decode

4
Access

5
Read

6
Execute

10

STLM A, SP
Prefetch Fetch Decode Access

Write to SP
Read Execute

POPM BK (write delayed by 1 cycle)

Prefetch Fetch

Decode

STM #1, AR1 (1st word) (write delayed by 1 cycle)

Prefetch Fetch

STM #1, AR1 (2nd word)

Legend:

Where a write conflict occurs

These conflicts are automatically resolved by the 54x CPU. This generally does not affect instruction-execution behavior. However, there is one case in which resolution by the CPU can cause an unprotected pipeline conflict. This is explained in section 7.5.3, Rules to Determine DAGEN Register Access Conflicts.

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Write to BK
Access

Write to BK
Read

Execute

Write to AR1
Access

Write to AR1
Read Execute

Decode

Where the write actually occurs

Pipeline Latencies

7.5.3

Rules to Determine DAGEN Register Access Conflicts

Some instructions update DAGEN registers in the read stage. This can result in conflict if the previous instruction tries to update a DAGEN register in its execute stage. This conflict is resolved automatically by the CPUs delaying the read stage update by one cycle. This delay can cause an additional cycle of latency between the instruction that writes to the DAGEN register in its read stage and the instruction that follows it. The following set of conditions determines when such a conflict can occur:

The first instruction is one of two types:

J J

Store-type instruction that accesses any DAGEN register to load a new value (see Table 75 on page 7-40) Move type 1 instruction (see Table 74) that has a DAGEN register conflict with the previous instruction.

7.5.4

The second instruction is a constant-initialization-type instruction, a move type 1 instruction, or a move type 2 instruction (see Table 74) that writes to BK, SP, or any ARx. The instruction must not use a long offset modifier (see Example 727). The third instruction uses the same register as the second instruction in indirect addressing mode.

Latencies for ARx and BK

An unprotected pipeline conflict can occur when accessing an auxiliary register or BK when both of the following two conditions are met:

An instruction writes to an auxiliary register or BK. The next instruction uses the same auxiliary register as an address pointer or index in indirect addressing mode, or uses BK in circular addressing mode. This instruction could also be an MVMM or a CMPR that reads BK or the same ARx.

This conflict occurs because the first instruction updates ARx or BK in either the read or execute stage of the pipeline and the following instruction uses BK or the same ARx when it is in the access stage of the pipeline. This results in an incorrect ARx or BK read by the second instruction, because the previous instruction has not yet updated the registers contents. Certain instructions (see Table 76) do not have any latency in updating ARx. Use these instructions wherever possible to avoid pipeline conflicts.
Pipeline
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Pipeline Latencies

Table 76. Pipeline-Protected Instructions for Updating ARx

To do this: Write an immediate value to ARx Copy a memory location to ARx Copy the contents of an ARx to another ARx Use this instruction: STM MVDK #lk, MMR Smem, MMR

MVMM MMR, MMR

See Table 77 for one possible conflict with these instructions.

STM and MVDK do not conflict with the next instruction for two reasons:

They are two-word instructions. They update ARx when the first instruction word is in the read stage of the pipeline.

Table 77 shows the latencies between instructions that update and subsequently use ARx. The second and third instructions must access the same auxiliary register or BK to cause a latency. Any instruction not mentioned in the table has no latency. Table 78 shows the latencies between instructions that update and subsequently use BK. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

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Pipeline Latencies

Table 77. Latencies for Accessing ARx

(a) Latencies based on third-instruction category
Third Instruction Second Instruction STM ST #lk, auxreg #lk, auxreg Category I 0 0 1 Category II 0 0 0

MVDK Smem, auxreg MVMD MMR, auxreg MVKD dmad, auxreg MVDM dmad, auxreg MVPD pmad, auxreg POPM POPD DELAY LTD MVDD auxreg auxreg auxreg auxreg Xmem, auxreg

Store-type instructions (see Table 75)

(b) Categories for the third instruction

Category I MVMM auxreg, MMR CMPR CC, auxreg MVKD dmad, auxind MVDM dmad, auxind MVPD pmad, auxind MACP auxind, pmad, src MACD auxind, pmad, src ADD LD STH STL SUB auxind, shift, src, dst auxind, shift, dst src, shift, auxind src, shift, auxind auxind, shift, src, dst With a long-offset modifier MVKD dmad, auxind MVDM dmad, auxind MVPD pmad, auxind MACP auxind, pmad, src MACD auxind, pmad, src ADD LD STH STL SUB auxind, shift, src, dst auxind, shift, dst src, shift, auxind src, shift, auxind auxind, shift, src, dst Category II

Without a longoffset modifier

With an extended shift and a longoffset modifier

With an extended shift and without a long-offset modifier With one operand using indirect addressing mode with or without a longoffset modifier

BANZ[D] auxind Instructions not listed here that use ARx in indirect addressing mode.

With or without a long- FIRS offset modifier

Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria. See section 7.5.3, Rules to Determine DAGEN Register Access Conflicts, for more information. The destination operand auxreg must point at AR0-AR7 in either direct or indirect addressing mode. The operand auxind must use indirect addressing mode. Shift value between 16 and 15 Notes: 1) Any instruction that does not fit in either of the two categories has zero latency. 2) The first instruction can be any 54x instruction.

Pipeline

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Pipeline Latencies

Table 78. Latencies for Accessing BK

(a) Latencies based on third-instruction category
Third Instruction Second Instruction STM ST #lk, bkreg #lk, bkreg Category I 1 1 2 Category II 0 0 1

MVDK Smem, bkreg MVMD MMR, bkreg MVKD dmad, bkreg MVDM dmad, bkreg MVPD pmad, bkreg POPM POPD DELAY LTD MVDD bkreg bkreg bkreg bkreg Xmem, bkreg

Store-type instructions (see Table 75)

(b) Categories for the third instruction

Category I MVKD dmad, circind MVDM dmad, circind MVPD pmad, circind MACP circind, pmad, src MACD circind, pmad, src ADD LD STH STL SUB circind, shift, src, dst circind, shift, dst src, shift, circind src, shift, circind circind, shift, src, dst With a long-offset modifier Category II MVKD dmad, circind MVDM dmad, circind MVPD pmad, circind MACP circind, pmad, src MACD circind, pmad, src ADD LD STH STL SUB circind, shift, src, dst circind, shift, dst src, shift, circind src, shift, circind circind, shift, src, dst

Without a longoffset modifier

With an extended shift and a longoffset modifier

With an extended shift and without a long-offset modifier With one operand using indirect addressing mode with or without a longoffset modifier

BANZ[D] circind Instructions not listed here that use BK in circular addressing mode.

With or without a long- FIRS offset modifier

Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria. See section 7.5.3, Rules to Determine DAGEN Register Access Conflicts, for more information. The destination operand bkreg must point at BK in either direct or indirect addressing mode. The operand circind must use circular addressing mode. Shift value between 16 and 15 Notes: 1) Any instruction that does not fit in either of the two categories has zero latency. 2) The first instruction can be any 54x instruction.

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Pipeline Latencies

Example 725. ARx Updated With No Latency

(a)
ADD STM LD A, B #100h, AR3 *AR3+, A ; This instruction does not conflict ; with the previous instruction. ; No latency is required to use AR3.

(b)
ADD MVDK STH A, B 200h, AR7 B, *AR7+ ; This instruction does not create ; a DAGEN conflict. ; This instruction has zero latency.

(c)
STLM A, AR1 ; ; ; ; ; ; ; This instruction updates AR1 in the execute stage, possibly creating a DAGEN conflict. However, this instruction uses a long offset modifier. Therefore, it creates no DAGEN conflict. No latency is required to use AR2.

MVDK

*(200h),AR2

MAR

*AR2+

Example 726. ARx Updated With a 1-Cycle Latency

(a)
ADD POPM NOP LD A, B AR3 ; ; ; ; ; ; This instruction does not create a DAGEN conflict. This instruction has a 1-cycle latency if AR3 is used in the next instruction. The NOP is inserted to avoid the conflict.

*AR3+, A

(b)
STLM POPM A, AR1 BK ; ; ; ; ; ; ; ; ; This instruction updates AR1 in the execute stage. This instruction tries to update BK in the read stage. The CPU delays the update by one cycle. This instruction tries to update AR2 in the read stage. The CPU delays this update by one cycle. This is why one NOP is required.

STM NOP LD

#1, AR2

*AR2+, B

Pipeline

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Pipeline Latencies

Example 727. ARx Updated With and Without a 1-Cycle Latency

(a) ARx updated with a one-cycle latency
STLM MVDK NOP MAR A, AR1 100h, AR2 *AR2+ ; ; ; ; This instruction creates DAGEN conflict. The AR2 update is delayed by one cycle.

(b) ARx updated with no latency after reordering instructions

MVDK STLM MAR 100h, AR2 A, AR1 *AR2+ ; ; ; ; ; This instruction does not require any latency. This instruction is placed after MVDK to avoid a DAGEN conflict. No latency is required now.

Example 728. ARx Updated With and Without a 2-Cycle Latency

(a) ARx updated with a two-cycle latency
STLM POPM NOP NOP LD A, SP AR1 ; ; ; ; This instruction creates a DAGEN conflict. This instruction has a 2-cycle latency due to the DAGEN conflict.

*AR1+, A

; Two NOPs avoid this conflict.

(b) ARx updated with no latency after reordering instructions

POPM STLM AR1 A, SP ; ; ; ; ; ; This instruction has a 1-cycle latency. This instruction is placed after the POPM to avoid DAGEN conflicts and to eliminate the need for NOPs.

LD

*AR1+, A

Example 729. ARx Updated With a 2-Cycle Latency

ADD A, B STLM NOP NOP MVMM A, AR1 ; ; ; ; This instruction does not create a DAGEN conflict. This instruction has a 2-cycle latency.

AR1, AR2

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Pipeline Latencies

Example 730. BK Updated With a 1-Cycle Latency

ADD STM NOP ADD A, B #100h, BK ; ; ; ; ; ; This instruction does not create a DAGEN conflict. This instruction needs a 1-cycle latency. This instruction uses BK for circular addressing

*AR1+%, B

7.5.5

Latencies for the Stack Pointer

Stack pointer (SP) latencies discussed in this section occur when SP is used in one of two ways:

7.5.5.1

As an offset in direct addressing (when CPL = 1) In a push, pop, call, return, FRAME, or MVMM operation

SP Used in Compiler Mode (CPL = 1)

A pipeline conflict occurs if two conditions are simultaneously met:

One instruction writes to SP. The next instruction uses SP as the base address for direct addressing in compiler mode (CPL = 1), or an interrupt occurs#.

The conflict occurs because the second instruction tries to use SP in a pipeline stage that occurs before the previous instruction updates it. Table 79 lists the latencies between instructions that update and subsequently use SP in compiler mode. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate for SP latencies.
# Interrupts cause an update of SP. This update of SP can interfere with a previous write to SP. Therefore, special considerations must be made when using interrupts while executing instructions that update SP.

Pipeline

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Pipeline Latencies

Table 79. Latencies for SP in Compiler Mode (CPL = 1)

(a) Latencies based on third-instruction category
Third Instruction Second Instruction STM ST #lk, SP #lk, SP Category I 1 1 2 Category II 0 0 1

MVDK Smem, SP MVMD MMR, SP MVKD dmad, SP MVDM dmad, SP MVPD pmad, SP MVDD POPM POPD FRAME MVMM POPM POPD PSHM PSHD RETFD Xmem, spind SP SP k MMR, SP MMR Smem MMR Smem

Store-type instructions (see Table 75)

(b) Categories for the third instruction

Category I All instructions using SP in direct addressing mode, except those listed in Category II. Category II MVKD dmad, dirmem MVDM dirmem, MMR MVPD pmad, dirmem MACP dirmem, pmad, src MACD dirmem, pmad, src ADD dirmem, shift, src, dst LD dirmem, shift, dst STH src, shift, dirmem STL src, shift, dirmem SUB dirmem, shift, src, dst
Legend:

With an extended shift

SP Destination operand pointing to the stack pointer in either direct or indirect addressing modes MMR Any memory-mapped register except SP spind Destination operand pointing to the stack pointer using indirect addressing mode dirmem Operand using direct addressing mode in compiler mode (CPL = 1) Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria. See section 7.5.3, Rules to Determine DAGEN Register Access Conflicts, for more information. Shift value between 16 and 15. 1) Any instruction that does not fit in either of the two categories has zero latency. 2) The first instruction can be any 54x instruction.

Notes:

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Example 731. SP Load With No Latency in Compiler Mode (CPL =1)

(a)
ADD MVDK ADD A, B ; ; 100h, SP ; ; 50h,-3,A,B This instruction does not create a DAGEN conflict. This SP update requires a zero latency according to the above table.

(b)
STLM POPM MVKD A, AR2 AR1 100h,1h ; ; ; ; This instruction does not affect pipeline latency. This SP update requires a zero latency according to the table.

Example 732. SP Load With a 1-Cycle Latency in Compiler Mode (CPL = 1)

(a)
STLM MVMM NOP LD A, AR2 AR1, SP ; ; ; ; ; This instruction does not affect pipeline latency. This SP update requires a one-cycle latency since the next instruction uses SP when CPL = 1.

50h,A

(b)
ADD STM NOP LD A, B ; ; #100h, SP ; ; ; 50h,A This instruction does not create a DAGEN conflict This SP update requires a one-cycle latency since the next instruction uses SP when CPL = 1.

(c)
ADD RETFD NOP LD A,B ; ; ; ; ; ; ; ; This instruction does not affect pipeline latency. SP is incremented after popping the return address. This instruction cannot be placed in the first delay slot since it uses direct addressing mode with the new SP value.

50h, A

Pipeline

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Pipeline Latencies

Example 733. SP Load With and Without a 2-Cycle Latency

(a) SP Load With a Two-Cycle Latency
STLM MVDK NOP NOP LD A, BK 100h, SP ; ; ; ; ; This instruction creates a DAGEN conflict. This SP update requires 2 cycles of latency according to the above table.

50h, A

(b) SP Load With No Latency

MVDK STLM 100h, SP A, BK ; ; ; ; ; ; This SP update requires 1 cycle of latency. This instruction is placed after the MVDK instruction to prevent a DAGEN conflict. No NOPs are required in this case.

LD

50h, A

Example 734. SP Load With a 2-Cycle Latency in Compiler Mode (CPL = 1)

ADD POPM NOP NOP LD A, B SP ; ; ; ; ; This instruction does not affect pipeline latency. The new value of SP is popped from the stack. Two NOPs are required to use the new value of SP.

50h, A

Example 735. SP Load With a 3-Cycle Latency in Compiler Mode (CPL = 1, DP = 0)

STLM STH NOP NOP NOP LD A, AR1 A, SP ; ; ; ; ; This instruction does not affect pipeline latency. This SP update requires a three-cycle latency since the next instruction uses SP when CPL is 1.

50h,A

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Pipeline Latencies

7.5.5.2

SP Used in Push, Pop, Call, Return, FRAME, and MVMM Operations

A pipeline conflict occurs if two conditions are simultaneously met:

An instruction updates SP. The next instruction uses the stack for a push, pop, call, return, FRAME, or MVMM operation.

The conflict occurs because the second instruction tries to use SP in a pipeline stage that occurs before the stage in which the previous instruction updates SP. Table 710 lists instructions that do not have any latency in updating SP when the CPU is not in compiler mode (CPL = 0). These instructions should be used wherever possible to avoid conflicts.

Table 710. Pipeline-Protected Instructions to Update SP in Noncompiler Mode (CPL = 0)

To do this: Write an immediate value to SP Copy a memory location to SP Copy the contents of an ARx or BK to SP Move SP by a frame Use this instruction: STM MVDK #lk, SP Smem, SP

MVMM MMR, SP FRAME k

See Table 711 for one possible conflict with these instructions.

Table 711 lists the latencies between instructions that update and use SP in noncompiler mode (CPL = 0). Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate SP latencies.

Pipeline

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Pipeline Latencies

Table 711. Latencies for SP in Noncompiler Mode (CPL = 0)

(a) Latencies based on third-instruction category
Third Instruction Second Instruction STM ST #lk, SP #lk, SP Category I 0 0 1 Category II 0 0 0

MVDK Smem, SP MVMD MMR, SP MVKD dmad, SP MVDM dmad, SP MVPD pmad, SP MVDD POPM POPD Xmem, spind SP SP

Store-type instructions (see Table 75)

(b) Categories for the third instruction

Category I PSHM PSHD POPM PSHM MMR Smem MMR Smem Without a long-offset modifier Category II PSHM MMR PSHD Smem POPM MMR PSHM Smem CALA[D] address FCALA[D] With a long-offset modifier

CALL[D] address CC[D] address FCALL[D] FRET[D] FRETE[D] INTR k RC[D] RET[D] RETE[D] RETF[D] MVMM FRAME TRAP
Legend:

SP, MMR k n
SP Destination operand pointing to the stack pointer in either direct or indirect addressing modes MMR Any memory-mapped register except SP spind Destination operand pointing to the stack pointer using indirect addressing mode Add one more cycle of latency if the first instruction meets the DAGEN register conflict criteria. See section 7.5.3, Rules to Determine DAGEN Register Access Conflicts, for more information. 1) Any instruction that does not fit in either of the two categories has zero latency. 2) The first instruction can be any 54x instruction.

Notes:

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Example 736. SP Load With No Latency in Noncompiler Mode (CPL = 0)

(a)
ADD STM PSHM A, B ; ; #100h, SP ; ; AR1 This instruction does not create a DAGEN conflict This SP update does not require any latency according to the above table.

(b)
STH MVDK A, 100h 200h, SP ; ; ; ; This instruction does not create a DAGEN conflict. This SP update does not require any latency according to the above table.

FRAME 10

Example 737. SP Load With and Without a 1-Cycle Latency in Noncompiler Mode (CPL = 0)
(a) SP Load With a One-Cycle Latency
STLM MVDK NOP PSHM A, AR1 200h, SP AR2 ; ; ; ; This instruction causes a DAGEN conflict with the next instruction. This SP update requires a one-cycle latency.

(b) SP Load With No Latency

MVDK STLM PSHM 200h, SP A, AR1 AR2 ; This instruction requires no latency. ; This instruction was placed after ; MVDK to avoid a DAGEN conflict.

Example 738. SP Load With a 1-Cycle Latency in Noncompiler Mode (CPL = 0)

STLM A, AR1 ; ; ; ; ; This instruction does not affect the pipeline latency for the next instruction. This SP update requires a one-cycle latency.

STLM NOP CALA

B, SP A

Pipeline

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Pipeline Latencies

7.5.6

Latencies for Temporary Register (T)

A pipeline conflict can occur when accessing T if two conditions are simultaneously met:

An instruction writes to T The next instruction uses T for a shift or bit-test operation.

The conflict occurs because the second instruction tries to use T in a pipeline stage that occurs before the previous instruction updates it. Table 712 lists instructions that do not have any latency in updating T. Use these instructions wherever possible to avoid any conflicts.

Table 712. Pipeline-Protected Instructions for Updating T

To do this: Write an immediate value to T Copy a memory location to T Copy a memory location to T Copy a memory location to T Use this instruction: STM #lk, T

MVDK Smem, T LD ST || LD Smem, T src, Ymem Xmem, T

Table 713 lists the latencies between instructions that update and use T.

Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate T latencies.

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Table 713. Latencies for the T Register Based on Second-Instruction Category

(a) Latencies Based on Second-Instruction Category
Second Instruction Category I
1

First Instruction MVKD dmad, T MVDM dmad, T POPM POPD DELAY MVDD T T T Xmem, Tind

Store-type instructions (see Table 75) EXP src

1
1

(b) Categories for the Second Instruction

Category I LD ADD SUB NORM BITT DADST DSADT DSUBT
Legend:

Smem, TS, dst Smem, TS, src Smem, TS, src src, dst Xmem Lmem, dst Lmem, dst Lmem, dst
T Tind

Without a long-offset modifier

Destination operand pointing at T in either direct or indirect addressing modes. Destination operand pointing at T using indirect addressing mode.

Note:

Any instruction that does not fit in Category I has zero latency.

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Example 739. T Load With No Latency

(a)
LD LD *AR3+, T *AR5+,TS,A ; This T update does not require ; any latency.

(b)
STM LD #100h, T *AR5+,TS,A ; This T update does not require ; any latency.

Example 740. T Load With a 1-Cycle Latency

(a)
POPM NOP BITT T *AR5+ ; This instruction requires a one; cycle latency.

(b)
EXP NOP NORM A A ; This instruction requires a one; cycle latency.

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7.5.7

Latencies for Accessing Status Registers

The following status register fields and bits are affected by latency:

7.5.7.1

ARP (auxiliary register pointer) CMPT (compatibility mode bit) CPL (compiler mode bit) DP (data page pointer) SXM (sign-extension mode bit) ASM (accumulator shift mode field) BRAF (block-repeat activity flag)

ST1 and a Repeat Block Loop

Some instructions write to ST1 in the execute stage of the pipeline. If any of these instructions is immediately followed by a RPTB[D] instruction that sets the BRAF flag in ST1 an incomplete repeat-block loop results. This occurs because RPTB[D] sets BRAF in the access stage of the pipeline and the previous instruction overwrites ST1 one cycle later. To avoid this conflict, it is recommended that only instructions listed in Table 714 be used to write to ST1 immediately prior to a RPTB[D] instruction. Any other instruction that writes to ST1 must not be immediately followed by a RPTB[D] instruction.

Table 714. Recommended Instructions for Writing to ST1

To do this Store a value to ST1 Copy a value from data memory to ST1 Clear a bit in ST1 Set a bit in ST1 Load ASM with a value Use this instruction STM ST #k, ST1 #k, ST1

MVDK #k, ST1 MVMD #k, ST1 RSBX SSBX LD LD #k, ASM Smem, ASM

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7.5.7.2

Updating ARP in Compatibility Mode (CMPT = 1) and CMPT bit

A pipeline conflict can occur if two conditions are simultaneously met:

An instruction updates ARP or CMPT. The next instruction uses ARP or CMPT to update the address pointer in indirect addressing mode.

The conflict occurs because the second instruction uses ARP or CMPT in a pipeline stage that occurs before the previous instruction updates ARP or CMPT. Table 715 lists one instruction that does not have any latency in updating ARP when the CPU is in compatibility mode. Use this instruction wherever possible to avoid any conflicts.

Table 715. Pipeline-Protected Instruction to Update ARP in Compatibility Mode (CMPT = 1)

To do this: Load ARP field of ST0 register Use this instruction: LD #k, ARP

Table 716 lists the latencies between instructions that update and use ARP or CMPT.

Notes: 1) You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies. 2) In compatibility mode (CMPT = 1), ARP is automatically updated by instructions that use indirect addressing mode. There is no pipeline conflict associated with such an ARP update. 3) ARP must always be set to 0 when the DSP is in standard mode (CMPT = 0). At reset, both ARP and CMPT are set to 0 automatically.

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Table 716. Latencies for ARP in Compatibility Mode (CMPT = 1) and CMPT bit
(a) Latencies based on second-instruction category
Second Instruction First Instruction STM ST #lk, status #lk, status Category I 2 2 3 Category II 2 2 2

MVDK Smem, status MVMD MMR, status MVKD dmad, status MVDM dmad, status MVPD pmad, status MVPD POPM POPD DELAY LTD MVDD pmad, status status status status status status

3 3

3 2

Store-type instruction (see Table 75) SSBX RSBX statbit statbit

3 3

2 2

(b) Categories for the second instruction

Category I MVKD MVDM MVPD MACP MACD ADD LD STH STL SUB dmad, auxind dmad, auxind dmad, auxind dmad, auxind, pmad, src auxind, pmad, src auxind, shift, src, dst auxind, shift, dst src, shift, auxind arc, shift, auxind auxind, shift, src, dst Category II MVKD dmad, auxind With a long-offset MVDM dmad, auxind MVPD pmad, auxind modifier MACP auxind, pmad, src MACD auxind, pmad, src With an extended shift and a long offset modifier ADD LD STH STL SUB auxind, shift, src, dst auxind, shift, dst src, shift, auxind src, shift, auxind auxind, shift, src, dst

Without a longoffset modifier

With an extended shift and without a long-offset modifier

All other instructions that use ARP or CMPT in indirect addressing mode with or without a long offset modifier.
Legend: Destination operand pointing to ST0 or ST1 to update ARP or CMPT respectively in either direct or indirect addressing modes MMR Any memory-mapped register auxind A read or write operand using indirect addressing mode statbit Destination operand writing to a bit in ARP or CMPT Shift value between 16 and 15. Any instruction that does not fit in either of the two categories has zero latency. status

Note:

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Example 741. ARP Load With No Latency in Compatibility Mode (CMPT = 1)

LD LD #1h, ARP *AR0, A ; This ARP load does not require any ; latency.

Example 742. ARP Load With a 2-Cycle Latency in Compatibility Mode (CMPT = 1)
STLM NOP NOP ADD A, ST0 ; The ARP field of ST0 is updated here.

*AR0+,3,B ; The new ARP value is used here

Example 743. ARP Load With a 3-Cycle Latency in Compatibility Mode (CMPT = 1)
POPM NOP NOP NOP LD ST0 ; The ARP field of ST0 is updated here.

*AR0+, A

; The new ARP value is used here.

7.5.7.3

Updating DP in Direct Addressing Mode (CPL = 0)

A pipeline conflict can occur if two conditions are simultaneously met:

An instruction updates DP. The next instruction uses DP as the base address for direct addressing in noncompiler mode (CPL = 0).

The conflict occurs because the second instruction uses DP in a pipeline stage that occurs before the previous instruction updates it. Table 717 lists instructions that do not have any latency in writing to DP. It is recommended that these instructions be used wherever possible to avoid conflicts.

Table 717. Recommended Instructions to Update DP in Noncompiler Mode (CPL = 0)

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To do this: Use this instruction: LD LD #k, DP Load an immediate number to DP Copy contents of a memory location to DP Smem, DP

Table 718 lists the latencies between instructions that update DP and subsequently use it. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

Pipeline Latencies

Table 718. Latencies for DP in Noncompiler Mode (CPL = 0)

(a) Latencies based on second-instruction category
Second Instruction First Instruction STM ST #lk, status #lk, status Category I 2 2 3 3 3 Category II 2 2 2 3 2

MVDK Smem, status MVMD MMR, status MVKD dmad, status MVDM dmad, status MVPD POPM POPD MVDD pmad, status status status status

Store-type instruction (see Table 75) SSBX RSBX ST0, statbit ST0, statbit

3 3

2 2

(b) Categories for the second instruction

Category I All instructions that use DP for direct addressing mode except those listed in Category II. Category II MVKD MVPD MACP MACD ADD LD STH STL SUB
Legend:

dmad, dirmem pmad, dirmem dirmem, pmad, src dirmem, pmad, src dirmem, shift, src, dst dirmem, shift, dst src, shift, dirmem src, shift, dirmem dirmem, shift, src, dst With an extended shift

Note:

status Destination operand pointing to ST0 to update DP in either direct or indirect addressing modes MMR Any memory-mapped register statbit Destination operand writing to a bit in DP field of ST0 dirmem A read or write operand using direct addressing mode when CPL = 0 Shift value between 16 and 15. Any instruction that does not fit in either of the two categories has zero latency.

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Example 744. DP Load With No Latency in Noncompiler Mode (CPL = 0)

(a)
LD LD #2h, DP 27h, A ; This DP load does not require any ; latency.

(b)
LD LD 100h, DP 27h, A ; This DP load does not require any ; latency.

Example 745. DP Load With a 2-Cycle Latency in Noncompiler Mode (CPL = 0)

STLM NOP NOP STH A, ST0 ; The DP field of ST0 is updated here.

B,-3,27h

; The new DP value is used here.

Example 746. DP Load With a 3-Cycle Latency in Noncompiler Mode (CPL = 0)

POPM NOP NOP NOP LD ST0 ; The DP field of ST0 is updated here.

27h, A

; The new DP value is used here

7.5.7.4

Updating CPL
A pipeline conflict can occur if two conditions are simultaneously met:

An instruction modifies CPL. The next instruction uses direct addressing mode.

The conflict occurs because the second instruction reads CPL in a pipeline stage that occurs before the previous instruction updates it. Table 719 lists the latencies between instructions that update CPL and subsequently use it. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

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Table 719. Latencies for the CPL Bit

(a) Latencies based on second-instruction category
Second Instruction First Instruction STM ST #lk, status #lk, status Category I 2 2 3 3 3 Category II 1 1 2 3 2

MVDK Smem, status MVMD MMR, status MVKD dmad, status MVDM dmad, status MVPD POPM POPD MVDD pmad, status status status status

Store-type instruction (see Table 75) SSBX RSBX CPL CPL

3 3

2 2

(b) Categories for the second instruction

Category I All instructions that use direct addressing mode except those listed in Category II. Category II MVKD MVPD MACP MACD ADD LD STH STL SUB
Legend: MMR dirmem status

dmad, dirmem pmad, dirmem dirmem, pmad, src dirmem, pmad, src dirmem, shift, src, dst dirmem, shift, dst src, shift, dirmem arc, shift, dirmem dirmem, shift, src, dst

With an extended shift

Note:

Any memory-mapped register A read or write operand using direct addressing mode when CPL = 0 Destination operand pointing to ST1 to modify CPL in either direct, indirect, or memory-mapped addressing mode Shift value between 16 and 15. Any instruction that does not fit in either of the two categories has zero latency.

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Example 747. CPL Update With a 1-Cycle Latency

STM NOP MVKD #k, ST1 ; This instruction modifies the CPL ; bit of ST1. ; Data read from 1000h is written to ; (SP + 30h)

1000h, 30h

Example 748. CPL Update With a 2-Cycle Latency

RSBX NOP NOP LD CPL ; ; ; ; ; ; CPL is changed from 1 to 0. Two NOPs are required, since a LD with an extended shift is being used to access an operand. The operand is read from the current data page.

27h, 1, A

Example 749. CPL Update With a 3-Cycle Latency

SSBX NOP NOP NOP LD CPL ; ; ; ; ; ; ; CPL is changed from 0 to 1. These NOPs can be replaced by other instructions that do not use direct addressing mode to access operands. The operand is read at an offset of 27h from SP.

27h, A

7.5.7.5

Updating SXM
A pipeline conflict can occur if two conditions are simultaneously met:

An instruction modifies SXM. The next instruction uses SXM to control sign extension.

The conflict occurs because the second instruction uses SXM in a pipeline stage that occurs before the previous instruction updates it. Table 720 lists the latencies between instructions that update SXM and subsequently use it. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

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Table 720. Latencies for the SXM Bit

(a) Latencies based on second-instruction category
First Instruction MVKD MVDM POPM POPD MVDD dmad, status dmad, status status status Xmem, status Second Instruction Category I 1

Store-type instruction (see Table 75) SSBX RSBX SXM SXM

1 1

(b) Category for the second instruction

Category I All instructions affected by the sign-extension mode bit, except those that require an Smem operand with a long offset modifier (for example, LD *+AR1 (100h), A)
Legend: Note: status Destination operand pointing at ST1 to update SXM in either direct, indirect, or memory-mapped addressing mode

Any instruction that does not fit in Category I has zero latency.

Example 750. SXM Update With No Latency

RSBX ADD SXM ; This instruction modifies the SXM bit of ; ST1. *+AR1(100h),A

Example 751. SXM Update With a 1-Cycle Latency

(a)
RSBX NOP LD SXM ; This SXM load requires one cycle of ; latency.

*AR5+, A

(b)
POPM NOP ADD ST1 ; This instruction modifies the SXM bit of ; ST1. *AR2+,A

(c)
STLM NOP SUB A, ST1 ; This instruction modifies the SXM bit of ; ST1. *AR2-,A

Pipeline

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7.5.7.6

ASM Field Used for Shift Operations

A pipeline conflict can occur if two conditions are simultaneously met:

An instruction modifies ASM. The next instruction uses ASM as the shift-count value.

The conflict occurs because the second instruction reads ASM in a pipeline stage that occurs before the previous instruction updates it. Table 721 lists instructions that do not have any latency for writing to the ASM bit field. Use these instructions wherever possible to avoid any conflicts.

Table 721. Pipeline-Protected Instructions for Writing to ASM

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To do this: Use this instruction: LD LD #k, ASM Load an immediate number to ASM Copy contents of a memory location to ASM Smem, ASM

Table 722 lists the latencies between instructions that write to ASM and those that subsequently use it. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

Pipeline Latencies

Table 722. Latencies for ASM Bit Field

(a) Latencies based on second-instruction category
First Instruction MVKD MVDM POPM POPD MVDD dmad, status dmad, status status status Xmem, status Second Instruction Category I 1

Store-type instruction (see Table 75) SSBX RSBX STI, asmbit STI, asmbit

1 1

(b) Category for the second instruction

Category I STH STL src, ASM, Smem src, ASM, Smem Without a long-offset modifier

ST src, Ymem || LD/ADD/SUB/MAC/MAS/MPY SACCD src, Smem, cond LD ADD SUB src, ASM, dst src, ASM, dst src, ASM, dst
Destination operand writing to a bit in ASM field of ST1 Destination operand pointing at ST1 to update ASM in direct, indirect,or memory-mapped addressing mode

Legend: asmbit status Note:

Any instruction that does not fit in either of the two categories has zero latency.

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Example 752. ASM Update With No Latency

(a)
LD STH #6, ASM ; This instruction loads ASM with no ; latency. A,ASM,*AR1+

(b)
LD ADD 100h, ASM ; This instruction loads ASM with no ; latency A,ASM,B

(c)
STLM A, ST1 ; This instruction modifies the ASM ; field of ST1. No latency is needed ; since STL uses a long offset ; modifier. A,ASM,*+AR5(100h)

STL

Example 753. ASM Update With a 1-Cycle Latency

POPM NOP SUB ST1 A,ASM,B ; This instruction modifies the ASM ; field of ST1

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7.5.8

Latencies in Repeat-Block Loops

The following status register fields and bits are affected by latency:

7.5.8.1

BRC (block-repeat counter register) BRAF (block-repeat active flag)

Updating Block-Repeat Counter (BRC) Register

A pipeline conflict can occur if two conditions are simultaneously met:

An instruction writes to the BRC register The next instruction is an RPTB[D]

The conflict occurs because the second instruction reads BRC in a pipeline stage that occurs before the previous instruction updates it. There are certain instructions which do not cause any pipeline conflicts when updating BRC. Use these instructions wherever possible to avoid conflicts.

Table 724. Latencies for Updating BRC Before an RPTB Loop

First Instruction MVDK Smem, BRC MVMD MMR, BRC STM ST #k, BRC #k, BRC Latency if Second Instruction Is RPTB[D] 0 0 1

To do this Use this instruction STM #lk, BRC Write an immediate value to BRC Copy a memory location to BRC MVDK Smem, BRC

Table 723. Recommended Instructions for Writing to BRC Before an RPTB Loop

Table 724 lists latencies between instructions that update BRC and an RPTB[D] instruction. Notes: 1) Do not place instructions that modify BRC in the delay slots of a RPTBD instruction. 2) You are responsible for rearranging instructions or inserting NOPS, if necessary, to accommodate latencies.

All other instructions that modify BRC

Pipeline

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Example 754. Loading BRC Before Executing a New Repeat-Block Loop

(a)
STM RPTB ... endloop: #lk,BRC endloop1 ; There is no latency when BRC is ; loaded via STM before a new RPTB ; loop.

(b)
MVDK RPTBD ... endloop: count,BRC ; There is no latency when BRC is endloop1 ; loaded using MVDK before a new ; RPTB loop

(c)
STLM NOP RPTB ... endloop: A,BRC endloop1 ; There is a 1 cycle latency when ; BRC is loaded using an STLM ; instruction.

(d)
POPM BRC NOP RPTBD endloop1 ... endloop: ; There is a 1 cycle latency when ; BRC is loaded using a POPM ; instruction.

In a repeat-block loop, BRC is decremented when the last instruction in the loop is in the decode stage of the pipeline. However, the SRCCD instruction writes the BRCs contents in the execute stage of the pipeline. This can result in an incorrect BRC value written by the SRCCD instruction. The pipeline conflict can be avoided by placing the SRCCD instruction at least three instruction words from the bottom of the loop, as shown in Example 755 and Example 756.

Example 755. SRCCD Instruction With No Latency

RPTB endloop1 ... SRCCD *AR3, ALEQ

; ; ; ;

Placing the SRCCD instruction in this position ensures that current value of BRC will be written to memory.

ADD SUB STH endloop:

*AR1+,A *AR2,A A, *AR1+

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Example 756. SRCCD Instruction With a 3-Cycle Latency

RPTB endloop1 ... SRCCD *AR3, ALEQ NOP NOP NOP endloop:

;This ensures that current value of ; BRC will be written to memory.

There is also a 5-to-6-cycle latency when writing a new value to BRC from within a RPTB loop. The latencies described in Table 725 are relevant only if BRC is modified while a RPTB loop is active. See Example 757 for details.

Table 725. Latencies for Updating BRC From Within an RPTB Loop
Instruction STM ST MVDK MVMD #lk, BRC #lk, BRC Smem, BRC MMR, BRC Latency The next 5 instruction words must not contain the last instruction in the RPTB loop.

All other instructions that modify BRC

The next 6 instruction words must not contain the last instruction in the RPTB loop.

Example 757. Modifying BRC From Within an RPTB Loop

RPTB ... XC MVDK LD ADD SUB LD MPYA STL endloop: endloop1 2, Condition 5h, BRC *AR1+, A *AR2, A *AR3+, A *AR4+, T A A, *AR3+ ; ; ; ; ; ; ; If Condition is evaluated as true, write the new count value to BRC. These six instructions provide sufficient latency for the new BRC value to take effect before the next iteration begins.

7.5.8.2

Deactivating the Block-Repeat Active Flag (BRAF)

The 54x sets the block-repeat active flag (BRAF) to 1 to indicate that the repeat-block loop is active. BRAF is set or cleared in the decode stage of the first instruction of the repeat-block loop during the last loop iteration (BRC = 0). BRAF is tested by the device at the end of each loop iteration to determine whether the next prefetch will be from the top of the loop or not.
Pipeline
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BRAF can be deactivated in software to terminate the repeat-block prematurely. This, however, must be done early enough in the pipeline so that BRAF is cleared prior to the prefetch of the instruction at the top of the loop. Therefore, an instruction that clears BRAF (such as RSBX) must be placed at least six instructions words before the end of the repeat-block loop. This is shown in Example 758.

Example 758. BRAF Deactivation

RPTB ... RSBX NOP NOP NOP NOP NOP NOP endloop: endloop1 BRAF ; This ensures that the loop will ; terminate after completing this ; iteration. ; These six NOPs may be replaced by ; other instructions.

7.5.9

Latencies for the PMST

PMST fields OVLY, DROM, MP/MC, and IPTR configure the 54x memory space. When an instruction modifies one of these fields, a certain number of pipeline cycles must pass before the new memory space can be accessed. This latency is required because the PMST fields are updated in the read or execute stage of the pipeline while instructions in earlier pipeline stages may be accessing that memory space. In the case of program memory control via OVLY, IPTR, and MP/MC fields, the prefetch stage of the pipeline evaluates these bits. In the case of data memory control via the DROM field, the access or read stage evaluates this bit. If an external memory access occurs, additional cycles are required for operations affected by the changing bit. Any change in PMST fields is delayed until an in-process external access is completed. For example, if an external memory access is occurring while an instruction in the execute stage of the pipeline tries to modify OVLY, the update is delayed until the external bus cycle is completed. This, in turn, requires additional cycles to those listed in the following tables. Table 726 lists the latencies between instructions that write to the OVLY, IPTR, or MP/MC bit fields and those instructions that are subsequently fetched from the new memory space. Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

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Table 726. Latencies for OVLY, IPTR, and MP/MC Bits

(a) Latencies based on second-instruction category
Second Instruction First Instruction STM #lk, pmst ST #lk, pmst MVDK dmad, pmst MVMD MMR, pmst Category I 0 Category II 0 Category III 1 Category IV 2

All other instructions that modify OVLY, IPTR, MP/MC

(b) Categories for the second instruction

Category I BACC[D] CALA[D] FRET[D] FRETE[D] FBACC[D] FCALA[D]
Legend: pmst Notes: Destination operand pointing at PMST to modify OVLY, IPTR, MP/MC in either direct, indirect, or memory-mapped addressing modes

Category II BC[D] CC[D] RC[D] RET[D] RETE[D]

Category III B[D] BANZ[D] CALL[D] FB[D] FCALL[D]

Category IV INTR RETF[D] TRAP

1. Additional latency cycles are required if an external memory access is in progress when an instruction is trying to modify OVLY, IPTR, or MP/MC bit fields. 2. The second instruction loads PC with a new value that points to the modified program address range.

Example 759. OVLY Setup Followed by an Unconditional Branch (DP = 0)

ORM NOP NOP B #20h, PMST ; This instruction sets OVLY to 1.

onchip

; Branch to on-chip dual-access ; memory.

Example 760. OVLY Setup Followed by a Conditional Branch

MVDK BC 5h, PMST onchip,AEQ ; This instruction sets OVLY to 1. ; Branch to on-chip dual-access ; memory.

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Example 761. OVLY Setup Followed by a Return (DP = 0)

ANDM #0ffdfh, PMST NOP RET ; This instruction sets OVLY to 0. ; Return to off-chip memory.

Example 762. MP/MC Setup Followed by an Unconditional Delayed Call

STLM A, PMST NOP NOP CALLD offchip STM #k, AR1 ;This instruction sets MP/MC to 1.

; Call a routine in external ; program memory after executing ; this 2-word instruction.

Example 763. IPTR Setup Followed by a Software Trap

STM NOP NOP TRAP #k, PMST ; ; ; ; ; This instruction relocates interrupt vectors by writing to the IPTR bit field. Fetch a TRAP vector from the relocated vector table.

Table 727 lists the latencies between instructions that write to the DROM bit of PMST and those that subsequently read from or write to the DROM address range. Note: You are is responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

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Table 727. Latencies for the DROM Bit

(a) Latencies based on second-instruction category

Example 764. DROM Setup Followed by a Read Access (DP = 0)

ORM NOP NOP NOP LD #8h, PMST ; This instruction sets DROM = 1.

Example 765. DROM Setup Followed by a Dual-Read Access

STM NOP NOP MPY #k, PMST ; This instruction sets DROM = 1.

All other instructions that modify DROM 3

First instruction is... STM ST MVDK MVMD #lk, drom #lk, drom dmad, drom MMR, drom And second instruction is Category I, the latency is... 2

(b) Catagory for the second-instruction

Category I

All instructions that read from or write to the DROM address range

Legend: Notes:

drom Destination operand pointing at PMST to modify DROM bit in either direct , indirect, or memory-mapped addressing modes

1. Additional latency cycles are required if an external memory access is occurring at the time when an instruction is trying to modify the DROM bit field. 2. Any instruction not listed in this table that modifies DROM bit of PMST register has zero latency.

*AR3, A

; Reads from on-chip DROM

*AR3+,*AR4+, A

; This instruction reads from ; on-chip DROM.

Pipeline

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7.5.10 Latencies for Memory-Mapped Accesses to Accumulators

Accumulators A and B can be addressed as memory-mapped registers using memory-mapped, direct, or indirect addressing modes. Generally, it is not useful to access accumulators as memory-mapped registers, because the 54x instruction set supports direct accesses to the accumulators. Some examples of the instructions that support direct access to accumulators are ADD, SUB, AND, OR, XOR, LD, STH, STL, MAC, and MPYA. When the two accumulators are accessed using instructions that do not access them as memory-mapped registers, no pipeline latencies occur. In rare cases when you access the accumulators through the memory-mapped registers AG, AH, AL, BG, BH, and BL, you can use any instruction that uses memory-mapped, direct, or indirect addressing modes to access operands. Examples of such instructions are POPM AL and PSHM AH. Note that DP must be zero in order to access memory-mapped registers via direct addressing modes. A pipeline conflict can occur when two conditions are simultaneously met:

One instruction modifies an accumulator (either A or B) directly. The next instruction tries to read that accumulator as a memory-mapped register.

The conflict occurs because the first instruction updates an accumulator at the same time when the next instruction tries to read it as a memory-mapped register.

Example 766. Accumulator Access With a 1-Cycle Latency

ADD NOP Smem, A ; ; ; ; ; ; ; ; A is updated directly by this instruction. This conflict occurs because the next instruction tries to read A as a memory-mapped register. A one-cycle latency required. This instruction reads A as a memorymapped register.

PSHM

AL

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Example 767. Accumulator Access With No Conflict

(a)
ADD Smem, A ; ; ; ; ; A is updated directly by this instruction. No conflict occurs because the next instruction reads accumulator A directly. This instruction reads A directly.

NEG

(b)
STLM A, BH ; ; ; ; ; ; ; ; BH is written using memory-mapped addressing here. No conflict occurs because the next instruction also accesses the same accumulator as a memorymapped register. Reads BH as a memorymapped register.

PSHM

BH

(c)
STLM A, BH ; ; ; ; ; ; BH is written using memory-mapped addressing here. No conflict occurs because the next instruction accesses the same accumulator directly. This instruction reads B directly.

NEG

Table 728 lists the latencies between instructions that update an accumulator directly and instructions that access the same accumulator as a memorymapped register.

Note: You are responsible for rearranging instructions or inserting NOPs, if necessary, to accommodate latencies.

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Table 728. Latencies for Accumulators A and B When Used as Memory-Mapped Registers
(a) Latencies based on second-instruction category
First Instruction All 1-word instructions that directly modify A or B without accessing them as memory-mapped registers ADD LD SUB Smem, shift, src, dst Smem, shift, dst Smem, shift, src, dst Second Instruction Category I 1 Second Instruction Category II 0

All 2-word instructions that directly modify A or B without accessing them as memory-mapped registers

(b) Categories for the second instruction

Category I All instructions that read an accumulator as a memorymapped register (AG, AH, AL, BG, BH, and BL) without using a long-offset modifier. Category II All instructions that read an accumulator as memory-mapped register (AG, AH, AL, BG, BH, BL) using a long-offset modifier MVKD accum, Smem MVDM accum, MMR ADD LD SUB
Legend: MMR accum

accum, shift, src, dst accum, shift, dst accum, shift, src, dst

With extended shift value of 16 to 15

Any memory-mapped register Source operand pointing to AG, AH, AL, BG, BH, or BL using memory-mapped, direct, or indirect addressing modes Shift value between 16 and 15.

Example 768. Updating Accumulator With a 1-Cycle Latency

LD NOP Smem, 1, B ; ; ; ; ; ; ; ; B is updated directly by this instruction Conflict occurs because next instruction tries to read B as a memory-mapped register. A one-cycle latency is required. Reads BH as a memory-mapped register.

PSHM

BH

7-82

Pipeline Latencies

Example 769. Updating Accumulator With No Latency

(a)
MAC #K,A ; ; ; ; ; ; A is updated directly by this instruction. No latency is required since MAC is a 2word instruction. This instruction reads A as a memory-mapped register.

PSHM

AL

(b)
ADD Smem,A ; ; ; ; ; ; ; A is updated directly by this instruction. No latency is required since the next instruction uses a long offset modifier. This instruction reads A as a memorymapped register.

LD

*(AL),ASM

Pipeline

7-83

Chapter 8

On-Chip Peripherals
On-chip peripherals for the 54x are specific to the individual device. This chapter, along with Chapter 9, Serial Ports, and Chapter 10, External Bus Operation, describes all of the available on-chip peripherals; however, your device may contain only a subset of them. Enhanced peripherals, available on specific 54x devices, are not discussed at length in this chapter. For detailed information about enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, (literature number SPRU302). All 54x devices have general-purpose I/O pins, a timer, a clock generator, a software-programmable wait-state generator, and a programmable bankswitching module. Different types of serial ports, host port interfaces, and clock generators are device-specific peripherals. The serial ports are discussed in Chapter 9, Serial Ports, and the software-programmable wait-state generator and programmable bank-switching module are discussed in Chapter 10, External Bus Operation.

Topic
8.1 8.2 8.3 8.4 8.5 8.6

Page
Available On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37

8-1

Available On-Chip Peripherals / Peripheral Memory-Mapped Registers Available On-Chip Peripherals

8.1 Available On-Chip Peripherals

The following on-chip peripherals are available on 54x devices:

General-purpose I/O pins: XF and BIO Timer Clock generator Host port interface 8-bit standard (542, 545, 548, 549) 8-bit enhanced (5402, 5410 see note below) 16-bit enhanced (5420 see note below) Synchronous serial port (541, 545, and 546) Buffered serial port (542, 543, 545, 546, 548, and 549) Multichannel buffered serial port (McBSP) (5402, 5410, and 5420 see note below) Time-division multiplexed (TDM) serial port (542, 543, 548, and 549). Software-programmable wait-state generator Programmable bank-switching module

J J J

Note:

Enhanced Peripherals

For more detailed information on the enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

8.2 Peripheral Memory-Mapped Registers

Peripherals are operated and controlled by accessing memory-mapped control and data registers. These registers can also transfer data to and from the peripherals. Setting and clearing bits in the control registers can enable, disable, initialize, and dynamically reconfigure the peripherals. The operations of the serial ports and the timer are synchronized to the CPU through interrupts or interrupt polling. When peripherals are not in use, the internal clocks are shut off; thus, the peripherals consume less power in normal run mode or in idle mode. The peripheral registers are mapped into data page 0. Table 81 through Table 87 list the individual peripheral memory-mapped registers for each version of the 54x.

8-2

Peripheral Memory-Mapped Registers

Table 81. 541/541B Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A2F 30 31 32 3357 58 5957 Name DRR0 DXR0 SPC0 TIM PRD TCR SWWSR BSCR DRR1 DXR1 SPC1 CLKMD Description Serial port 0 data receive register Serial port 0 data transmit register Serial port 0 control register Reserved Timer register Timer period register Timer control register Reserved Software wait-state register Bank-switching control register Reserved Serial port 1 data receive register Serial port 1 data transmit register Serial port 1 control register Reserved Clock mode register (541B only) Reserved

On-Chip Peripherals

8-3

Peripheral Memory-Mapped Registers

Table 82. 542 Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A-2B 2C 2D-2F 30 31 32 33 34 35 3637 38 39 3A 3B 3C5F

Name BDRR0 BDXR0 BSPC0 BSPCE0 TIM PRD TCR SWWSR BSCR HPIC TRCV TDXR TSPC TCSR TRTA TRAD AXR0 BKX0 ARR0 BKR0

Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait-state register Bank-switching control register Reserved Host port interface control register Reserved TDM serial port data receive register TDM serial port data transmit register TDM serial port control register TDM serial port channel select register TDM serial port receive transmit register TDM serial port receive address register Reserved ABU transmit address register ABU transmit buffer-size register ABU receive address register ABU receive buffer-size register Reserved

8-4

Peripheral Memory-Mapped Registers

Table 83. 543 Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A-2F 30 31 32 33 34 35 36-37 38 39 3A 3B 3C-5F Name BDRR0 BDXR0 BSPC0 BSPCE0 TIM PRD TCR SWWSR BSCR TRCV TDXR TSPC TCSR TRTA TRAD AXR0 BKX0 ARR0 BKR0 Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait-state register Bank-switching control register Reserved TDM serial port data receive register TDM serial port data transmit register TDM serial port control register TDM serial port channel select register TDM serial port receive transmit register TDM serial port receive address register Reserved ABU transmit address register ABU transmit buffer-size register ABU receive address register ABU receive buffer-size register Reserved

On-Chip Peripherals

8-5

Peripheral Memory-Mapped Registers

Table 84. 545/545A Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A-2B 2C 2D-2F 30 31 32 33-37 38 39 3A 3B 3C-57 58 59-5F Name BDRR0 BDXR0 BSPC0 BSPCE0 TIM PRD TCR SWWSR BSCR HPIC DRR1 DXR1 SPC1 AXR0 BKX0 ARR0 BKR0 CLKMD Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait-state register Bank-switching control register Reserved Host port interface control register Reserved Serial port data receive register Serial port data transmit register Serial port control register Reserved ABU transmit address register ABU transmit buffer-size register ABU receive address register ABU receive buffer-size register Reserved Clock mode register (545A only) Reserved

8-6

Peripheral Memory-Mapped Registers

Table 85. 546/546A Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A-2F 30 31 32 33-37 38 39 3A 3B 3C-57 58 59-5F Name BDRR0 BDXR0 BSPC0 BSPCE0 TIM PRD TCR SWWSR BSCR DRR1 DXR1 SPC1 AXR0 BKX0 ARR0 BKR0 CLKMD Description Buffered serial port data receive register Buffered serial port data transmit register Buffered serial port control register Buffered serial port control extension register Timer register Timer period register Timer control register Reserved Software wait-state register Bank-switching control register Reserved Serial port data receive register Serial port data transmit register Serial port control register Reserved ABU transmit address register ABU transmit buffer-size register ABU receive address register ABU receive buffer-size register Reserved Clock mode register (546A only) Reserved

On-Chip Peripherals

8-7

Peripheral Memory-Mapped Registers

Table 86. 548 Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A-2B 2C 2D-2F 30 31 32 33 34 35 36-37 38 39 3A 3B

Name BDRR0 BDXR0 BSPC0 BSPCE0 TIM PRD TCR SWWSR BSCR HPIC TRCV TDXR TSPC TCSR TRTA TRAD AXR0 BKX0 ARR0 BKR0

Description Buffered serial port 0 data receive register Buffered serial port 0 data transmit register Buffered serial port 0 control register Buffered serial port 0 control extension register Timer register Timer period register Timer control register Reserved Software wait-state register Bank-switching control register Reserved Host port interface control register Reserved TDM serial port data receive register TDM serial port data transmit register TDM serial port control register TDM serial port channel select register TDM serial port receive transmit register TDM serial port receive address register Reserved ABU 0 transmit address register ABU 0 transmit buffer-size register ABU 0 receive address register ABU 0 receive buffer-size register

8-8

Peripheral Memory-Mapped Registers

Table 86 548 Peripheral Memory-Mapped Registers (Continued)

Address (Hex) 3C 3D 3E 3F 40 41 42 43 44-57 58 59-5F Name AXR1 BKX1 ARR1 BKR1 BDRR1 BDXR1 BSPC1 BSPCE1 CLKMD Description ABU 1 transmit address register ABU 1 transmit buffer-size register ABU 1 receive address register ABU 1 receive buffer-size register Buffered serial port 1 data receive register Buffered serial port 1 data transmit register Buffered serial port 1 control register Buffered serial port 1 control extension register Reserved Clock-mode register Reserved

Table 87. 549 Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A 2B Name BDRR0 BDXR0 BSPC0 BSPCE0 TIM PRD TCR SWWSR BSCR XSWR Description Buffered serial port 0 data receive register Buffered serial port 0 data transmit register Buffered serial port 0 control register Buffered serial port 0 control extension register Timer count register Timer period register Timer control register Reserved External interface software wait-state register External interface bank-switching control register Reserved Extended software wait-state register

On-Chip Peripherals

8-9

Peripheral Memory-Mapped Registers

Table 87 549 Peripheral Memory-Mapped Registers (Continued)

Address (Hex) 2C 2D-2F 30 31 32 33 34 35 36-37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44-57 58 59-5F Name HPIC TRCV TDXR TSPC TCSR TRTA TRAD AXR0 BKX0 ARR0 BKR0 AXR1 BKX1 ARR1 BKR1 BDRR1 BDXR1 BSPC1 BSPCE1 CLKMD Description Host port interface control register Reserved TDM serial port data receive register TDM serial port data transmit register TDM serial port control register TDM serial port channel select register TDM serial port receive transmit register TDM serial port receive address register Reserved ABU 0 transmit address register ABU 0 transmit buffer-size register ABU 0 receive address register ABU 0 receive buffer-size register ABU 1 transmit address register ABU 1 transmit buffer-size register ABU 1 receive address register ABU 1 receive buffer-size register Buffered serial port 1 data receive register Buffered serial port 1 data transmit register Buffered serial port 1 control register Buffered serial port 1 control extension register Reserved Clock-mode register Reserved

8-10

Peripheral Memory-Mapped Registers

Table 88. 5402 Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D2F 30 31 32 3337 38

Name DRR20 DRR10 DXR20 DXR10 TIM PRD TCR SWWSR BSCR SWCR HPIC TIM1 PRD1 TCR1 SPSA0

Description McBSP0 data receive register 2

39

SPSD0

3A3B 3C 3D

GPIOCR GPIOSR

McBSP0 data receive register 1 McBSP0 data transmit register 2 McBSP0 data transmit register 1 Timer0 register Timer0 period counter Timer0 control register Reserved

Bank-switching control register Reserved Software wait-state control register HPI control register Reserved Timer1 register

Software wait-state register

Timer1 period register Timer1 control register Reserved McBSP0 serial port sub-bank address register (See Table 811 on page 8-17.) McBSP0 serial port sub-bank data register (See Table 811 on page 8-17.) Reserved General purpose I/O pins control register General purpose I/O pins status register

On-Chip Peripherals
8-11

Peripheral Memory-Mapped Registers

Table 88. 5402 Peripheral Memory-Mapped Registers (Continued)

Address (Hex) 3E3F 40 41 42 43 4447 48 49 4A53 54 55 Name DRR21 DRR11 DXR21 DXR11 SPSA1 SPSD1 Description Reserved McBSP1 data receive register 2

DMPREC DMA channel priority and enable control register DMSA DMA sub-bank address register (See Table 812 on page 8-18.) DMA sub-bank data register with sub-bank address auto-increment (See Table 812 on page 8-18.)

56 57 58

DMSDI

DMSDN CLKMD

595F

8-12

McBSP1 data receive register 1 McBSP1 data transmit register 2 McBSP1 data transmit register 1 Reserved McBSP1 serial port sub-bank address register (See Table 811 on page 8-17.) McBSP1 serial port sub-bank data register (See Table 811 on page 8-17.) Reserved DMA sub-bank data register (See Table 812 on page 8-18.) Clock mode register Reserved

Peripheral Memory-Mapped Registers

Table 89. 5410 Peripheral Memory-Mapped Registers

Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D2F 30 31 32 33 34 35 3637 3A3F 38 39 Name DRR20 DRR10 DXR20 DXR10 TIM PRD TCR SWWSR BSCR SWCR HPIC DRR22 DRR12 DXR22 DXR12 SPSA2 SPSD2 SPSA0 SPSD0 Description McBSP0 data receive register 2 McBSP0 data receive register 1 McBSP0 data transmit register 2 McBSP0 data transmit register 1 Timer register Timer period counter Timer control register Reserved Software wait-state register Bank-switching control register Reserved Software wait-state control register HPI control register Reserved McBSP2 data receive register 2 McBSP2 data receive register 1 McBSP2 data transmit register 2 McBSP2 data transmit register 1 McBSP2 serial port sub-bank address register (See Table 811 on page 8-17.) McBSP2 serial port sub-bank data register (See Table 811 on page 8-17.) Reserved Reserved McBSP0 serial port sub-bank address register (See Table 811 on page 8-17.) McBSP0 serial port sub-bank data register (See Table 811 on page 8-17.)

On-Chip Peripherals

8-13

Peripheral Memory-Mapped Registers

Table 89. 5410 Peripheral Memory-Mapped Registers (Continued)

Address (Hex) 40 41 42 43 4447 48 49 4A53 54 55 56
57{ 58

Name DRR21 DRR11 DXR21 DXR11 SPSA1 SPSD1

Description McBSP1 data receive register 2 McBSP1 data receive register 1 McBSP1 data transmit register 2 McBSP1 data transmit register 1 Reserved McBSP1 serial port sub-bank address register (See Table 811 on page 8-17.) McBSP1 serial port sub-bank data register (See Table 811 on page 8-17.) Reserved

DMPREC DMA channel priority and enable control register DMSA DMSDI DMSDN
CLKMD

DMA sub-bank-address register DMA sub-bank data register with sub-bank address auto-increment (See Table 812 on page 8-18.) DMA sub-bank data register (See Table 812 on page 8-18.) Clock mode register Reserved

59 5F

8-14

Peripheral Memory-Mapped Registers

Table 810. 5420 Peripheral Memory-Mapped Registers For Each DSP Subsystem
Address (Hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D2F 30 31 32 33 34 35 3637 38 39

Name DRR20 DRR10 DXR20 DXR10 TIM PRD TCR SWWSR BSCR SWCR HPIC DRR22 DRR12 DXR22 DXR12 SPSA2 SPSD2 SPSA0 SPSD0

Description MCBSP 0 data receive register 2 MCBSP 0 data receive register 1 MCBSP 0 data transmit register 2 MCBSP 0 data transmit register 1 Timer register Timer period counter Timer control register Reserved Software wait-state register Bank switching control register Reserved Software wait-state control register HPI control register Reserved MCBSP 2 data receive register 2 MCBSP 2 data receive register 1 MCBSP 2 data transmit register 2 MCBSP 2 data transmit register 1 MCBSP 2 serial port sub-bank address register (See Table 811 on page 8-17.) MCBSP 2 serial port sub-bank data register (See Table 811 on page 8-17.) Reserved MCBSP 0 serial port sub-bank address register (See Table 811 on page 8-17.) MCBSP 0 serial port sub-bank data register (See Table 811 on page 8-17.)

On-Chip Peripherals

8-15

Peripheral Memory-Mapped Registers

Table 810. 5420 Peripheral Memory-Mapped Registers For Each DSP Subsystem (Continued)
Address (Hex) 3A3B 3C 3D3F 40 41 42 43 4447 48 49 4A53 54 55 56 57 58 595F Name GPIO DRR21 DRR11 DXR21 DXR11 SPSA1 SPSD1 DMPREC DMSA DMSDI DMSDN CLKMD Description Reserved General purpose I/O register Reserved MCBSP 1 data receive register 2 MCBSP 1 data receive register 1 MCBSP 1 data transmit register 2 MCBSP 1 data transmit register 1 Reserved MCBSP 1 serial port sub-bank address register (See Table 811 on page 8-17.) MCBSP 1 serial port sub-bank data register (See Table 811 on page 8-17.) Reserved DMA channel priority and enable control register DMA sub-bank address register (See Table 812 on page 8-18.) DMA sub-bank data register with sub-bank address auto-increment (See Table 812 on page 8-18.) DMA sub-bank data register (See Table 812 on page 8-18.) Clock mode register Reserved

8-16

Peripheral Memory-Mapped Registers

Table 811. 5402/5410/5420 McBSP Sub-addressed Registers

McBSP0 McBSP1 McBSP2 Address Address Address Name Name Name (Hex) (Hex) (Hex) SPCR10 SPCR20 RCR10 RCR20 XCR10 XCR20 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 SPCR11 49 49 49 49 49 49 49 49 49 49 49 49 49 49 49 SPCR12 SPCR22 RCR12 RCR22 XCR12 XCR22 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 Subaddress (Hex) Description 00 01 02 03 04 05 06 07 08 09 Serial port control register 1 Serial port control register 2 Receive control register 1 Receive control register 2

SPCR21 RCR11 RCR21 XCR11 Transmit control register 1 Transmit control register 2 Sample rate generator register 1 Sample rate generator register 2 XCR21 SRGR10 SRGR20 MCR10 MCR20 SRGR11 SRGR12 SRGR22 MCR12 MCR22 SRGR21 MCR11 Multichannel register 1 Multichannel register 2 MCR21 RCERA0 RCERB0 XCERA0 XCERB0 PCR0 RCERA1 RCERB1 XCERA1 XCERB1 PCR1 RCERA2 RCERA2 XCERA2 XCERA2 PCR2 0A 0B Receive channel enable register partition A Receive channel enable register partition B 0C 0D 0E Transmit channel enable register partition A Transmit channel enable register partition B Pin control register

On-Chip Peripherals

8-17

Peripheral Memory-Mapped Registers

Table 812. 5402/5410/5420 DMA Sub-addressed Registers

DMA Name DMSRC0 DMDST0 Address (Hex) 56/57{ Subaddress (Hex) 00 01 02 03 04 05 06 07 08 09

Description DMA channel 0 source address register

56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ DMA channel 0 destination address register DMA channel 0 element count register DMCTR0 DMSFC0 DMA channel 0 sync select and frame count register DMA channel 0 transfer mode control register DMA channel 1 source address register DMMCR0 DMSRC1 DMDST1 DMA channel 1 destination address register DMA channel 1 element count register DMCTR1 DMSFC1 DMA channel 1 sync select and frame count register DMA channel 1 transfer mode control register DMA channel 2 source address register DMMCR1 DMSRC2 DMDST2 0A 0B DMA channel 2 destination address register DMA channel 2 element count register DMCTR2 DMSFC2 0C 0D 0E 0F 10 11 DMA channel 2 sync select and frame count register DMA channel 2 transfer mode control register DMA channel 3 source address register DMMCR2 DMSRC3 DMDST3 DMA channel 3 destination address register DMA channel 3 element count register DMCTR3 DMSFC3 12 13 14 15 16 DMA channel 3 sync select and frame count register DMA channel 3 transfer mode control register DMA channel 4 source address register DMMCR3 DMSRC4 DMDST4 DMA channel 4 destination address register DMA channel 4 element count register DMCTR4 Accesses to address 57h update the sub-addressed register and post-increment the sub-address contained in
DMSBAR. Accesses to 56h update the sub-addressed register without modifying DMSBAR.

8-18

Peripheral Memory-Mapped Registers

Table 812. 5402/5410/5420 DMA Sub-addressed Registers (Continued)

DMA Name DMSFC4 Address (Hex) 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ 56/57{ Subaddress (Hex) 17 18 19

Description DMA channel 4 sync select and frame count register DMA channel 4 transfer mode control register DMA channel 5 source address register

DMMCR4 DMSRC5 DMDST5 1A 1B DMA channel 5 destination address register DMA channel 5 element count register DMCTR5 DMSFC5 1C 1D 1E 1F 20 21 22 23 24 25 26 27 DMA channel 5 sync select and frame count register DMA channel 5 transfer mode control register DMMCR5 DMSRCP DMDSTP DMIDX0 DMIDX1 DMFRI0 DMFRI1 DMGSA DMA source program page address (common channel) DMA destination program page address (common channel) DMA element index address register 0 DMA element index address register 1 DMA frame index register 0 DMA frame index register 1 DMA global source address reload register DMGDA DMA global destination address reload register DMA global count reload register DMGCR DMGFR DMA global frame count reload register Accesses to address 57h update the sub-addressed register and post-increment the sub-address contained in
DMSBAR. Accesses to 56h update the sub-addressed register without modifying DMSBAR.

On-Chip Peripherals

8-19

General-Purpose I/O

8.3 General-Purpose I/O

The 54x offers general-purpose I/O through two dedicated pins that are software controlled. The two dedicated pins are the branch control input pin (BIO) and the external flag output pin (XF).

8.3.1

Branch Control Input Pin (BIO)

BIO can be used to monitor the status of peripheral devices. It is especially useful as an alternative to using an interrupt when time-critical loops must not be disturbed. A branch can be conditionally executed dependent upon the state of the BIO input. Of the instructions that use BIO, the execute conditionally (XC) instruction samples the condition of BIO during the decode phase of the pipeline; all other conditional instructions (branch, call, and return) sample BIO during the read phase of the pipeline.

8.3.2

External Flag Output Pin (XF)

XF can be used to signal external devices. The XF pin is controlled using software. It is driven high by setting the XF bit (in ST1) and is driven low by clearing the XF bit. The set status register bit (SSBX) and reset status register bit (RSBX) instructions can be used to set and clear XF, respectively. XF is also set high at device reset. Figure 81 shows the relationship between the time the SSBX or RSBX instruction is fetched and the time the XF pin is set or reset (refer to the 54x data sheet for timing specifications). The XF timing shown is for a sequence of single-cycle instructions. Actual timing can vary with different instruction sequences.

Figure 81. External Flag Timing Diagram

CLKOUT SSBX or RSBX instruction A(150) prefetch XF fetch decode access read write Delay

8-20

Timer

8.4 Timer
The on-chip timer is a software-programmable timer that consists of three registers and can be used to periodically generate interrupts. The timer resolution is the CPU clock rate of the processor.The high dynamic range of the timer is achieved with a 16-bit counter with a 4-bit prescaler. The 5402 and the 5420 have two on-chip timers.

8.4.1

Timer Registers
The on-chip timer consists of three memory-mapped registers (TIM, PRD, and TCR). These three registers and their respective timer addresses are listed in Table 813.

Table 813. Timer Registers

Timer 0 Address 0024h 0025h 0026h Timer 1 Address (5402 only) 0030h 0031h 0032h

Register TIM PRD TCR

Description Timer register Timer period register Timer control register

Timer register (TIM). The 16-bit memory-mapped timer register (TIM) is loaded with the period register (PRD) value and decremented. Timer period register (PRD). The 16-bit memory-mapped timer period register (PRD) is used to reload the timer register (TIM). Timer control register (TCR). The 16-bit memory-mapped timer control register (TCR) contains the control and status bits of the timer. The TCR bit fields are shown in Figure 82 and described in Table 814.

On-Chip Peripherals

8-21

Timer

Figure 82. Timer Control Register (TCR) Diagram

1512 11 10 96 5 4 30 Reserved Soft Free PSC TRB TSS TDDR

Table 814. Timer Control Register (TCR) Bit Summary

Bit 1512 11 Name Reserved Soft Reset Value 0 Function Reserved; always read as 0. Used in conjunction with the Free bit to determine the state of the timer when a breakpoint is encountered in the HLL debugger. When the Free bit is cleared, the Soft bit selects the timer mode. Soft = 0 Soft = 1 10 Free 0 The timer stops immediately. The timer stops when the counter decrements to 0.

Used in conjunction with the Soft bit to determine the state of the timer when a breakpoint is encountered in the HLL debugger. When the Free bit is cleared, the Soft bit selects the timer mode. Free = 0 Free = 1 The Soft bit selects the timer mode. The timer runs free regardless of the Soft bit.

96

PSC

Timer prescaler counter. Specifies the count for the on-chip timer. When PSC is decremented past 0 or the timer is reset, PSC is loaded with the contents of TDDR and the TIM is decremented. Timer reload. Resets the on-chip timer. When TRB is set, the TIM is loaded with the value in the PRD and the PSC is loaded with the value in TDDR. TRB is always read as a 0. Timer stop status. Stops or starts the on-chip timer. At reset, TSS is cleared and the timer immediately starts timing. TSS = 0 TSS = 1 The timer is started. The timer is stopped.

TRB

TSS

30

TDDR

0000

Timer divide-down ratio. Specifies the timer divide-down ratio (period) for the on-chip timer. When PSC is decremented past 0, PSC is loaded with the contents of TDDR.

8-22

Timer

8.4.2

Timer Operation
The timer is an on-chip down-counter that can be used to periodically generate CPU interrupts. The timer is driven by a prescaler that is decremented by 1 at every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt (TINT) is generated and the down-counter is reloaded with the period value. See section 6.10, Interrupts, on page 6-26, for more details about interrupts. Figure 83 shows a logical block diagram of the timer. It consists of two basic blocks: the main timer block, consisting of PRD and TIM; and a prescaler block, consisting of TDDR and PSC bits in TCR. The timer is clocked by the CPU clock.

Figure 83. Timer Block Diagram

SRESET TRB

PRD

TDDR CPU clock

TIM Borrow

PSC Borrow

TSS

TINT

TOUT

Under normal operation, TIM is loaded with the contents of PRD when TIM decrements to 0. The contents of PRD are also loaded into TIM when the device is reset (SRESET input in Figure 83) or when the timer is individually reset (TRB input in Figure 83). TIM is clocked by the prescaler block. Each output clock from the prescaler block decrements TIM by 1. The output of the main timer block is the timer interrupt (TINT) signal that is sent to the CPU and to the timer output (TOUT) pin. The duration of the TOUT pulse is equal to the period of CLKOUT.
Note that on the 5402, the timer1 output (TOUT1) is only available when the HPI-8 is disabled, and the TOUT1 bit is set in the GPIO control register.

On-Chip Peripherals

8-23

Timer

The prescaler block has two elements similar to the TIM and PRD. These are the prescale counter (PSC) and timer divide-down ratio (TDDR). Both PSC and TDDR are fields in the timer control register (TCR). Under normal operation, PSC is loaded with the contents of TDDR when PSC decrements to 0. The contents of TDDR are also loaded into PSC when the device is reset or when the timer is individually reset. PSC is clocked by the device CPU clock. Each CPU clock decrements PSC by 1. PSC can be read by reading TCR, but it cannot be written to directly. The timer can be stopped by making use of the TSS input to turn off the clock input to the timer. Stopping the timers operation allows the device to run in a low-power mode when the timer is not needed. The timer interrupt (TINT) rate is equal to the CPU clock frequency divided by two independent factors: TINT rate

+t

1
c(C)

+t

c(C)

(TDDR

) 1)
1

(PRD

) 1)

In the equation, tc(C) is the period of CPU clock, u is the sum of the TDDR contents plus 1, and v is the sum of the PRD contents plus 1. The current value in the timer can be read by reading TIM; PSC can be read by reading TCR. Because it takes two instructions to read both registers, there may be a change between the two reads as the counter decrements. Therefore, when precise timing measurements are needed, it is more accurate to stop the timer before reading these two values. The timer can be stopped by setting the TSS bit and restarted by clearing it. The timer can be used to generate a sample clock for peripheral circuits such as an analog interface. This can be accomplished by using the TOUT signal to clock a device or by using the interrupt to periodically read a register. The timer is initialized with the following steps: 1) Stop the timer by writing a 1 to TSS in TCR. 2) Load PRD. 3) Start the timer by reloading TCR to initialize TDDR. Enable the timer by setting TSS to 0 and TRB to 1 to reload the timer period.
Note that on the 5402, the timer1 output (TOUT1) is only available when the HPI-8 is disabled, and the TOUT1 bit is set in the GPIO control register.

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Optionally, the timer interrupt may be enabled by (assuming INTM = 1): 1) Clearing any pending timer interrupts by writing a 1 to TINT in the IFR. 2) Enabling the timer interrupt by writing a 1 to TINT in the IMR. 3) Enabling interrupts globally, if necessary, by clearing INTM to 0. At reset, TIM and PRD are set to a maximum value of FFFFh. The timer dividedown ratio (TDDR) field of the TCR is cleared to 0 and the timer is started.

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8.5 Clock Generator

The clock generator allows system designers to select the clock source. The sources that drive the clock generator are:

A crystal resonator with the internal oscillator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the 54x. The CLKMD pins must be configured to enable the internal oscillator. An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected.

The clock generator on the 54x devices consists of an internal oscillator and a phase-locked loop (PLL) circuit. Currently, there are two different types of PLL circuits on 54x devices. Some devices have hardware-configurable PLL circuits while others have software-programmable PLL circuits. The 541, 542, 543, 545, and 546 devices use a hardware-configurable PLL. The 541B, 545A, 546A, 548, 549, 5402, 5410, and 5420 devices use a software-programmable PLL.

8.5.1

Hardware-Configurable PLL
The PLL functions with a lower external frequency source than the machine cycle rate of the CPU. This feature reduces high-frequency noise from a highspeed switching clock. The internal oscillator or the external clock source is fed into the PLL. The internal CPU clock is generated by multiplying the external clock source or the internal oscillator frequency by a factor N (PLL N). If you are using the internal oscillator circuit, the clock source is divided by 2 to generate the internal CPU clock. If you are using the external clock, the internal CPU clock is a factor of PLL N.

The PLL has a maximum operating frequency of 40 MHz on a 25-ns 54x device. The PLL requires a transitory locking time of 50 s. The locking time is necessary during reset and recovery from the IDLE3 power-down mode. See section 6.11, Power-Down Modes, on page 6-50, and section 10.5.2, IDLE3, on page 10-26, for more information. The clock mode is determined by the CLKMD1, CLKMD2, and CLKMD3 pins. Table 815 shows how these pins select the clock mode. For non-PLL use, the frequency of the CPU clock is half the crystals oscillating frequency or the external clock frequency. The clock mode must not be reconfigured with the clock mode pins during normal operation. During IDLE3 mode, the clock mode can be reconfigured after CLKOUT is set high.
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Table 815. Clock Mode Configurations

Mode Select Pins CLKMD1 0 1 1 0 0 1 1 0 CLKMD2 0 1 0 1 0 1 0 1 CLKMD3 0 0 0 0 1 1 1 1 Option 1 Clock Mode

 3 with external source PLL  2 with external source PLL  3 with oscillator enabled PLL  1.5 with external source
PLL Divide-by-2 with external source Divide-by 2 with oscillator enabled PLL

 5 with external source PLL  4 with external source PLL  5 with oscillator enabled PLL  4.5 with external source
PLL Divide-by-2 with external source Divide-by-2 with oscillator enabled PLL

Option 2

 1 with external source

 1 with external source

Stop mode

Stop mode

An individual device is either an Option 1 or Option 2 clock-mode device. The PLL is disabled. The system clock is not provided to CPU/peripherals. The function of the stop mode is equivalent to that of the power-down mode of IDLE3; however, the IDLE 3 instruction is recommended rather than stop mode to realize full power saving, since IDLE3 stops clocks synchronously and can be exited with an interrupt.

8.5.2

Software-Programmable PLL (541B/545A/546A/548/549/5402/5410/5420)

The software-programmable PLL features a high level of flexibility, and includes: a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

PLL mode. The input clock (CLKIN) is multiplied by 1 of 31 possible ratios from 0.25 to 15. These ratios are achieved using the PLL circuitry. DIV (divider) mode. The input clock (CLKIN) is divided by 2 or 4. When DIV mode is used, all of the analog parts, including the PLL circuitry, are disabled in order to minimize power dissipation.

Immediately following reset, the clock mode is determined by the values of the three external pins, CLKMD1, CLKMD2, and CLKMD3. The modes corresponding to the CLKMD pins are shown in Table 816 and Table 817.
The VC5420 device does not have CLKMD pins. Following reset, the 5420 operates in bypass mode (PLL is off).

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Table 816. Clock Mode Settings at Reset (541B/545A/546A/548/549/5410)

CLKMD CLKMD1 CLKMD2 CLKMD3 Reset Value 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0000h 1000h 2000h 4000h 6000h 7000h 0007h Clock Mode Divide-by-2 with external source Divide-by-2 with external source Divide-by-2 with external source Divide-by-2, internal oscillator enabled Divide-by-2 with external source Divide-by-2, internal oscillator enabled{ PLL

 1 with external source

Stop mode

Reserved on 549 and 5410

Table 817. Clock Mode Settings at Reset (5402)

CLKMD CLKMD1 CLKMD2 CLKMD3 Reset Value 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 E007h 9007h 4007h 1007h F007h 0000h F000h Clock Mode
PLL x 15, internal oscillator enabled PLL x 10, internal oscillator enabled PLL x 5, internal oscillator enabled PLL x 2, internal oscillator enabled PLL x 1, internal oscillator enabled 1/2 (PLL disabled), internal oscillator enabled 1/4 (PLL disabled), internal oscillator enabled Reserved (bypass mode)

Following reset, the software-programmable PLL can be programmed to any configuration desired. The following clock mode pin combinations enable the PLL during reset: CLKMD (31) = 000 110 on 5402, and CLKMD (31) = 101 on all other devices. When these clock mode pin combinations are used,
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the internal PLL lock timer is not active; therefore, the system must delay releasing reset in order to allow for the PLL lock-time delay. The programming of the PLL is loaded in the 16-bit memory-mapped (address 58h) clock mode register (CLKMD). The CLKMD is used to define the clock configuration of the PLL clock module. The CLKMD bit fields are shown in Figure 84 and described in Table 818. Note that upon reset, the CLKMD is initialized with a predetermined value dependent only upon the state of the CLKMD(13) pins (see Table 816).

1512 11 103 2 1 0 PLLMUL
R/W

Figure 84. Clock Mode Register (CLKMD) Diagram

PLLDIV
R/W

PLLCOUNT
R/W

PLLON/OFF
R/W

PLLNDIV
R/W

PLLSTATUS
R

When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are dont cares, and their contents are indeterminate.

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Table 818. Clock Mode Register (CLKMD) Bit Summary

Bit 1512 11 103 Name PLLMUL PLLDIV Function PLL multiplier. Defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV, as shown in Table 819 on page 8-31. PLL divider. Defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV, as shown in Table 819 on page 8-31. PLL counter value. Specifies the number of input clock cycles (in increments of 16 cycles) for the PLL lock timer to count before the PLL begins clocking the processor after the PLL is started. The PLL counter is a down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the PLL counter decrements by 1. See section Using the PLLCOUNT Programmable Lock Timer, on page 8-31 for more information about PLLCOUNT. The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked, so that only valid clock signals are sent to the device. 2 PLLON/OFF PLL on/off. Enables or disables the PLL part of the clock generator in conjunction with PLLNDIV. PLLON/OFF and PLLNDIV both force the PLL to operate; when PLLON/ OFF is high, the PLL runs independently of the state of PLLNDIV: PLLON/OFF 0 0 1 1 PLLNDIV 0 1 0 1 PLL State off on on on

PLLCOUNT

PLLNDIV

PLL clock generator select. Determines whether the clock generator works in PLL mode or in divider (DIV) mode, thus defining the frequency multiplier in conjunction with PLLMUL and PLLDIV. PLLNDIV = 0 PLLNDIV = 1 Divider (DIV) mode is used. PLL mode is used.

PLLSTATUS

PLL status. Indicates the mode that the clock generator is operating. PLLSTATUS = 0 PLLSTATUS = 1 Divider (DIV) mode PLL mode

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Table 819. PLL Multiplier Ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL
PLLNDIV 0 0 1 1 1 1 PLLDIV x x 0 0 1 1 PLLMUL 0 14 15 0 14 15 0 or even odd Multiplier 0.5 0.25 PLLMUL + 1 1 (bypass)} (PLLMUL + 1) PLLMUL

B4

B2

CLKOUT = CLKIN Multiplier This is the default mode for the 5420 after reset.

Programming Considerations When Using the Software-Programmable PLL

The software-programmable PLL offers many different options in startup configurations, operating modes, and power-saving features. Programming considerations and several software examples are presented here to illustrate the proper use of the software-programmable PLL at start-up, when switching between different clocking modes, and before and after IDLE 1/IDLE 2/IDLE 3 instruction execution.

Using the PLLCOUNT Programmable Lock Timer

During the lockup period, the PLL should not be used to clock the 54x. The PLLCOUNT programmable lock timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is achieved. The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided by 16. The resulting lockup delay can therefore be set from 0 to 255 16 CLKIN cycles. The lock timer is activated when the clock generator operating mode is switched from DIV to PLL (see section Switching From DIV Mode to PLL Mode, on page 8-32). During the lockup period, the clock generator continues to operate in DIV mode; after the PLL lock timer has decremented to 0, the PLL begins clocking the 54x.
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The decimal preset value, PLLCOUNT, is:

PLLCOUNT

u LockupTime 16 T
CLKIN

where TCLKIN is the input reference clock period and LockupTime is the required PLL lockup time as shown in Figure 85.

Figure 85. PLL Lockup Time Versus CLKOUT Frequency

60 55 50 45 Lockup Time ( s) 40 35 30 25 20 15 10 5 0 2.5 10 20 30 40 50 60 70 80 100 CLKOUT frequency (MHz) 23 22 16 17 16 19 24 29 549, and 5410 35 44 All other 59

Switching Clock Mode From DIV Mode to PLL Mode

Several circumstances may require switching from DIV mode to PLL mode; however, note that if the PLL is not locked when switching from DIV mode to PLL mode, the PLL lockup time delay must be observed before the mode switch occurs to ensure that only proper clock signals are sent to the device. It is, therefore, important to know whether or not the PLL is locked when switching operating modes. The PLL is unlocked on power-up, after changing the PLLMUL or PLLDIV values, after turning off the PLL (PLLON/OFF = 0), or after loss of input reference clock. Once locked, the PLL remains locked even in DIV mode as long as the PLL had been previously locked and has not been turned off (PLLON/ OFF stays 1), and the PLLMUL and PLLDIV values have not been changed since the PLL was locked. Switching from DIV mode to PLL mode (setting PLLNDIV to 1) activates the PLLCOUNT programmable lock timer (when PLLCOUNT is preloaded with a
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nonzero value) and this can be used to provide a convenient method for implementing the lockup time delay. The PLLCOUNT lock timer feature should be used in the previously described situations where the PLL is unlocked unless a reset delay is used to implement the lockup delay, or the PLL is not used. Switching from DIV mode to PLL mode is accomplished by loading CLKMD. The following procedure describes switching from DIV mode to PLL mode when the PLL is not locked. When performing this mode switch with the PLL already locked, the effect is the same as when switching from PLL mode to DIV mode, but in the reverse order. In this case, the delays of when the new clock mode takes effect are the same. When switching from DIV mode to PLL mode with the PLL unlocked, or when the mode change will result in unlocked operation, the PLLMUL, PLLDIV, and PLLNDIV bits are set to select the desired frequency multiplier as shown in Table 819 on page 8-31, and the PLLCOUNT bits are set to select the required lockup time delay. Note that PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF can only be modified when in DIV mode. Once the PLLNDIV bit is set, the PLLCOUNT timer begins being decremented from its preset value. When the PLLCOUNT timer reaches 0, the switch to PLL mode takes effect after 6 CLKIN cycles plus 3.5 PLL cycles. When the switch to PLL mode is completed, the PLLSTATUS bit in CLKMD is read as 1. Note that during the PLL lockup period, the 54x continues operating in DIV mode. The following code can be used to switch from DIV mode to PLL 3 mode, with a CLKIN frequency of 13 MHz and PLLCOUNT = 41 (decimal):
STM #0010000101001111b, CLKMD

Switching Clock Mode From PLL Mode to DIV Mode

When switching from PLL mode to DIV mode, the PLLCOUNT delay does not occur and the switch between the two modes takes place after a short transition delay. The switch from PLL mode to DIV mode is also accomplished by loading CLKMD. The PLLNDIV bit is cleared to 0, selecting DIV mode, and the PLLMUL bits are set to select the desired frequency multiplier as shown in Table 819 on page 8-31. The switch to DIV mode takes effect in 6 CLKIN cycles plus 3.5 PLL cycles for all PLLMUL values except 1111b. For a PLLMUL value of 1111b, the switch to DIV mode takes effect in 12 CLKIN cycles plus 3.5 PLL cycles. When the switch to DIV mode is completed, the PLLSTATUS bit in CLKMD is read as 0. Example 81 shows a code sequence that can be used to switch from PLL 3 mode to divide-by-2 mode. Note that the PLLSTATUS bit is polled to determine
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when the switch to DIV mode has taken effect, and then the STM instruction is used to turn off the PLL at this point.

Example 81. Switching Clock Mode From PLL 3 Mode to Divide-by-2 Mode
STM TstStatu: LDM AND BC STM #0b, CLKMD ;switch to DIV mode CLKMD, A #01b, A ;poll STATUS bit TstStatu, ANEQ #0b, CLKMD ;reset PLLON/OFF when STATUS ;is DIV mode

Changing the PLL Multiplier Ratio

When switching from one PLL multiplier ratio to another multiplier ratio is required, the clock generator must first be switched from PLL mode to DIV mode before selecting the new multiplier ratio; switching directly from one PLL multiplier ratio to another multiplier ratio is not supported. In order to switch from one PLL multiplier ratio to another multiplier ratio, the following steps must be followed: 1) Clear the PLLNDIV bit to 0, selecting DIV mode. 2) Poll the PLLSTATUS bit until a 0 is obtained, indicating that DIV mode is enabled. 3) Modify CLKMD to set the PLLMUL, PLLDIV, and PLLNDIV bits to the desired frequency multiplier as shown in Table 819 on page 8-31 4) Set the PLLCOUNT bits to the required lock-up time. Once the PLLNDIV bit is set, the PLLCOUNT timer begins being decremented from its preset value. When the PLLCOUNT timer reaches 0, the new PLL mode takes effect after 6 CLKIN cycles plus 3.5 PLL cycles. Note that a direct switch between divide-by-2 mode and divide-by-4 mode is not possible. To switch between these two modes, the clock generator must first be set to PLL mode with an integer-only (nonfractional) multiplier ratio and then set back to DIV mode in the desired divider configuration (see section Switching From DIV Mode to PLL Mode, on page 8-32). Example 82 shows a code sequence that can be used to switch the clock mode from PLL X mode to PLL 1 mode.
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Example 82. Switching Clock Mode From PLL X Mode to PLL 1 Mode
STM #0b, CLKMD ;switch to DIV mode TstStatu: LDM CLKMD, A AND #01b, A ;poll STATUS bit BC TstStatu, ANEQ STM #0000001111101111b, CLKMD ;switch to PLL 1 mode

PLL Operation Immediately Following Reset

Immediately following reset, the clock mode is determined by the values of the three external pins, CLKMD1, CLKMD2, and CLKMD3. Switching from the initial clock mode to any other mode can easily be accomplished by changing the contents of CLKMD. If use of the internal oscillator with an external crystal is desired, the device CLKMD pins must be configured at reset to enable the internal oscillator. See Table 816 and Table 817 on page 8-28 for external pin values and available modes on each device. (The internal oscillator option is not available on the 5420.) The following code can be used to switch from divide-by-2 mode to PLL 3 mode:
STM #0010000101001111b, CLKMD

PLL Considerations When Using IDLE Instruction

When using one of the IDLE instructions to reduce power requirements, proper management of the PLL is important. The clock generator consumes the least power when operating in DIV mode with the PLL disabled. Therefore, if power dissipation is a significant consideration, it is desirable to switch from PLL mode to DIV mode and disable the PLL, before executing an IDLE 1, IDLE 2, or IDLE 3 instruction. This is accomplished as explained in section Switching From PLL Mode to DIV Mode, on page 8-33. After waking up from IDLE1/IDLE2/IDLE3, the clock generator can be reprogrammed to PLL mode as explained in section Switching From DIV Mode to PLL Mode, on page 8-32. Note that when the PLL is stopped during an IDLE state and the 54x device is restarted and the clock generator is switched back to PLL mode, the PLL lockup delay occurs in the same manner as in a normal device startup. Therefore, in this case, the lockup delay must also be accounted for, either externally or by using the PLL lockup counter timer. Example 83 shows a code sequence that switches the clock generator from PLL 3 mode to divide-by-2 mode, turns off the PLL, and enters IDLE3. After waking up from IDLE3, the clock generator is switched from DIV mode to PLL 3 mode using a single STM instruction, with a PLLCOUNT of 64 (decimal) used for the lock timer value.
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Example 83. Switching Clock From PLL 3 Mode to Divide-by-2 Mode, Turning Off the PLL, and Entering IDLE3
STM TstStatu: LDM AND BC STM IDLE3 (After IDLE3 wake-up switch the PLL from DIV mode to PLL STM 3 mode) #0b, CLKMD CLKMD, A #01b, A TstStatu, ANEQ #0b, CLKMD ;switch to DIV mode ;poll STATUS bit ;reset PLLON_OFF when STATUS ;is DIV mode

#0010001000000111b, CLKMD ;PLLCOUNT = 64 (decimal)

PLL Considerations When Using the Bootloader

The ROM on the 545A and 546A contains a bootloader program that can be used to load programs into RAM for execution following reset. When using this bootloader with the software-programmable PLL, several considerations are important for proper system operation. On the 545A and 546A, for compatibility, the bootloader configures the PLL to the same mode as would have resulted if the same CLKMD(13) input bits had been provided to the option-1 or option-2 hardware-programmable PLL (see Table 815 on page 8-27), according to whether the 545A or 546A is an option-1 or option-2 device. Once the bootloader program has finished executing and control is transferred to the users program, the PLL can be reprogrammed to any desired configuration.

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8.6 Host Port Interface

The standard host port interface (HPI) is available on the 542, 545, 548, and 549 devices. The HPI is an 8-bit parallel port that interfaces a host device or host processor to the 54x. Information is exchanged between the 54x and the host device through on-chip 54x memory that is accessible by both the host and the 54x. Enhanced host port interfaces are available on the 5402, 5410 (HPI-8) and 5420 (HPI-16) devices. This chapter does not describe these enhanced HPIs. For more information on the HPI-8 and HPI-16, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302. The HPI interfaces to the host device as a peripheral, with the host device as master of the interface, facilitating ease of access by the host. The host device communicates with the HPI through dedicated address and data registers, to which the 54x does not have direct access, and the HPI control register, using the external data and interface control signals (see Figure 86). Both the host device and the 54x have access to the HPI control register.

Figure 86. Host Port Interface Block Diagram

HD(70)

Interface control signals

8 8 16 16 MUX 16 MUX Address register Data Address HPI memory block HPI control logic Host port interface

Data latch

HPI control register

DSP data

DSP address

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Host Port Interface

The HPI provides 16-bit data to the 54x while maintaining the economical 8-bit external interface by automatically combining successive bytes transferred into 16-bit words. When the host device performs a data transfer with the HPI registers, the HPI control logic automatically performs an access to a dedicated 2K-word block of internal 54x dual-access RAM to complete the transaction. The 54x can then access the data within its memory space. The HPI RAM can also be used as general-purpose dual-access data or program RAM. The HPI has two modes of operation, shared-access mode (SAM) and hostonly mode (HOM). In shared-access mode (the normal mode of operation), both the 54x and the host can access HPI memory. In this mode, asynchronous host accesses are resynchronized internally and, in the case of a conflict between a 54x and a host cycle (where both accesses are reads or writes), the host has access priority and the 54x waits one cycle. In host-only mode, only the host can access HPI memory while the 54x is in reset or in IDLE2 with all internal and external clocks stopped. The host can therefore access the HPI RAM while the 54x is in its minimum power consumption configuration. The HPI supports high speed, back-to-back host accesses. In shared-access mode, the HPI can transfer one byte every five CLKOUT cycles (that is, 64M bps) with the 54x running at a 40-MHz CLKOUT. The HPI is designed so the host can take advantage of this high bandwidth and run at frequencies up to (Fd*n)/5, where Fd is the 54x CLKOUT frequency and n is the number of host cycles for an external access. Therefore, with a 40-MHz 54x and common values of 4 (or 3) for n, the host can run at speeds of up to 32 (or 24) MHz without requiring wait states. In the host-only mode, the HPI supports even higher speed back-to-back host accesses on the order of one byte every 50 ns (that is, 160M bps), independent of the 54x clock rate (refer to the TMS320C54x data sheet for specific detailed timing information).

8.6.1

Basic Host Port Interface Functional Description

The external HPI interface consists of the 8-bit HPI data bus and control signals that configure and control the interface. The interface can connect to a variety of host devices with little or no additional logic necessary. Figure 87 shows a simplified diagram of a connection between the HPI and a host device.

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Host Port Interface

Figure 87. Generic System Block Diagram

8 Data HD0HD7 2 Address Read/Write HCNTL0/1 (address) HBIL (1st/2nd byte) HR/W HDS1 HDS2 HCS HAS Sampled by internal strobe or HAS Data strobe Internal strobe (controls transfer) Address Latch Enable (if used) (Samples Address and Read/Write signals, if used) HINT Ready HRDY Interrupt

Host device

54x

The 8-bit data bus (HD0HD7) exchanges information with the host. Because of the 16-bit word structure of the 54x, all transfers with a host must consist of two consecutive bytes. The dedicated HBIL pin indicates whether the first or second byte is being transferred. An internal control register bit determines whether the first or second byte is placed into the most significant byte of a 16-bit word. The host must not break the first byte/second byte (HBIL low/high) sequence of an ongoing HPI access. If this sequence is broken, data can be lost, and unpredictable operation can result.

The two control inputs (HCNTL0 and HCNTL1) indicate which internal HPI register is being accessed and the type of access to the register. These inputs, along with HBIL, are commonly driven by host address bus bits or a function of these bits. Using the HCNTL0/1 inputs, the host can specify an access to the HPI control (HPIC) register, the HPI address (HPIA) register (which serves as the pointer into HPI memory), or HPI data (HPID) register. The HPID register can also be accessed with an optional automatic address increment. The autoincrement feature provides a convenient way of reading or writing to subsequent word locations. In autoincrement mode, a data read causes a postincrement of the HPIA, and a data write causes a preincrement of the HPIA. By writing to the HPIC, the host can interrupt the 54x CPU, and the HINT output can be used by the 54x to interrupt the host. The host can also acknowledge and clear HINT by writing to the HPIC.
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Table 820 summarizes the three registers that the HPI utilizes for communication between the host device and the 54x CPU and their functions.

Table 820. HPI Registers Description

Name HPIA HPIC HPID Address 002Ch Description HPI address register. Directly accessible only by the host. Contains the address in the HPI memory at which the current access occurs. HPI control register. Directly accessible by either the host or by the 54x. Contains control and status bits for HPI operations. HPI data register. Directly accessible only by the host. Contains the data that was read from the HPI memory if the current access is a read, or the data that will be written to HPI memory if the current access is a write.

The two data strobes (HDS1 and HDS2), the read/write strobe (HR/W), and the address strobe (HAS) enable the HPI to interface to a variety of industrystandard host devices with little or no additional logic required. The HPI is easily interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe and a read/write strobe, or two separate strobes for read and write. This is described in detail later in this section. The HPI ready pin (HRDY) allows insertion of wait states for hosts that support a ready input to allow deferred completion of access cycles and have faster cycle times than the HPI can accept due to 54x operating clock rates. If HRDY, when used directly from the 54x, does not meet host timing requirements, the signal can be resynchronized using external logic if necessary. HRDY is useful when the 54x operating frequency is variable, or when the host is capable of accessing at a faster rate than the maximum shared-access mode access rate (up to the host-only mode maximum access rate). In both cases, the HRDY pin provides a convenient way to automatically (no software handshake needed) adjust the host access rate to a faster 54x clock rate or switch the HPI mode. All of these features combined allow the HPI to provide a flexible and efficient interface to a wide variety of industry-standard host devices. Also, the simplicity of the HPI interface greatly simplifies data transfers both from the host and the 54x sides of the interface. Once the interface is configured, data transfers are made with a minimum of overhead at a maximum speed.

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8.6.2

Details of Host Port Interface Operation

This section includes a detailed description of each HPI external interface pin function, as well as descriptions of the register and control bit functions. Logical interface timings and initialization and read/write sequences are discussed in section 8.6.3, Host Read/Write Access to HPI, on page 8-46. The external HPI interface signals implement a flexible interface to a variety of types of host devices. Devices with single or multiple data strobes and with or without address latch enable (ALE) signals can easily be connected to the HPI. Table 821 gives a detailed description of the function of each of the HPI external interface pins.

Table 821. HPI Signal Names and Functions

HPI Pin HAS Host Pin Address latch enable (ALE) or Address strobe or unused (tied high) State Signal Function I Address strobe input. Hosts with a multiplexed address and data bus connect HAS to their ALE pin or equivalent. HBIL, HCNTL0/1, and HR/W are then latched on HAS falling edge. When used, HAS must precede the later of HCS, HDS1, or HDS2 (see 54x data sheet for detailed HPI timing specifications). Hosts with separate address and data bus can connect HAS to a logic-1 level. In this case, HBIL, HCNTL0/1, and HR/W are latched by the later of HDS1, HDS2, or HCS falling edge while HAS stays inactive (high). Byte identification input. Identifies first or second byte of transfer (but not most significant or least significant this is specified by the BOB bit in the HPIC register, described later in this section). HBIL is low for the first byte and high for the second byte. Host control inputs. Selects a host access to the HPIA register, the HPI data latches (with optional address increment), or the HPIC register. Chip select. Serves as the enable input for the HPI and must be low during an access but may stay low between accesses. HCS normally precedes HDS1 and HDS2, but this signal also samples HCNTL0/1, HR/W, and HBIL if HAS is not used and HDS1 or HDS2 are already low (this is explained in further detail later in this section). Figure 88 on page 8-43 shows the equivalent circuit of the HCS, HDS1 and HDS2 inputs. Parallel bidirectional 3-state data bus. HD7 (MSB) through HD0 (LSB) are placed in the high-impedance state when not outputting (HDSx | HCS = 1) or when EMU1/OFF is active (low).

HBIL

Address or control lines

HCNTL0, HCNTL1 HCS

Address or control lines Address or control lines

HD0HD7

Data bus

I/O/Z

I = Input, O = Output, Z = High impedance

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Host Port Interface

Table 821. HPI Signal Names and Functions (Continued)

HPI Pin HDS1, HDS2 Host Pin Read strobe and write strobe or data strobe State I Signal Function Data strobe inputs. Control transfer of data during host access cycles. Also, when HAS is not used, used to sample HBIL, HCNTL0/1, and HR/W when HCS is already low (which is the case in normal operation). Hosts with separate read and write strobes connect those strobes to either HDS1 or HDS2. Hosts with a single data strobe connect it to either HDS1 or HDS2, connecting the unused pin high. Regardless of HDS connections, HR/W is still required to determine direction of transfer. Because HDS1 and HDS2 are internally exclusive-NORed, hosts with a high true data strobe can connect this to one of the HDS inputs with the other HDS input connected low. Figure 88 on page 8-43 shows the equivalent circuit of the HDS1, HDS2, and HCS inputs. Host interrupt output. Controlled by the HINT bit in the HPIC. Driven high when the 54x is being reset. Placed in the high impedance state when EMU1/OFF is active (low). HPI ready output. When high, indicates that the HPI is ready for a transfer to be performed. When low, indicates that the HPI is busy completing the internal portion of the previous transaction. Placed in high impedance when EMU1/OFF is active (low). HCS enables HRDY; that is, HRDY is always high when HCS is high. Read/write input. Hosts must drive HR/W high to read HPI and low to write HPI. Hosts without a read/write strobe can use an address line for this function.

HINT

Host interrupt input

O/Z

HRDY

Asynchronous ready

O/Z

HR/W

Read/Write strobe, address line, or multiplexed address/data

I = Input, O = Output, Z = High impedance

The HCS input serves primarily as the enable input for the HPI, and the HDS1 and HDS2 signals control the HPI data transfer; however, the logic with which these inputs are implemented allows their functions to be interchanged if desired. If HCS is used in place of HDS1 and HDS2 to control HPI access cycles, HRDY operation is affected (since HCS enables HRDY and HRDY is always high when HCS is high). The equivalent circuit for these inputs is shown in Figure 88. The figure shows that the internal strobe signal that samples the HCNTL0/1, HBIL, and HR/W inputs (when HAS is not used) is derived from all three of the input signals, as the logic illustrates. Therefore, the latest of HDS1, HDS2, or HCS is the one which actually controls sampling of the HCNTL0/1, HBIL, and HR/W inputs. Because HDS1 and HDS2 are exclusive-NORed, both these inputs being low does not constitute an enabled condition.
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Host Port Interface

Figure 88. Select Input Logic

HDS1 HDS2

Internal Strobe HCS

When using the HAS input to sample HCNTL0/1, HBIL, and HR/W, this allows these signals to be removed earlier in an access cycle, therefore allowing more time to switch bus states from address to data information, facilitating interface to multiplexed address and data type buses. In this type of system, an ALE signal is often provided and would normally be the signal connected to HAS. The two control pins (HCNTL0 and HCNTL1) indicate which internal HPI register is being accessed and the type of access to the register. The states of these two pins select access to the HPI address (HPIA), HPI data (HPID), or HPI control (HPIC) registers. The HPIA register serves as the pointer into HPI memory, the HPIC contains control and status bits for the transfers, and the HPID contains the actual data transferred. Additionally, the HPID register can be accessed with an optional automatic address increment. Table 822 describes the HCNTL0/1 bit functions.

Table 822. HPI Input Control Signals Function Selection Descriptions

HCNTL1 0 0 1 1 HCNTL0 0 1 0 1 Description Host can read or write the HPI control register, HPIC. Host can read or write the HPI data latches. HPIA is automatically postincremented each time a read is performed and preincremented each time a write is performed. Host can read or write the address register, HPIA. This register points to the HPI memory. Host can read or write the HPI data latches. HPIA is not affected.

On the 54x, HPI memory is a 2K 16-bit word block of dual-access RAM that resides at 1000h to 17FFh in data memory space and optionally, depending on the state of the OVLY bit, in program memory space. From the host interface, the 2K-word block of HPI memory can conveniently be accessed at addresses 0 through 7FFh; however, the memory can also be accessed by the host starting with any HPIA values with the 11 LSBs equal to 0. For example, the first word of the HPI memory block, addressed at 1000h by the 54x in data memory space, can be accessed by the host with any of the following HPIA values: 0000h, 0800h,1000h,1800h, ... F800h.
On-Chip Peripherals
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Host Port Interface

The HPI autoincrement feature provides a convenient way of accessing consecutive word locations in HPI memory. In the autoincrement mode, a data read causes a postincrement of the HPIA, and a data write causes a preincrement of the HPIA. Therefore, if a write is to be made to the first word of HPI memory with the increment option, due to the preincrement nature of the write operation, the HPIA should first be loaded with any of the following values: 07FFh, 0FFFh, 17FFh, ... FFFFh. The HPIA is a 16-bit register and all 16 bits can be written to or read from, although with a 2K-word HPI memory implementation, only the 11 LSBs of the HPIA are required to address the HPI memory. The HPIA increment and decrement affect all 16 bits of this register.

HPI Control Register Bits and Function

Four bits control HPI operation. These bits are BOB (which selects first or second byte as most significant), SMOD (which selects host or shared-access mode), and DSPINT and HINT (which can be used to generate 54x and host interrupts, respectively) and are located in the HPI control register (HPIC). A detailed description of the HPIC bit functions is presented in Table 823.

Table 823. HPI Control Register (HPIC) Bit Descriptions

Bit BOB Host Access Red/Write 54x Access Description If BOB = 1, first byte is least significant. If BOB = 0, first byte is most significant. BOB affects both data and address transfers. Only the host can modify this bit and it is not visible to the 54x. BOB must be initialized before the first data or address register access. If SMOD = 1, shared-access mode (SAM) is enabled: the HPI memory can be accessed by the 54x. If SMOD = 0, host-only mode (HOM) is enabled: the 54x is denied access to the entire HPI RAM block. SMOD = 0 during reset; SMOD = 1 after reset. SMOD can be modified only by the 54x but can be read by both the 54x and the host.

SMOD

Read

Read/Write

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Host Port Interface

Table 823. HPI Control Register (HPIC) Bit Descriptions (Continued)

Bit DSPINT Host Access Write 54x Access Description The host processor-to-54x interrupt. This bit can be written only by the host and is not readable by the host or the 54x. When the host writes a 1 to this bit, an interrupt is generated to the 54x. Writing a 0 to this bit has no effect. Always read as 0. When the host writes to HPIC, both bytes must write the same value. See this section for a detailed description of DSPINT function. This bit determines the state of the 54x HINT output, which can be used to generate an interrupt to the host. HINT = 0 upon reset, which causes the external HINT output to be inactive (high). The HINT bit can be set only by the 54x and can be cleared only by the host. The 54x writes a 1 to HINT, causing the HINT pin to go low. The HINT bit is read by the host or the 54x as a 0 when the external HINT pin is inactive (high) and as a 1 when the HINT pin is active (low). For the host to clear the interrupt, however, it must write a 1 to HINT. Writing a 0 to the HINT bit by either the host or the 54x has no effect. See this section for a detailed description of HINT function.

HINT

Read/Write

Read/Write

Because the host interface always performs transfers with 8-bit bytes and the control register is normally the first register accessed to set configuration bits and initialize the interface, the HPIC is organized on the host side as a 16-bit register with the same high and low byte contents (although access to certain bits is limited, as described previously) and with the upper bits unused on the 54x side. The control/status bits are located in the least significant four bits. The host accesses the HPIC register with the appropriate selection of HCNTL0/1, as described previously, and two consecutive byte accesses to the 8-bit HPI data bus. When the host writes to HPIC, both the first and second byte written must be the same value. The 54x accesses the HPIC at 002Ch in data memory space. The layout of the HPIC bits is shown in Figure 89 through Figure 812. In the figures for read operations, if 0 is specified, this value is always read; if X is specified, an unknown value is read. For write operations, if X is specified, any value can be written. On a host write, both bytes must be identical. Note that bits 47 and 1215 on the host side and bits 415 on the 54x side are reserved for future expansion.

1512 X 11 10 0 9 8 74 X 3 2 0 1 0 HINT SMOD BOB HINT SMOD BOB
Note: X = Unknown value is read.

Figure 89. HPIC Diagram Host Reads from HPIC

On-Chip Peripherals

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Host Port Interface

Figure 810. HPIC Diagram Host Writes to HPIC

1512 X 11 10 9 8 74 X 3 2 1 0 HINT DSPINT X BOB HINT DSPINT X BOB
Note: X = Any value can be written.

Figure 811.HPIC Diagram TMS320C54x Reads From HPIC

154 X

2 0

0 0

HINT

SMOD

Note:

X = Unknown value is read.

Figure 812. HPIC Diagram TMS320C54x Writes to HPIC

154 X

HINT

SMOD

Note:

X = Any value can be written.

Because the 54x can write to the SMOD and HINT bits, and these bits are read twice on the host interface side, the first and second byte reads by the host may yield different data if the 54x changes the state of one or both of these bits in between the two read operations. The characteristics of host and 54x HPIC read/write cycles are summarized in Table 824.

Table 824. HPIC Host/TMS320C54x Read/Write Characteristics

Device Host 54x Read 2 bytes 16 bits Write 2 bytes (Both bytes must be equal) 16 bits

8.6.3

Host Read/Write Access to HPI

The host begins HPI accesses by performing the external interface portion of the cycle; that is, initializing first the HPIC register, then the HPIA register, and then writing data to or reading data from the HPID register. Writing to HPIA or HPID initiates an internal cycle that transfers the desired data between the HPID and the dedicated internal HPI memory. Because this process requires several 54x cycles, each time an HPI access is made, data written to the HPID is not written to the HPI memory until after the host access cycle, and the data read from the HPID is the data from the previous cycle. Therefore, when reading, the data obtained is the data from the location specified in the previous

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Host Port Interface

access, and the current access serves as the initiation of the next cycle. A similar sequence occurs for a write operation: the data written to HPID is not written to HPI memory until after the external cycle is completed. If an HPID read operation immediately follows an HPID write operation, the same data (the data written) is read. The autoincrement feature available for HPIA results in sequential accesses to HPI memory by the host being extremely efficient. During random (nonsequential) transfers or sequential accesses with a significant amount of time between them, it is possible that the 54x may have changed the contents of the location being accessed between a host read and the previous host data read/write or HPIA write access, because of the prefetch nature of internal HPI operation. If this occurs, data different from the current memory contents may be read. Therefore, in cases where this is of concern in a system, two reads from the same address or an address write prior to the read access can be made to ensure that the most recent data is read. When the host performs an external access to the HPI, there are two distinctly different types of cycles that can occur: those for which wait states are generated (the HRDY signal is active) and those without wait states. In general, when in shared-access mode (SAM), the HRDY signal is used; when in hostonly mode (HOM), HRDY is not active and remains high; however, there are exceptions to this, which will be discussed. For accesses utilizing the HRDY signal, during the time when the internal portion of the transfer is being performed (either for a read or a write), HRDY is low, indicating that another transfer cannot yet be initiated. Once the internal cycle is completed and another external cycle can begin, HRDY is driven high by the HPI. This occurs after a fixed delay following a cycle initiation (refer to the 54x data sheet for detailed timing information for HPI external interface timings). Therefore, unless back-to-back cycles are being performed, HRDY is normally high when the first byte of a cycle is transferred. The external HPI cycle using HRDY is shown in the timing diagram in Figure 813.

On-Chip Peripherals

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Host Port Interface

Figure 813. HPI Timing Diagram

Byte 1 HCNTL0/1 HR/W HBIL Valid Valid Byte 2

HCS HAS (if used) HDS1, HDS2 HD read HD write HRDY

In a typical external access, as shown in Figure 813, the cycle begins with the host driving HCNTL0/1, HR/W, HBIL, and HCS, indicating specifically what type of transfer is to occur and whether the cycle is to be read or a write. Then the host asserts the HAS signal (if used) followed by one of the data strobe signals. If HRDY is not already high, it goes high when the previous internal cycle is complete, allowing data to be transferred, and the control signals are de-asserted. Following the external HPI cycle, HRDY goes low and stays low for a period of approximately five CLKOUT cycles (refer to the 54x data sheet for HPI timing information) while the 54x completes the internal HPI memory access, and then HRDY is driven high again. Note, however, HRDY is always high when HCS is high. As mentioned previously, SAM accesses generally utilize the HRDY signal. The exception to the HRDY-based interface timings when in SAM occurs when reading HPIC or HPIA or writing to HPIC (except when writing 1 to either DSPINT or HINT). In these cases, HRDY stays high; for all other SAM accesses, HRDY is active.

8-48

Valid Valid Valid Valid

Host Port Interface

Host access cycles, when in HOM, have timings different from the SAM timings described previously. In HOM, the CPU is not involved (with one exception), and the access can be completed after a short, fixed delay time. The exception to this occurs when writing 1s to the DSPINT or HINT bits in HPIC. In this case, the host access takes several CPU clock cycles, and SAM timings apply. Besides the HRDY timings and a faster cycle time, HOM access cycles are logically the same as SAM access cycles. A summary of the conditions under which the HRDY signal is active (where SAM timings apply) for host accesses is shown in Table 825. When HRDY is not active (HRDY stays high), HOM timings apply. Refer to the 54x data sheet for detailed HPI timing specifications.

Table 825. Wait-State Generation Conditions

Wait State Generated Register HPIC Reads No Writes 1 to DSPINT/HINT Yes All other cycles No HPIA No HOM No SAM Yes HPID HOM No SAM Yes HOM No SAM Yes

Access Sequences
A complete host access cycle always involves two bytes, the first with HBIL low, and the second with HBIL high. This 2-byte sequence must be followed regardless of the type of host access (HPIA, HPIC, or data access) and the host must not break the first byte/second byte (HBIL low/high) sequence of an ongoing HPI access. If this sequence is broken, data may be lost, and an unpredictable operation may result. Before accessing data, the host must first initialize HPIC, in particular the BOB bit, and then HPIA (in this order, because BOB affects the HPIA access). After initializing BOB, the host can then write to HPIA with the correct byte alignment. On an HPI memory read operation, after completion of the HPIA write, the HPI memory is read and the contents at the given address are transferred to the two 8-bit data latches, the first byte data latch and the second byte data latch. Table 826 illustrates the sequence involved in initializing BOB and HPIA for an HPI memory read. In this example, BOB is set to 0 and a read is requested of the first HPI memory location (in this case 1000h), which contains FFFEh.
On-Chip Peripherals
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Host Port Interface

Table 826. Initialization of BOB and HPIA

Event Host writes HPIC, 1st byte Host writes HPIC, 2nd byte Host writes HPIA, 1st byte Host writes HPIA, 2nd byte Internal HPI RAM read complete HD 00 00 10 00 HR/W 0 0 0 0 HCNTL1/0 00 00 10 10 HBIL 0 1 0 1 HPIC 00xx 0000 0000 HPIA xxxx xxxx 10xx 1000 1000 latch1 xxxx xxxx xxxx xxxx FF latch2 xxxx xxxx xxxx xxxx FE

In the cycle shown in Table 826, BOB and HPIA are initialized, and by loading HPIA, an internal HPI memory access is initiated. The last line of Table 826 shows the condition of the HPI after the internal RAM read is complete; that is, after some delay following the end of the host write of the second byte to HPIA, the read is completed and the data has been placed in the upper and lower byte data latches. For the host to actually retrieve this data, it must perform an additional read of HPID. During this HPID read access, the contents of the first byte data latch appears on the HD pins when HBIL is low and the content of the second byte data latch appears on the HD pins when HBIL is high. Then the address is incremented if autoincrement is selected and the memory is read again into the data latches. The sequence involved in this access is shown in Table 827.

Table 827. Read Access to HPI With Autoincrement

Event Host reads data, 1st byte Host reads data, 2nd byte Internal HPI RAM read complete HD FF FE HR/W 1 1 HCNTL1/0 01 01 HBIL 0 1 HPIC 0000 0000 HPIA 1000 1000 1001 latch1 FF FF 6A latch2 FE FE BC

In the access shown in Table 827, the data obtained from reading HPID is the data from the read initiated in the previous cycle (the one shown in Table 826) and the access performed as shown in Table 827 also initiates a further read, this time at location 1001h (because autoincrement was specified in this access by setting HCNTL1/0 to 01). Also, when autoincrement is selected, the increment occurs with each 16-bit word transferred (not with each byte); therefore, as shown in Table 827, the HPIA is incremented by only 1. The last line of Table 827 indicates that after the second internal RAM read is complete, the contents of location 1001h (6ABCh) has been read and placed into the upper and lower byte data latches.
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Host Port Interface

During a write access to the HPI, the first byte data latch is overwritten by the data coming from the host while the HBIL pin is low, and the second byte data latch is overwritten by the data coming from the host while the HBIL pin is high. At the end of this write access, the data in both data latches is transferred as a 16-bit word to the HPI memory at the address specified by the HPIA register. The address is incremented prior to the memory write because autoincrement is selected. An HPI write access is illustrated in Table 828. In this example, after the internal portion of the write is completed, location 1002h of HPI RAM contains 1234h. If a read of the same address follows this write, the same data just written in the data latches (1234h) is read back.

Table 828. Write Access to HPI With Autoincrement

Event Host writes data, 1st byte Host writes data, 2nd byte Internal HPI RAM write complete HD 12 34 HR/W 0 0 HCNTL1/0 01 01 HBIL 0 1 HPIC 0000 0000 HPIA 1002 1002 1002 latch1 12 12 12 latch2 FE 34 34

8.6.4

DSPINT and HINT Function Operation

The host and the 54x can interrupt each other using bits in the HPIC register. This section presents more information about this process.

Host Device Using DSPINT to Interrupt the 54x

A 54x interrupt is generated when the host writes a 1 to the DSPINT bit in HPIC. This interrupt can be used to wake up the 54x from IDLE. The host and the 54x always read this bit as 0. A 54x write has no effect. Once a 1 is written to DSPINT by the host, a 0 need not be written before another interrupt can be generated, and writing a 0 to this bit has no effect. The host should not write a 1 to the DSPINT bit while writing to BOB or HINT, or an unwanted 54x interrupt is generated. On the 54x, the host-to-54x interrupt vector address is xx64h. This interrupt is located in bit 9 of the IMR/IFR. Since the 54x interrupt vectors can be remapped into the HPI memory, the host can instruct the 54x to execute preprogrammed functions by simply writing the start address of a function to address xx65h in the HPI memory prior to interrupting the 54x with a branch instruction located at address xx64h. If the interrupts are remapped to the host port accessible on-chip RAM, you must use SAM and the host must not write to location xx00h to xx7Fh, except for xx65h.
On-Chip Peripherals
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Host Port Interface

Host Port Interface (54x) Using HINT to Interrupt the Host Device
When the 54x writes a 1 to the HINT bit in HPIC, the HINT output is driven low; the HINT bit is read as a 1 by the 54x or the host. The HINT signal can be used to interrupt the host device. The host device, after detecting the HINT interrupt line, can acknowledge and clear the 54x interrupt and the HINT bit by writing a 1 to the HINT bit. The HINT bit is cleared and then read as a 0 by the 54x or the host, and the HINT pin is driven high. If the 54x or the host writes a 0, the HINT bit remains unchanged. While accessing the SMOD bit, the 54x should not write a 1 to the HINT bit unless it also wants to interrupt the host.

8.6.5

Considerations in Changing HPI Memory Access Mode (SAM/HOM) and IDLE2/3 Use
The HPI host-only mode (HOM) allows the host to access HPI RAM while the 54x is in IDLE2/3 (that is, completely halted). Additionally, the external clock input to the 54x can be stopped for the lowest power consumption configuration. Under these conditions, random accesses can still be made without having to restart the external clock for each access and wait for its lockup time if the 54x on-chip PLL is used. The external clock need only be restarted before taking the 54x out of IDLE2/3. The host cannot access HPI RAM in SAM when the 54x is in IDLE2/3, because CPU clocks are required for access in this mode of operation. Therefore, if the host requires access to the HPI RAM while the 54x is in IDLE2/3, the 54x must change HPI mode to HOM before entering IDLE2/3. When the HPI is in HOM, the 54x can access HPIC to toggle the SMOD bit or send an interrupt to the host, but cannot access the HPI RAM block; a 54x access to the HPI RAM is disregarded in HOM. In order for the 54x to again access the HPI RAM block, HPI mode must be changed to SAM after exiting IDLE2/3. To select HOM, a 0 must be written to the SMOD bit in HPIC. To select SAM, a 1 must be written to SMOD. When changing between HOM and SAM, two considerations must be met for proper operation. First, the instruction immediately following the one that changes from SAM to HOM must not be an IDLE 2 or IDLE 3. This is because in this case, due to the 54x pipeline and delays in the SAM to HOM mode switch, the IDLE2/3 takes effect before the mode switch occurs, causing the HPI to remain in SAM; therefore, no host accesses can occur.

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Host Port Interface

The second consideration is that when changing from HOM to SAM, the instruction immediately following the one that changes from HOM to SAM cannot read the HPI RAM block. This requirement is due to the fact that the mode has not yet changed when the HPI RAM read occurs and the RAM read is ignored because the mode switch has not yet occurred. HPI RAM writes are not included in this restriction because these operations occur much later in the pipeline, so it is possible to write to HPI RAM in the instruction following the one which changes from HOM to SAM. On the host side, there are no specific considerations associated with the mode changes. For example, it is possible to have a third device wake up the 54x from IDLE2/3 and the 54x changing to SAM upon wake-up without a software handshake with the host. The host can continue accessing while the HPI mode changes. However, if the host accesses the HPI RAM while the mode is being changed, the actual mode change will be delayed until the host access is completed. In this case, a 54x access to the HPI memory is also delayed. Table 829 illustrates the sequence of events involved in entering and exiting an IDLE2/3 state on the 54x when using the HPI. Throughout the process, the HPI is accessible to the host.

Table 829. Sequence for Entering and Exiting IDLE2 and IDLE3
Host or Other Device 54x Switches mode to HOM Executes a NOP Executes IDLE 2 or IDLE 3 instruction May stop DSP clock In IDLE2/3 Mode HOM HOM HOM HOM 54x clock Running Running Running Stopped or running Turns on DSP clock if it was stopped Sends an interrupt to DSP In IDLE2/3 In IDLE2/3 54x wakes up from IDLE2/3 54x switches mode to SAM HOM HOM HOM SAM Running Running Running Running

Sufficient wake-up time must be ensured when the 54x on-chip PLL is used.

On-Chip Peripherals

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Host Port Interface

8.6.6

Access of HPI Memory During Reset

The 54x is not operational during reset, but the host can access the HPI, allowing program or data downloads to the HPI memory. When this capability is used, it is often convenient for the host to control the 54x reset input. The sequence of events for resetting the 54x and downloading a program to HPI memory while the 54x is in reset is summarized in Table 830 and corresponds to the reset of the 54x. Initially, the host stops accessing the HPI at least six 54x periods before driving the 54x reset line low. The host then drives the 54x reset line low and can start accessing the HPI after a minimum of four 54x periods. The HPI mode is automatically set to HOM during reset, allowing high-speed program download. The 54x clock can even be stopped at this time; however, the clock must be running when the reset line falls and rises for proper reset operation of the 54x. Once the host has finished downloading into HPI memory, the host stops accessing the HPI and drives the 54x reset line high. At least 20 54x periods after the reset line rising edge, the host can again begin accessing the HPI. This number of periods corresponds to the internal reset delay of the 54x. The HPI mode is automatically set to SAM upon exiting reset. If the host writes a 1 to DSPINT while the 54x is in reset, the interrupt is lost when the 54x comes out of reset. The 54x warm boot can use the HPI memory and start execution from the lowest HPI address.

Table 830. HPI Operation During RESET

Host Waits 6 54x clock periods Brings RESET low and waits 4 clocks Can stop 54x clock Writes program and/or data in HPI memory Turns on DSP clock if it was stopped Brings RESET high Waits 20 54x clock periods Can access HPI 54x Running Goes into reset In reset In reset In reset In reset Comes out of reset Running Mode X HOM HOM HOM HOM HOM SAM SAM 54x CLK Running Running Stopped or running Stopped or running Running Running Running Running

Sufficient wake-up time must be ensured when the 54x on-chip PLL is used.

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Chapter 9

Serial Ports
This chapter discusses the four serial port interfaces connected to the 54x core CPU:

Standard synchronous serial port interface Buffered serial port interface Multichannel buffered serial Port (McBSP) interface Time-division multiplexed serial port interface

These peripherals are controlled through registers that reside in the memory map. The serial ports are synchronized to the core CPU by way of interrupts.

Topic
9.1 9.2 9.3 9.4

Page
Introduction to the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Buffered Serial Port (BSP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 Time-Division Multiplexed (TDM) Serial Port Interface . . . . . . . . . . . 9-56

Serial Ports

9-1

Introduction to the Serial Ports

9.1 Introduction to the Serial Ports

54x devices implement a variety of types of flexible serial port interfaces. These serial port interfaces provide full duplex, bidirectional, communication with serial devices such as codecs, serial analog to digital (A/D) converters, and other serial systems. The serial port interface signals are directly compatible with many industry-standard codecs and other serial devices. The serial port may also be used for interprocessor communication in multiprocessing applications (the time-division multiplexed (TDM) serial port is especially optimized for multiprocessing). Table 91 lists the serial ports available on various 54x devices.

Table 91. Serial Ports on the TMS320C54x Devices

Standard Synchronous Serial Ports 2 0 0 1 1 0 0 0 0 0 Buffered Serial Ports 0 1 1 1 1 2 2 0 0 0 MultiChannel Buffered Serial Ports 0 0 0 0 0 0 0 2 3 6 Time-Division Multiplexed Serial Ports 0 1 1 0 0 1 1 0 0 0

Device 541 542 543 545 546 548 549 5402 5410 5420

Table 92 lists the sections that should be consulted for the various serial ports and their modes.

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Introduction to the Serial Ports

Table 92. Sections that Discuss the Serial Ports

Serial Port Standard Buffered Mode Autobuffering Nonbuffered (standard) MCBSP TDM Multichannel TDM Non-TDM (standard) See . . . section 9.2, Standard Serial Port Interface, on page 9-4. section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33. section 9.2, Standard Serial Port Interface, on page 9-4. TMS320C54x Enhanced Peripherals, Volume 5 (literature number SPRU302). section 9.4, Time-Division Multiplexed (TDM) Serial Port Interface, on page 9-56. section 9.2, Standard Serial Port Interface, on page 9-4.

Serial Ports

9-3

Serial Port Interface

9.2 Serial Port Interface

Four different types of serial port interfaces are available on 54x devices. The basic standard serial port interface is implemented on 541, 545, and 546 devices. The TDM serial port interface is implemented on the 542, 543, 548, and 549 devices. The 542, 543, 545, 546, 548, and 549 devices include a buffered serial port (BSP) that implements an automatic buffering feature, which greatly reduces CPU overhead required in handling serial data transfers. The 5402, 5410, and 5420 devices include multichannel buffered serial ports (McBSPs). See Table 91 for information about the features included in various 54x devices. The BSP operates in either autobuffering or nonbuffered mode. When operated in nonbuffered (or standard) mode, the BSP functions the same as the basic standard serial port (except where specifically indicated) and is described in this section. The TDM serial port operates in either TDM or nonTDM mode. When operated in non-TDM (or standard) mode, the TDM serial port also functions the same as the basic standard serial port and is described in this section. The BSP also implements several enhanced features in standard mode. These features, together with operation of the BSP in autobuffering mode, are described in section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33. Therefore, when using the 542, 543, 545, 546, 548, and 549 devices, you should consult section 9.3. Operation of the TDM serial port in TDM mode is described in section 9.4, Time-Division Multiplexed (TDM) Serial Port Interface, on page 9-56. Note that the BSP and TDM serial ports initialize to a standard serial port compatible mode upon reset. In all 54x serial ports, both receive and transmit operations are doublebuffered, thus allowing a continuous communications stream with either 8- or 16-bit data packets. The continuous mode provides operation that, once initiated, requires no further frame synchronization pulses (FSR and FSX) when transmitting at maximum packet frequency. The serial ports are fully static and thus will function at arbitrarily low clocking frequencies. The maximum operating frequency for the standard serial port of one-fourth of CLKOUT (10 Mbit/s at 25 ns, 12.5 Mbit/s at 20 ns) is achieved when using internal serial port clocks. The maximum operating frequency for the BSP is CLKOUT. When the serial ports are in reset, the device may be configured to turn off the internal serial port clocks, allowing the device to run in a lower power mode of operation.
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9.2.1

Serial Port Interface Registers

The serial port operates through the three memory-mapped registers (SPC, DXR, and DRR) and two other registers (RSR and XSR) that are not directly accessible to the program, but are used in the implementation of the doublebuffering capability. These five registers are listed in Table 93.

Table 93. Serial Port Registers

Address Register DRR DXR SPC RSR XSR Description Data receive register Data transmit register Serial port control register Receive shift register Data transmit shift register

See section 8.2, Peripheral Memory-Mapped Registers.

Data receive register (DRR). The 16-bit memory-mapped data receive register (DRR) holds the incoming serial data from the RSR to be written to the data bus. At reset, the DRR is cleared. Data transmit register (DXR). The 16-bit memory-mapped data transmit register (DXR) holds the outgoing serial data from the data bus to be loaded in the XSR. At reset, the DXR is cleared. Serial port control register (SPC). The 16-bit memory-mapped serial port control register (SPC) contains the mode control and status bits of the serial port. Data receive shift register (RSR). The 16-bit data receive shift register (RSR) holds the incoming serial data from the serial data receive (DR) pin and controls the transfer of the data to the DRR. Data transmit shift register (XSR). The 16-bit data transmit shift register (XSR) controls the transfer of the outgoing data from the DXR and holds the data to be transmitted on the serial data transmit (DX) pin.

During normal serial port operation, the DXR is typically loaded with data to be transmitted on the serial port by the executing program, and its contents read automatically by the serial port logic to be sent out when a transmission is initiated. The DRR is loaded automatically by the serial port logic with data received on the serial port and read by the executing program to retrieve the received data.
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At times during normal serial port operation, however, it may be desirable for a program to perform other operations with the memory-mapped serial port registers besides simply writing to DXR and reading from DRR. On the SP, the DXR and DRR may be read or written at any time regardless of whether the serial port is in reset or not. On the BSP, access to these registers is restricted; the DRR can only be read, and the DXR can only be written when autobuffering is disabled (see section 9.3.2, Autobuffering Unit (ABU) Operation, on page 9-40). The DRR can only be written when the BSP is in reset. The DXR can be read at any time. Note, however, that on both the SP and the BSP, care should be exercised when reading or writing to these registers during normal operation. With the DRR, since, as mentioned previously, this register is written automatically by the serial port logic when data is received, if a write to DRR is performed, subsequent reads may not yield the result written if a serial port receive occurs after the write but before the read is performed. With the DXR, care should be exercised when this register is written, since if previously written contents intended for transmission have not yet been sent, these contents will be overwritten and the original data lost. As mentioned previously, the DXR can be read at any time. Alternatively, DXR and DRR may also serve as general purpose storage if they are not required for serial port use. If these registers are to be used for general purpose storage, the transmit and/or receive sections of the serial port should be disabled either by tying off (by pulling up or down, whichever is appropriate) external input pins which could spuriously cause serial port transfers, or by putting the port in reset.

9.2.2

Serial Port Interface Operation

This section describes operation of the basic standard serial port interface, which includes operation of the TDM and BSP serial ports when configured in standard mode. Table 94 lists the pins used in serial port operation. Figure 91 shows these pins for two 54x serial ports connected for a one-way transfer from device 0 to device 1. Only three signals are required to connect from a serial port transmitter to a receiver for data transmission. The transmitted serial data signal (DX) sends the actual data. The transmit frame synchronization signal (FSX) initiates the transfer (at the beginning of the packet), and the transmit clock signal (CLKX) clocks the bit transfer. The corresponding pins on the receive device are DR, FSR and CLKR, respectively.

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Table 94. Serial Port Pins

Pin CLKR CLKX DR DX FSR FSX Description Receive clock signal Transmit clock signal Received serial data signal Transmitted serial data signal Receive framing synchronization signal Transmit frame synchronization signal

Figure 91. One-Way Serial Port Transfer

54x device 0 DX FSX CLKX 54x device 1 DR FSR CLKR

Figure 92 shows how the pins and registers are configured in the serial port logic and how the double-buffering is implemented. Transmit data is written to the DXR, while received data is read from the DRR. A transmit is initiated by writing data to the DXR, which copies the data to the XSR when the XSR is empty (when the last word has been transmitted serially, that is, driven on the DX pin). The XSR manages shifting the data to the DX pin, thus allowing another write to DXR as soon as the DXR-to-XSR copy is completed. During transmits, upon completion of the DXR-to-XSR copy, a 0-to-1 transition occurs on the transmit ready (XRDY) bit in the SPC. This 0-to-1 transition generates a serial port transmit interrupt (XINT) that signals that the DXR is ready to be reloaded. See section 6.10, Interrupts, on page 6-26 for more information on 54x interrupts. The process is similar in the receiver. Data from the DR pin is shifted into the RSR, which is then copied into the DRR from which it may be read. Upon completion of the RSR-to-DRR copy, a 0-to-1 transition occurs on the receive ready (RRDY) bit in the SPC. This 0-to-1 transition generates a serial port receive interrupt (RINT). Thus, the serial port is double-buffered because data
Serial Ports
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can be transferred to or from DXR or DRR while another transmit or receive is being performed. Note that transfer timing is synchronized by the frame sync pulse in burst mode (discussed in more detail in section 9.2.4, Burst Mode Transmit and Receive Operations, on page 9-18).

Figure 92. Serial Port Interface Block Diagram

Data Bus 16 (Load) Load control logic 16 DXR (16) 16 Load Control Logic RSR (16) (Clear) Byte/word counter (Clock) (Clear) (Clock) Byte/word counter (Load) XINT on DXR-XSR transfer

DRR (16) 16 RINT on RSR-DRR transfer

XSR (16)

FSR DR

FSX DX

CLKR CLKX

9.2.3

Configuring the Serial Port Interface

The SPC contains control bits which configure the operation of the serial port. The SPC bit fields are shown in Figure 93 and described in Table 95. Note that seven bits in the SPC are read only and the remaining nine bits are read/write.

Figure 93. Serial Port Control Register (SPC) Diagram

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Free
R/W

Soft RSRFULL XSREMPTY XRDY RRDY

R/W R R R R

IN1
R

IN0 RRST XRST TXM MCM FSM

R R/W R/W R/W R/W R/W

FO

DLB
R/W

Res
R

R/W

Note:

R = Read, W = Write

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Table 95. Serial Port Control Register (SPC) Bit Summary

Bit Name 15 Free Reset Value 0 Function This bit is used in conjunction with the Soft bit to determine the state of the serial port clock when a breakpoint is encountered in the HLL debugger. See Table 96 on page 9-17 for the serial port clock configurations. Free = 0 Free = 1 14 Soft 0 The Soft bit selects the emulation mode. The serial port clock runs free regardless of the Soft bit.

This bit is used in conjunction with the Free bit to determine the state of the serial port clock when a breakpoint is encountered in the HLL debugger. When the Free bit is cleared to 0, the Soft bit selects the emulation mode. See Table 96 on page 9-17 for the serial port clock configurations. Soft = 0 The serial port clock stops immediately, thus aborting any transmission. The clock stops after completion of the current transmission.

Soft = 1 13 RSRFULL 0

Receive Shift Register Full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when RSR is full and DRR has not been read since the last RSR-to-DRR transfer. On the SP, when FSM = 1, the occurrence of a frame sync pulse on FSR qualifies the generation of RSRFULL = 1. When FSM = 0, and on the BSP, only the basic two conditions apply; that is, RSRFULL goes high without waiting for an FSR pulse. RSRFULL = 0 Any one of the following three events clears the RSRFULL bit to 0: reading DRR, resetting the receiver (RRST bit to 0), or resetting the device. The port has recognized an overrun. When RSRFULL = 1, the receiver halts and waits for DRR to be read, and any data sent on DR is lost. On the SP, the data in RSR is preserved; on the BSP, the contents of RSR are lost.

RSRFULL = 1

12

XSREMPTY

Transmit Shift Register Empty. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when XSR is empty and DXR has not been loaded since the last DXR-to-XSR transfer. XSREMPTY = 0 Any one of the following three events clears the XSREMPTY bit to 0: underflow has occurred, resetting the transmitter (XRST bit to 0), or resetting the device. On the SP, XSREMPTY is deactivated (set to 1) directly as a result of writing to DXR; on the BSP, XSREMPTY is only deactivated after DXR is loaded followed by the occurrence of an FSX pulse.

XSREMPTY = 1

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Table 95. Serial Port Control Register (SPC) Bit Summary (Continued)
Bit Name 11 XRDY Reset Value 1 Function Transmit Ready. A transition from 0 to 1 of the XRDY bit indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word. A transmit interrupt (XINT) is generated upon the transition. This bit can be polled in software instead of using serial port interrupts. Note that on the SP, XRDY is generated directly as a result of writing to DXR; while on the BSP, XRDY is only generated after DXR is loaded followed by the occurrence of an FSX pulse. At reset or serial port transmitter reset (XRST = 0), the XRDY bit is set to 1. Receive Ready. A transition from 0 to 1 of the RRDY bit indicates that the RSR contents have been copied to the DRR and that the data can be read. A receive interrupt (RINT) is generated upon the transition. This bit can be polled in software instead of using serial port interrupts. At reset or serial port receiver reset (RRST = 0), the RRDY bit is cleared to 0. Input 1. This bit allows the CLKX pin to be used as a bit input. IN1 reflects the current level of the CLKX pin of the device. When CLKX switches levels, there is a latency of between 0.5 and 1.5 CLKOUT cycles before the new CLKX value is represented in the SPC. Input 0. This bit allows the CLKR pin to be used as a bit input. IN0 reflects the current level of the CLKR pin of the device. When CLKR switches levels, there is a latency of between 0.5 and 1.5 CLKOUT cycles before the new CLKR value is represented in the SPC. Receive Reset. This signal resets and enables the receiver. When a 0 is written to the RRST bit, activity in the receiver halts. RRST = 0 RRST = 1 6 XRST 0 The serial port receiver is reset. Writing a 0 to RRST clears the RSRFULL and RRDY bits to 0. The serial port receiver is enabled.

10

RRDY

IN1

IN0

RRST

Transmitter Reset. This signal is used to reset and enable the transmitter. When a 0 is written to the XRST bit, activity in the transmitter halts. When the XRDY bit is 0, writing a 0 to XRST generates a transmit interrupt (XINT). XRST = 0 XRST = 1 The serial port transmitter is reset. Writing a 0 to XRST clears the XSREMPTY bit to 0 and sets the XRDY bit to 1. The serial port transmitter is enabled.

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Table 95. Serial Port Control Register (SPC) Bit Summary (Continued)
Bit Name 5 TXM Reset Value 0 Function Transmit Mode. This bit configures the FSX pin as an input (TXM = 0) or as an output (TXM = 1). TXM = 0 TXM = 1

External frame sync. The transmitter idles until a frame sync pulse is supplied on the FSX pin. Internal frame sync. Frame sync pulses are generated internally when data is transferred from the DXR to XSR to initiate data transfers. The internally generated framing signal is synchronous with respect to CLKX.

MCM

Clock Mode. This bit specifies the clock source for CLKX. MCM = 0 MCM = 1 CLKX is taken from the CLKX pin. CLKX is driven by an on-chip clock source. For the SP and the BSP in standard mode, this on-chip clock source is at a frequency of one-fourth of CLKOUT. The BSP also allows the option of generating clock frequencies at additional ratios of CLKOUT. For a detailed description of this feature, see section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33. Note that if MCM = 1 and DLB = 1, a CLKR signal is also supplied by the internal source.

FSM

Frame Sync Mode. This bit specifies whether frame synchronization pulses (FSX and FSR) are required after the initial frame sync pulse for serial port operation. See section 9.2.2, Serial Port Interface Operation, on page 9-6 for more details on the frame sync signals. FSM = 0

Continuous mode. Frame sync pulses are not required after the initial frame sync pulse, but they are not ignored; therefore, improperly timed frame syncs may cause errors in serial transfers. See section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26 for information about serial port operation under various exception conditions. Burst mode. A frame sync pulse is required on FSX/FSR for the transmission/reception of each word.

FSM = 1 2 FO 0

Format. This bit specifies the word length of the serial port transmitter and receiver. FO = 0 FO = 1 The data is transmitted and/or received as 16-bit words. The data is transferred as 8-bit bytes. The data is transferred with the MSB first. The BSP also allows the capability of 10and 12-bit transfers. For a detailed description of this feature, see section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33.

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Table 95. Serial Port Control Register (SPC) Bit Summary (Continued)
Bit Name 1 DLB Reset Value 0 Function Digital Loopback Mode. This bit can be used to put the serial port in digital loopback mode. DLB = 0 DLB = 1 The digital loopback mode is disabled. The DR, FSR, and CLKR signals are taken from their respective device pins. The digital loopback mode is enabled. The DR and FSR signals are connected to DX and FSX, respectively, through multiplexers, as shown in Figure 94(a) and (b) on page 9-13. Additionally, CLKR is driven by CLKX if MCM = 1. If DLB = 1 and MCM = 0, CLKR is taken from the CLKR pin of the device. This configuration allows CLKX and CLKR to be tied together externally and supplied by a common external clock source. The logic diagram for CLKR is shown in Figure 94(c) on page 9-13. Note also that in DLB mode, the FSX and DX signals appear on the device pins, but FSR and DR do not. Either internal or external FSX signals may be used in DLB mode, as defined by the TXM bit.

Res

Reserved. Always read as a 0 in the serial port. This bit performs a function in the TDM serial port discussed in section 9.4, Time-Division-Multiplexed (TDM) Serial Port Interface, on page 9-56.

Reserved Bit
Bit 0 is reserved and is read as 0, although it performs a function in the TDM serial port (discussed in section 9.4, Time-Division-Multiplexed (TDM) Serial Port Interface, on page 9-56).

DLB Bit
The DLB (bit 1) selects digital loopback mode, which allows testing of serial port code with a single 54x device. When DLB = 1, DR and FSR are connected to DX and FSX, respectively, through multiplexers, as shown in Figure 94. When in loopback mode, CLKR is driven by CLKX if on-chip serial port clock generation is selected (MCM = 1), but if MCM = 0, then CLKR is driven by the external CLKR signal. This allows for the capability of external serial port clock generation in digital loopback mode. If DLB = 0, then normal operation occurs where DR, FSR, and CLKR are all taken from their respective pins.
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Figure 94. Receiver Signal Multiplexers

(a) DR 0 MUX FSR 0 MUX (b)

DR (internal) (c)

FSR (internal)

DX

1 CLKR DLB MUX 0

FSX

1 DLB

CLKR (internal)

CLKX

1 DLB MCM

FO Bit
The FO (bit 2) specifies whether data is transmitted as 16-bit words (FO = 0) or 8-bit bytes (FO = 1). Note that in the latter case, only the lower byte of whatever is written to DXR is transmitted, and the lower byte of data read from DRR is what was received. To transmit a whole 16-bit word in 8-bit mode, two writes to DXR are necessary, with the appropriate shifts of the value because the upper eight bits written to DXR are ignored. Similarly, to receive a whole 16-bit word in 8-bit mode, two reads from DRR are required, with the appropriate shifts of the value. In the SP, the upper eight bits of DRR are indeterminate in 8-bit receptions; in the BSP, the unused bits of DRR are sign-extended. Additionally, in the BSP, transfers of 10- and 12-bit words are provided for additional flexibility. For a detailed description of this feature, refer to section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33.

FSM Bit
The FSM (bit 3) specifies whether or not frame sync pulses are required in consecutive serial port transmits. If FSM = 1, a frame sync must be present for every transfer, although FSX may be either externally or internally generated depending on TXM. This mode is referred to as burst mode, because there are normally periods of inactivity on the serial port between transmits. The frequency with which serial port transmissions occur is called packet frequency, and data packets can be 8, 10, 12, or 16 bits long. Therefore, as packSerial Ports
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et frequency increases, it reaches a maximum that occurs when the time, in serial port clock cycles, from one packet to the next, is equal to the number of bits being transferred. If transmission occurs at the maximum rate for multiple transfers in a row, however, frame sync essentially becomes redundant. Note that frame sync actually becomes redundant in burst mode only at maximum packet frequency with FSX configured as an output (TXM = 1). When FSX is an input (TXM = 0), its presence is required for transmissions to occur. FSM = 0 selects the continuous mode of operation which requires only an initial frame sync pulse as long as a write to DXR (for transmit), or a read from DRR (for receive), is executed during each transfer. Note that when FSM = 0, frame sync pulses are not required, but they are not ignored, therefore, improperly timed frame syncs may cause errors in serial transfers. The timing of burst and continuous modes is discussed in detail in sections 9.2.4, 9.2.5, and 9.2.6.

MCM Bit
The serial port clock source is set by MCM (bit 4). If MCM = 0, CLKX is configured as an input and thus accepts an external clock. If MCM = 1, then CLKX is configured as an output, and is driven by an internal clock source. For the SP, and the BSP operating in standard mode, this on-chip clock is at a frequency of one-fourth of CLKOUT. The BSP also allows the option of generating clock frequencies at additional ratios of CLKOUT. For a detailed description of this feature, refer to section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33. Note that the CLKR pin is always configured as an input.

TXM Bit
The transmit frame synchronization pulse source is set by TXM (bit 5). Like MCM, if TXM = 1, FSX is configured as an output and generates a pulse at the beginning of every transmit. If TXM = 0, FSX is configured as an input, and accepts an external frame sync signal. Note that the FSR pin is always configured as an input.

XRST and RRST Bits

The serial port transmitter and receiver are reset with XRST (bit 6) and RRST (bit 7). These signals are active low, so that if XRST = RRST = 0, the serial port is in a reset state. To reset and reconfigure the serial port, a total of two writes to the SPC are required.

The first write to the SPC should: write a 0 to the XRST and RRST bits write the desired configuration to the remainder of the bits.

J J

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Serial Port Interface

The second write to the SPC should: write 1 to the XRST and RRST bits resend the desired configuration to the remainder of the bits.

J J

The second write takes the serial port out of reset. Note that the transmitter and receiver may be reset individually if desired. When a 0 is written to XRST or RRST, activity in the corresponding section of the serial port stops. This minimizes the switching and allows the device to operate with lower power consumption. When XRST = RRST = MCM = 0, power requirements are further reduced since CLKX is no longer driven as an output. In IDLE2 and IDLE3 mode, SP operation halts as with other parts of the 54x device. On the BSP, however, if the external serial port clock is being used, operation continues after an IDLE2/3 is executed. This allows power savings to still be realized in IDLE2/3, while still maintaining operation of critical serial port functions if necessary (see section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33 for further information about BSP operation). It should also be noted that, on the SP, the serial port may be taken out of reset at any time. Depending on the timing of exiting reset, however, a frame sync pulse may be missed. On the BSP, for receive and transmit with external frame sync, a setup of at least one CLKOUT cycle plus 1/2 serial port clock cycle is required prior to FSX being sampled active in standard mode. In autobuffering mode, additional setup is required (see section 9.3, Buffered Serial Port (BSP) Interface, on page 9-33 for further information about BSP initialization timing requirements).

IN0 and IN1 Bits

IN0 (bit 8) and IN1 (bit 9) allow the CLKR and CLKX pins to be used as bit inputs. IN0 and IN1 reflect the current states of the CLKR and CLKX pins. The data on these pins can be sampled by reading the SPC. This can be accomplished using the BIT, BITF, BITT, or CMPM instruction. Note that there is a latency of between 0.5 and 1.5 CLKOUT cycles in duration from CLKR/ CLKX switching to the new CLKR/CLKX value being available in the SPC. Note that even if the serial port is reset, IN0 and IN1 can still be used as bit inputs, and DRR and DXR as general-purpose registers.

RRDY and XRDY Bits

Bits 1013 in the SPC are read-only status bits that indicate various states of serial port operation. Writes and reads of the serial port may be synchronized by polling RRDY (bit 10) and XRDY (bit 11), or by using the interrupts that they generate. A transition from 0 to 1 of the RRDY bit indicates that the RSR conSerial Ports
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tents have been copied to the DRR and that the received data may be read. A receive interrupt (RINT) is generated upon this transition. A transition from 0 to 1 of the XRDY bit indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word. A transmit interrupt (XINT) is generated upon this transition. Polling XRDY and RRDY in software may either substitute for or complement the use of serial port interrupts (both polling and interrupts may be used together if so desired). Note that with external FSX, on the SP, XSR is loaded directly as a result of loading DXR, while on the BSP, XSR is not loaded until an FSX occurs.

XSREMPTY Bit
The XSREMPTY (bit 12) indicates whether the transmitter has experienced underflow. XSREMPTY is an active low bit; therefore, when XSREMPTY = 0, an underflow has occurred. Any one of the following three conditions causes XSREMPTY to become active (XSREMPTY = 0):

DXR has not been loaded since the last DXR-to-XSR transfer, and XSR empties (the actual transition of XSREMPTY occurs after the last bit has been shifted out of XSR), or the transmitter is reset (XRST = 0), or the 54x device is reset (RS = 0).

When XSREMPTY = 0, the transmitter halts and stops driving DX (the DX pin is in a high-impedance state) until the next frame sync pulse. Note that underflow does not constitute an error condition in the burst mode, although it does in the continuous mode (error conditions are further discussed in section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26). The following condition causes XSREMPTY to become inactive (XSREMPTY = 1):

A write to DXR occurs on the SP, or on the BSP a write to DXR occurs followed by an FSX pulse (see section 9.2.4, Burst Mode Transmit and Receive Operations, on page 9-18 for further information about transmit timing).

RSRFULL Bit
The RSRFULL (bit 13) indicates whether the receiver has experienced overrun. RSRFULL is an active high bit; therefore, when RSRFULL = 1, RSR is full. In burst mode (FSM = 1), all three of the following must occur to cause RSRFULL to become active (RSRFULL = 1):
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The DRR has not been read since the last RSR-to-DRR transfer, RSR is full, and a frame sync pulse appears on FSR.

In continuous mode (FSM = 0), and on the BSP, only the first two conditions are necessary to set RSRFULL: The DRR has not been read since the last RSR-to-DRR transfer and RSR is full.

Therefore, in continuous mode, and on the BSP, RSRFULL occurs after the last bit has been received. When RSRFULL = 1, the receiver halts and waits for the DRR to be read, and any data sent on DR is lost. On the SP, the data in RSR is preserved; on the BSP, the RSR contents are lost. Any one of the following three conditions causes RSRFULL to become inactive (RSRFULL = 0): The DRR is read, or the serial port is reset (RRST = 0), or the 54x device is reset (RS = 0).

SOFT and FREE Bits

Soft (bit 14) and Free (bit 15) are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high-level language (HLL) debugger. If the Free bit is set to 1, then upon a software breakpoint, the clock continues to run (free runs) and data is still shifted out. When Free = 1, the Soft bit is a dont care. If the Free bit is cleared to 0, then the Soft bit takes effect. If the Soft bit is cleared to 0, then the clock stops immediately, thus aborting any transmission. If the Soft bit is set to 1 and a transmission is in progress, the transmission continues until completion of the transfer, and then the clock halts. These options are listed in Table 96. The receive side functions in a similar fashion. Note that if an option other than immediate stop (Soft = Free = 0) is chosen, the receiver continues running and an overflow error is possible. The default value for these bits is immediate stop.

Table 96. Serial Port Clock Configuration

Free 0 0 1
Note:

Soft 0 1 X

Serial Port Clock Configuration Immediate stop, clocks are stopped. (Reset values) Transmitter stops after completion of the current word. The receiver is not affected. Free run.

X = Dont care

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9.2.4

Burst Mode Transmit and Receive Operations

In burst mode operation, there are periods of serial port inactivity between packet transmits. The data packet is marked by the frame sync pulse occurring on FSX (see Figure 95). On the transmit device, the transfer is initiated by a write to DXR. The value in DXR is then transferred to XSR, and, upon a frame sync pulse on FSX (generated internally or externally depending on TXM), the value in XSR is shifted out and driven on the DX pin. Note that on the SP, the DXR to XSR transfer occurs on the second rising edge of CLKX after DXR is loaded, while on the BSP this transfer does not occur until an FSX occurs, when FSX is external. When FSX is internal on the BSP, the DXR to XSR transfer and generation of FSX occur directly after loading DXR. On both the SP and the BSP, once XSR is loaded with the value from DXR, XRDY goes high, generating a transmit interrupt (XINT) and setting XSREMPTY to a 1.

Figure 95. Burst Mode Serial Port Transmit Operation

CLKX FSX (TXM = 1) DX (FO = 1) XRDY (SP) XINT (SP) XSREMPTY (SP) XRDY (BSP) XINT (BSP) XSREMPTY (BSP) A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1

DXR loaded XSR loaded (SP)

XSR loaded (BSP)

DXR reloaded

XSR reloaded (SP)

XSR reloaded (BSP)

Note that in both the SP and the BSP, DXR to XSR transfers occur only if the XSR is empty and the DXR has been loaded since the last DXR to XSR transfer. If DXR is reloaded before the old DXR contents have been transferred to XSR, the previous DXR contents are overwritten. Accordingly, unless overwriting DXR is intended, the DXR should only be loaded if XRDY = 1. This is assured if DXR writes are made only in response to a transmit interrupt or polling XRDY.
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Serial Port Interface

It should be noted that in the following discussions, the timings are slightly different for internally (TXM = 1, FSX is an output) and externally (TXM = 0, FSX is an input) generated frame syncs. This distinction is made because in the former case, the frame sync pulse is generated by the transmitting device as a direct result of a write to DXR. In the latter case, there is no such direct effect. Instead, the transmitting device must write to DXR and wait for an externally generated frame sync. If internal frame sync pulse generation is selected (TXM = 1), a frame sync pulse is generated on the second rising edge of CLKX following a write to DXR. For externally generated frame syncs, the events described here will occur as soon as a properly timed frame sync pulse occurs (see the data sheet for detailed serial port interface timings). On the next rising edge of CLKX after FSX goes high, the first data bit (MSB first) is driven on the DX pin. Thus, if the frame sync pulse is generated internally (TXM = 1), there is a 2-CLKX cycle latency (approximately) after DXR is loaded, before the data is driven on the line. If frame sync is externally generated, data transmission is delayed indefinitely after a DXR load until the FSX pulse occurs (this is described in further detail later in this section). With the falling edge of frame sync, the rest of the bits are shifted out. When all the bits are transferred, DX enters a high-impedance state. At the end of each transmission, if DXR was not reloaded when XINT was generated, XSREMPTY becomes active (low) at this point, indicating underflow. With externally generated frame sync, if XSREMPTY is active and a frame sync pulse is generated, any old data in the DXR is transmitted. This is explained in detail in section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26. Note that the first data bit transferred could have variable length if frame sync is generated externally and does not fall within one CLKX cycle (this is illustrated in Figure 96). Internally generated frame syncs are assured by 54x timings to be one CLKX cycle in duration.

Figure 96. Serial Port Transmit With Long FSX Pulse

CLKX

FSX

DX

MSB

MSB-1

MSB-2

Serial Ports

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Serial Port Interface

Serial port transmit with external frame sync pulses is similar to that with internal frame sync, with the exception that transfers do not actually begin until the external frame sync occurs. If the external frame sync occurs many CLKX cycles after DXR is loaded, however, the double buffer is filled and frozen until frame sync appears. On the SP (Figure 97), when the delayed frame sync occurs, A is transmitted on DX; after the transmit, a DXR-to-XSR copy of B occurs, XINT is generated, and again, the transmitter remains frozen until the next frame sync. When frame sync finally occurs, B is transmitted on DX. Note that when B is loaded into DXR, a DXR-to-XSR copy of B does not occur immediately because A has not been transmitted, and no XINT is generated. Any subsequent writes to DXR before the next delayed frame sync occurs overwrite B in the DXR.

Figure 97. Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (SP)
CLKX FSX (TXM = 0) DX (F0 = 1) XRDY (SP) XINT (SP) XSREMPTY (SP) A1 MSB A7 A8 LSB B1 B2

DXR loaded with A

XSR loaded with A

DXR loaded with B

XSR loaded with B

On the BSP (Figure 98), since DXR was reloaded with B shortly after being loaded with A when the delayed frame sync finally occurs, B is transmitted on DX. After the transmit, the transmitter remains frozen until the next frame sync. When frame sync finally occurs, B is again transmitted on DX. Note that when B is loaded into DXR, a DXR-to-XSR copy of B does not occur immediately since the BSP requires a frame sync to initiate transmitting. Any subsequent writes to DXR before the next delayed frame sync occurs overwrite B in the DXR.

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Serial Port Interface

Figure 98. Burst Mode Serial Port Transmit Operation With Delayed Frame Sync in External Frame Sync Mode (BSP)
CLKX FSX (TXM = 0) DX (F0 = 1) XRDY (BSP) XINT (BSP) XSREMPTY (BSP) B1 MSB B7 B8 LSB B1 B2

DXR loaded with A

DXR loaded with B

XSR loaded with B

XSR loaded with B

During a receive operation, shifting into RSR begins on the falling edge of the CLKR cycle after frame sync has gone low (as shown in Figure 99). Then, as the last data bit is being received, the contents of the RSR are transferred to the DRR on the falling edge of CLKR, and RRDY goes high, generating a receive interrupt (RINT).

Figure 99. Burst Mode Serial Port Receive Operation

CLKR FSR DR (FO = 1) RRDY RINT A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1 B2

DRR loaded from RSR

DRR read

If the DRR from a previous receive has not been read, and another word is received, no more bits can be accepted without causing data corruption since DRR and RSR are both full. In this case, the RSRFULL bit is set indicating this condition. On the SP, this occurs with the next FSR; on the BSP, RSRFULL is set on the falling edge of CLKR during the last bit received. RSRFULL timing on both the SP and BSP is shown in Figure 910.
Serial Ports
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Serial Port Interface

Figure 910. Burst Mode Serial Port Receive Overrun

CLKR FSR DR RRDY RINT RSRFULL(SP) RSRFULL(BSP) A1 MSB A8 LSB B1 MSB B8 LSB C1 MSB C2 C3 C4 C5

DRR loaded with A

Read A from DRR

Unlike transmit underflow, overrun (RSRFULL = 1) constitutes an actual error condition. While DRR contents are preserved in overrun, its occurrence can often result in loss of other received data. Overrun is handled differently on the SP and on the BSP. On the SP, the contents of RSR are preserved on overrun, but since RSRFULL is not set to 1 until the next FSR occurs after the overflowing reception, incoming data usually begins being lost as soon as RSRFULL is set. Data loss can only be avoided if RSRFULL is polled in software and the DRR is read immediately after RSRFULL is set to 1. This is normally possible only if the CLKR frequency is slow with respect to CLKOUT, since RSRFULL is set on the falling edge of CLKR during FSR, and data begins being received on the following rising edge of CLKR. The time available for polling RSRFULL and reading the DRR to avoid data loss is, therefore, only half of one CLKR cycle. On the BSP, RSRFULL is set on the last valid bit received, but the contents of RSR are never transferred to DRR, therefore, the complete transferred word in RSR is lost. If the DRR is read (clearing RSRFULL) before the next FSR occurs, subsequent transfers can be received properly. Overrun and various other serial port exception conditions such as the occurrence of frame sync during a receive are discussed in further detail in section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26. If the serial port receiver is provided with FSR pulses significantly longer than one CLKR cycle, timing of data reception is effected in a similar fashion as with long FSX pulses. With long FSR pulses, however, the reception of all bits, including the first one, is simply delayed until FSR goes low. Serial port receive operation with a long FSR pulse is illustrated in Figure 911.
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Serial Port Interface

Figure 911.Serial Port Receive With Long FSR Pulse

CLKR

FSR

DR

MSB

MSB-1

MSB-2

Note that if the packet transmit frequency is increased, the inactivity period between the data packets for adjacent transfers decreases to zero. This corresponds to a minimum period between frame sync pulses (equivalent to 8 or 16 CLKX/R cycles, depending on FO) that corresponds to a maximum packet frequency at which the serial port may operate. At maximum packet frequency, transmit timing is a compressed version of Figure 95, as shown in Figure 912.

Figure 912. Burst Mode Serial Port Transmit at Maximum Packet Frequency
CLKX FSX (TXM = 1) DX (FO = 1) XRDY (SP) XINT (SP) XRDY (BSP) XINT (BSP)
A7 A8 B1 MSB B2 B3 B4 B5 B6 B7 B8 LSB C1 C2 C3 C4

DXR loaded XSR loaded (SP)

XSR loaded (BSP)

DXR reloaded

XSR reloaded (SP)

XSR reloaded (BSP)

At maximum packet frequency, the data bits in consecutive packets are transmitted contiguously with no inactivity between bits. The frame sync pulse overlaps the last bit transmitted in the previous packet. Maximum packet frequency receive timing is similar and is shown in Figure 913.
Serial Ports
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Serial Port Interface

Figure 913. Burst Mode Serial Port Receive at Maximum Packet Frequency
CLKR FSR DR (FO = 1) RRDY RINT A8 B1 MSB B2 B3 B4 B5 B6 B7 B8 LSB C1 C2 C3 C4 C5

DRR loaded from RSR

DRR read

DRR loaded from RSR

DRR read

As shown in Figure 912 and Figure 913, with the transfer of multiple data packets at maximum packet frequency in burst mode, packets are transmitted at a constant rate, and the serial port clock provides sufficient timing information for the transfer, which permits a continuous stream of data. Therefore, the frame sync pulses are essentially redundant. Theoretically, then, only an initial frame sync signal is required to initiate the multipacket transfer. The 54x does support operation of the serial port in this fashion, referred to as continuous mode, which is selected by clearing the FSM bit in the SPC to 0. Continuous mode serial port operation is described in detail in section 9.2.5, Continuous Mode Transmit and Receive Operations.

9.2.5

Continuous Mode Transmit and Receive Operations

In continuous mode, a frame sync on FSX/FSR is not necessary for consecutive packet transfers at maximum packet frequency after the initial pulse. Continuous mode is selected by setting FSM = 0. Note that when FSM = 0, frame sync pulses are not required, but they are not ignored, therefore, improperly timed frame syncs may cause errors in serial transfers. Serial port operation under various error conditions is described in detail in section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26. In continuous mode transmission, one frame sync is generated following the first DXR load, and no further frame syncs are generated. As long as DXR is reloaded once every transmission, continuous transfers are maintained. Failing to update DXR causes the serial port to halt, as in the burst mode case (XSREMPTY becomes asserted, etc). If DXR is reloaded after a halt, the device begins continuous mode transmission again and generates a single FSX, assuming that internal frame sync generation is selected.

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Serial Port Interface

The distinction between internal and external frame syncs for continuous mode is similar to that of burst mode, as discussed in section 9.2.4, Burst Mode Transmit and Receive Operations, on page 9-18. If frame sync is externally generated (TXM = 0), then when DXR is loaded, the appearance of the frame sync pulse initiates continuous mode transmission. Continuous mode transmission may be discontinued (and burst mode resumed) only by reconfiguring and resetting the serial port (see section 9.2.2, Serial Port Interface Operation, on page 9-6). Simply changing the FSM bit during transmit or halt will not properly switch to burst mode. Continuous mode transmit timing, shown in Figure 914, is similar to maximum packet frequency transmission in burst mode as shown in Figure 912. The major difference is the lack of a frame sync pulse after the initial one. As long as DXR is updated once per transmission, this mode will continue. Overwrites to DXR behave just as in burst mode; the last data written will be transmitted. XSR operation is the same as in burst mode. A new external FSX pulse will abort the present transmission, cause one data packet to be lost, and initiate a new continuous mode transmit. This is explained in more detail in section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26.

Figure 914. Continuous Mode Serial Port Transmit

CLKX FSX (TXM = 1) DX (FO = 1) XRDY (SP) XINT (SP) XRDY (BSP) XINT (BSP) A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1 B2 B3 B4

DXR loaded XSR loaded (SP)

XSR loaded (BSP)

DXR reloaded

XSR reloaded (BSP) XSR reloaded (SP)

Continuous mode reception is similar to the transmit operation. After the initial frame sync pulse on FSR, no further frame syncs are required. This mode will continue as long as DRR is read every transmission. If DRR is not read by the end of the next transfer, the receiver will halt, and RSRFULL is set, indicating overrun. See section 9.2.6, Serial Port Interface Exception Conditions.
Serial Ports
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Serial Port Interface

Overrun in continuous mode effects the SP and the BSP differently. On the SP, once overrun has occurred, reading DRR will restart continuous mode at the next word/byte boundary after DRR is read; no new FSR pulse is required. On the BSP, continuous mode reception does not resume until DRR is read and an FSR occurs. Continuous mode reception may only be discontinued by reconfiguring and resetting the serial port. Simply changing the FSM bit during a reception or halt will not properly switch to burst mode. Continuous mode receive timing is shown in Figure 915.

Figure 915. Continuous Mode Serial Port Receive

CLKR FSR DR (FO = 1) RRDY RINT A1 MSB A2 A3 A4 A5 A6 A7 A8 LSB B1 B2 B3 B4 B5

DRR loaded from RSR

DRR read

Figure 915 shows only one frame sync pulse; otherwise, it is similar to Figure 913. If a pulse occurs on FSR during a transfer (an error), then the receive operation is aborted, one packet is lost, and a new receive cycle is begun. This is discussed in more detail in section 9.2.2, Serial Port Interface Operation, on page 9-6 and in section 9.2.6, Serial Port Interface Exception Conditions.

9.2.6

Serial Port Interface Exception Conditions

Exception (or error) conditions result from an unexpected event occurring on the serial port. These conditions are operational aberrations such as overrun, underflow, or a frame sync pulse during a transfer. Understanding how the serial port handles these errors and the state it acquires during these error conditions is important for efficient use of the serial port. Because the error conditions differ slightly in burst and continuous modes, they are discussed separately.

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Serial Port Interface

Burst Mode
In burst mode, one type of error condition (presented in section 9.2.2, Serial Port Interface Operation) is receive overrun, indicated by the RSRFULL flag. This flag is set when the device has not read incoming data and more data is being sent. If this condition occurs, the processor halts serial port receives until DRR is read. Thus, any further data sent may be lost. Overrun is handled differently on the SP and on the BSP. On the SP, the contents of RSR are preserved on overrun, but since RSRFULL is not set to 1 until the next FSR occurs after the overflowing reception, incoming data usually begins being lost as soon as RSRFULL is set. Data loss can only be avoided if RSRFULL is polled in software and the DRR is read immediately after RSRFULL is set to 1. This is normally possible only if the CLKR frequency is slow with respect to CLKOUT, since RSRFULL is set on the falling edge of CLKR during FSR, and data begins being received on the following rising edge of CLKR. The time available for polling RSRFULL and reading the DRR to avoid data loss is, therefore, only half of one CLKR cycle. On the BSP, RSRFULL is set on the last valid bit received, but the contents of RSR are never transferred to DRR, therefore, the complete transferred word in RSR is lost. If the DRR is read (clearing RSRFULL) before the next FSR occurs, subsequent transfers can be received properly. Another type of receive error is caused if frame sync occurs during a receive (that is, data is being shifted into RSR from DR). If this happens, the present receive is aborted and a new one begins. Thus, the data that was being loaded into RSR is lost, but the data in DRR is not (no RSR-to-DRR copy occurs). Burst mode serial port receiver behavior under normal and error conditions for the SP is shown in Figure 916 and for the BSP is shown in Figure 917.

Figure 916. SP Receiver Functional Operation (Burst Mode)

FSR pulse occurs

Receive in progress ?

No

Is RSRFULL set ? Yes

No

Is RSR full ?

No

Start new data receive

Yes Abort receive. Start next reception. (No RSR to DRR, thus, 1 word lost)

Yes Set RSRFULL=1

Ignore FSR pulse

Serial Ports

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Serial Port Interface

Figure 917. BSP Receiver Functional Operation (Burst Mode)

FSR pulse occurs

Receive in progress ?

No

Is RSRFULL set ? Yes Ignore FSR pulse

No

Start new data receive

Yes Abort receive. Start next reception. (No RSR to DRR, thus, 1 word lost)

Transmitter exception conditions in burst mode may occur for several possible reasons. Underflow, which is described in section 9.2.3, Configuring the Serial Port Interface, on page 9-8 is an exception condition that may occur in burst mode, however, underflow is not normally considered an error. An exception condition that causes errors in transmitted data occurs when frame sync pulses occur at inappropriate times during a transfer. If a transmit is in progress (that is, XSR data is being driven on DX) when a frame sync pulse occurs, the transmission is aborted, and the data in XSR is lost. Then, whatever data is in DXR at the time of the frame sync pulse is transferred to XSR (DXR-to-XSR copy) and is transmitted. Note, however, that in this case an XINT is generated only if the DXR has been written to since the last transmit. Also, if XSREMPTY is active and a frame sync pulse occurs, the old data in DXR is shifted out. Figure 918 summarizes serial port transmit behavior under error and nonerror conditions. Note that if an FSX occurs when no transmit is in progress, and DXR has been reloaded since the last transmit, the DXR-to-XSR copy and generation of transmit interrupt occur at this point only on the BSP. On the SP, these two events occur at the time the DXR was reloaded.

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Serial Port Interface

Figure 918. SP/BSP Transmitter Functional Operation (Burst Mode)

FSX pulse occurs

Transmit in progress?

No

New DXR since last transmit ?

No

XSREMPTY is low, DXR-to-XSR copy occurs. No transmit interrupt. Start transmit.

Yes Abort transmit

Yes DXR-to-XSR copy (BSP only). Transmit interrupt (BSP only). Start transmit.

New DXR written since last transmit ?

No

DXR-to-XSR copy. No transmit interrupt. Start transmit.

Yes DXR-to-XSR copy. Transmit interrupt. Start transmit (1 word is lost).

Continuous Mode
In continuous mode, errors take on a broader meaning, since data transfer is intended to occur at all times. Thus, underflow (XSREMPTY = 0) constitutes an error in continuous mode because data will not be transmitted. As in burst mode, overrun (RSRFULL = 1) is also an error, and in continuous mode, both overrun and underflow cause the serial port receive or transmit sections, respectively, to halt (see section 9.2.3, Configuring the Serial Port Interface, on page 9-8 for a description of these conditions). Fortunately, underflow and overrun errors may not be catastrophic; they can often be corrected simply by reading DRR or writing to DXR. The SP and the BSP are affected differently when overrun occurs in continuous mode. In the SP, when DRR is read to deactivate RSRFULL, a frame sync pulse is not required in order to resume continuous mode operation. The receiver keeps track of the transfer word boundary, even though it is not receiving data. Therefore, when the RSRFULL flag is deactivated by a read from DRR, the receiver begins reading from the correct bit. On the BSP, since an FSR pulse is required to restart continuous reception, this also reestablishes the proper bit alignment, in addition to restarting reception. Figure 919 shows receiver functional operation in continuous mode.
Serial Ports
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Serial Port Interface

Figure 919. SP/BSP Receiver Functional Operation (Continuous Mode)

FSR pulse occurs Ignore pulse, since RSRFULL is active

Receive in progress ?

No

Yes Abort current receive. Start next reception. (No RSR-to-DRR copy; thus, current word is lost)

During a receive in continuous mode, if a frame sync pulse occurs, this causes a receive abort condition, and one packet of data is lost (this is caused because the frame sync pulse resets the RSR bit counter). The data present on DR then begins being shifted into RSR, starting again from the first bit. Note that if a frame sync occurs after deactivating the RSRFULL flag by reading DRR, but before the beginning of the next word boundary, this also creates a receive abort condition. Another cause for error is the appearance of extraneous frame syncs during a transmission. After the initial frame sync in continuous mode, no others are required; if an improperly timed frame sync pulse occurs during a transmit, the current transfer (that is, serially driving XSR data onto DX) is aborted, and data in XSR is lost. A new transmit cycle is initiated, and transfers continue as long as the DXR is updated once per transmission afterward. Figure 920 shows continuous mode transmitter functional operation. Note that if XSREMPTY is active in continuous mode and an external frame sync occurs, the previous DXR data is transmitted as in burst mode operation.

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Serial Port Interface

Figure 920. SP/BSP Transmitter Functional Operation (Continuous Mode)

FSX pulse occurs

Transmit in progress ?

No

XSREMPTY is low, DXR-to-XSR copy occurs. No transmit interrupt. Start transmit.

Yes Abort transmit

New DXR since last transmit ?

No

DXR-to-XSR copy. No transmit interrupt. Start transmit.

Yes DXR-to-XSR copy. Transmit interrupt. Start new transmit. (Current word is lost)

9.2.7

Example of Serial Port Interface Operation

As an illustration of the proper operation of a standard serial port, Example 91 and Example 92 define a sequence of actions. This illustration is based on the use of interrupts to handle the normal I/O between the serial port and CPU. The 545 peripheral configuration has been used as a reference for these examples.

Serial Ports

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Serial Port Interface

Example 91. Serial Port Initialization Routine

Action 1) Reset and initialize the serial port by writing 0038h (or 0008h) to SPC. Description This places both the transmit and receive portions of the serial port in reset and sets up the serial port to operate with internally generated FSX and CLKX signals and FSX/FSR required for transmit/ receive of each 16-bit word. (The alternative is used if another device will provide FSX and CLKX.) Eliminate any interrupts that may have occurred before initialization. Enable both transmit and receive interrupts. A common alternative when transmit and receive are synchronized to one another is to enable only one or the other, by ORing 0080h or 0040h with IMR, and performing both I/O operations with the same interrupt service routine (ISR). Interrupts must be globally enabled for the CPU to respond. This takes both the transmit and receive portions of the serial port out of reset and starts operations with the conditions defined in step 1. This initiates serial port transmit operations if FSX and CLKX are internally generated or prepares the serial port transmit for operation when the first FSX arrives.

2) 3)

Clear any pending serial port interrupts by writing 00C0h to IFR. Enable the serial port interrupts by ORing 00C0h with IMR.

4) 5)

Enable interrupts globally (if necessary) by clearing the INTM bit in ST1. Start the serial port by writing 00F8h (or 00C8h) to SPC. Write the first data value to DXR. (If the serial port is connected to the serial port of another processor and this processor will be generating FSX, a handshake must be performed prior to writing the first data value to DXR.)

6)

Example 92. Serial Port Interrupt Service Routine

Action 1) 2) Save any context that may be modified on the stack. Read the DRR or write the DXR or both. The data read form DRR should be written to a predetermined location in memory. The data written to DXR should be read from a predetermined location in memory. Restore the context that was saved in step 1. Return from the ISR with an RETE to reenable interrupts. Description The operating context of the interrupted code must be maintained. Read the received data for the receive ISR. Write the new transmit data for the transmit ISR. Or, do both if the ISR is combined for transmit and receive.

3) 4)

The operating context of the interrupted code must be maintained. Interrupts must be reenabled for the CPU to respond to the next interrupt.

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Buffered Serial Port (BSP) Interface

9.3 Buffered Serial Port (BSP) Interface

The buffered serial port (BSP) is made up of a full-duplex, double-buffered serial port interface, which functions in a similar manner to the 54x standard serial port, and an autobuffering unit (ABU) (see Figure 921). The serial port section of the BSP is an enhanced version of the 54x standard serial port. The ABU is an additional section of logic which allows the serial port section to read/write directly to 54x internal memory independent of the CPU. This results in a minimum overhead for serial port transfers and faster data rates. The full duplex BSP serial interface provides direct communication with serial devices such as codecs, serial A/D converters, and other serial devices with a minimum of external hardware. The double-buffered BSP allows transfer of a continuous communication stream in 8-,10-,12- or 16-bit data packets. Frame synchronization pulses as well as a programmable frequency serial clock can be provided by the BSP for transmission and reception. The polarity of frame sync and clock signals are also programmable. The maximum operating frequency is CLKOUT (40 Mbit/s at 25 ns, 50 Mbit/s at 30 ns). The BSP transmit section includes a pulse code modulation (PCM) mode that allows easy interface with a PCM line. Operation of the BSP in standard (nonbuffered) mode is detailed in section 9.3.1 on page 9-35. The ABU has its own set of circular addressing registers, each with corresponding address generation units. Memory for transmit and receive buffers resides within a special 2K word block of 54x internal memory. This memory can also be used by the CPU as general purpose storage, however, this is the only memory block in which autobuffering can occur. Using autobuffering, word transfers occur directly between the serial port section and the 54x internal memory automatically using the ABU embedded address generators. The length and starting addresses of the buffers within the 2K block are programmable, and a buffer empty/full interrupt can be generated to the CPU. Buffering can easily be halted using the autodisabling capability. ABU operation is detailed in section 9.3.2 on page 9-40. The BSP autobuffering capability can be separately enabled for the transmit and receive sections. When autobuffering is disabled (standard mode), data transfers with the serial port section occur under software control in the same fashion as with the standard 54x serial port. In this mode, the ABU is transparent, and the WXINT and WRINT interrupts generated each time a word is transmitted or received are sent to the CPU as transmit interrupt (BXINT) and receive interrupt (BRINT). When autobuffering is enabled, the BXINT and BRINT interrupts are only generated to the CPU each time half of the buffer is transferred.
Serial Ports
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Buffered Serial Port (BSP) Interface

Figure 921. BSP Block Diagram

54x memory interface
DATA BUS ADDRESS BUS

11

Read

Write

54x CPU interface

16

Autobuffering unit module

Control XRDY

RRDY

BXINT BMINT BRINT

BCLKX BFSX

BDXR

BSPCE

WXINT

BXINT

BDX BDR

BXSR Serial port control logic BRSR WRINT Interrupt control

BMINT

Interrupt logic

BRINT

BCLKR BFSR BDRR BSPC

Serial port interface module

As mentioned previously, most aspects of BSP operation are similar to that of the 54x standard serial port. section 9.2, Serial Port Interface, on page 9-4 discusses operation of both the 54x standard serial port and the BSP in standard mode. Since standard mode BSP operation is a superset of standard serial port operation, section 9.2, Serial Port Interface, should first be studied before the rest of this section is read. System considerations of BSP operation such as initialization and low power modes are discussed in section 9.3.3 on page 9-49.
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Buffered Serial Port (BSP) Interface

9.3.1

BSP Operation in Standard Mode

BSP operation in standard mode is discussed in section 9.2, Serial Port Interface, on page 9-4. This section summarizes the differences between serial port operation and standard mode BSP operation and describes the enhanced features that the BSP offers. The enhanced BSP features are available both in standard mode and in autobuffering mode. ABU is discussed in section 9.3.2 on page 9-40. Information presented in this section assumes familiarity with standard mode operation as described in section 9.2, Serial Port Interface. The BSP uses its own dedicated memory-mapped data transmit, data receive and serial port control registers (BDXR, BDRR, and BSPC). The BSP also utilizes an additional control register, the BSP control extension register (BSPCE), in implementing its enhanced features and controlling the ABU. The BDRR, BDXR, and BSPC registers function similarly to their counterparts in the serial port as described in section 9.2, Serial Port Interface. As with the serial port, the BSP transmit and receive shift registers (BXSR and BRSR) are not directly accessible in software but facilitate the double-buffering capability. If the serial port is not being used, the BDXR and the BDRR registers can be used as general purpose registers. In this case, BFSR should be set to an inactive state to prevent a possible receive operation from being initiated. Note, however, that program access to BDXR or BDRR is limited when autobuffering is enabled for transmit or receive, respectively. BDRR can only be read, and BDXR can only be written when the ABU is disabled. BDRR can only be written when the BSP is in reset. BDXR can be read any time. The buffered serial port registers are summarized in Table 97. The ABU utilizes several additional registers which are discussed in section 9.3.2, Autobuffering Unit (ABU) Operation, on page 9-40.

Table 97. Buffered Serial Port Registers

Address Register BDRR BDXR BSPC BSPCE BRSR BXSR Description 16-bit BSP data receive register 16-bit BSP data transmit register 16-bit BSP control register 16-bit BSP control extension register 16-bit BSP data receive shift register 16-bit BSP data transmit shift register

See section 8.2, Peripheral Memory-Mapped Registers.

Serial Ports

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Buffered Serial Port (BSP) Interface

9.3.1.1

Differences Between Serial Port and BSP Operation in Standard Mode

The differences between serial port and BSP operation in standard mode are discussed in detail in the standard mode serial port operation (section 9.2 on page 9-4). These differences relate primarily to boundary conditions, however, in some systems, these differences may be significant. The differences are summarized in Table 98.

Table 98. Differences Between Serial Port and BSP Operation in Standard Mode
Condition RSRFULL is set. Serial Port RSRFULL is set when RSR is full and then an FSR occurs, except in continuous mode where RSRFULL is set as soon as RSR is full. RSR contents are preserved on overrun. Receive restarts as soon as DRR is read (see section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26). No Occur when DXR is loaded. DRR and DXR can be read or written under program control at any time. Note that caution should be exercised when reads and writes of the DRR may be close in time to serial port receptions. In this case, a DRR read may not yield the result that was previously written by the program. Also note that rewrites of DXR may cause loss (and therefore non-transmission) of previously written data depending on the relative timing of the writes and FSX (see section 9.2.4, Burst Mode Transmit and Receive Operations, on page 9-18). CLKOUT/4 BSP RSRFULL is set as soon as BRSR is full.

Preservation of data in RSR on overrun. Continuous mode receive restart after overrun.

BRSR contents are not preserved on overrun. Receive does not restart until BDRR is read and then a BFSR occurs. Yes Occur when when a BFSX occurs after BDXR is loaded. BDRR can only be read and BDXR can only be written when the ABU is disabled. BDRR can only be written when the BSP is in reset. BDXR can be read any time. The same precautions with regard to reads and writes to these registers apply as in serial port.

Sign extension in DRR on 8-, 10-, or 12-bit transfers. XSR load, XSREMPTY clear, XRDY/XINT generation. Program accessibility to DXR and DRR.

Maximum serial port clock rate.

CLKOUT

9-36

Buffered Serial Port (BSP) Interface

Table 98. Differences Between Serial Port and BSP Operation in Standard Mode (Continued)
Condition Initialization timing requirements. Serial Port On the serial port, the serial port may be taken out of reset at any time with respect to FSX/FSR, however, if XRST/RRST go high during or after the frame sync, the frame sync may be ignored. BSP On the BSP, exiting serial port reset under certain conditions must precede FSX timing by one CLKOUT cycle in standard mode and by six CLKOUT cycles in autobuffering mode (see section 9.3.3, System Considerations of BSP Operation, on page 9-49). Yes (see section 9.3.3, System Considerations of BSP Operation, on page 9-49).

Operates in IDLE2/3 mode.

No

9.3.1.2

Enhanced BSP Features

The enhanced features that the BSP offers include the capability to generate programmable rate serial port clocks, select positive or negative polarities for clock and frame sync signals, and to perform transfers of 10- and 12-bit words, in addition to the 8- and 16-bit transfers offered by the serial port. Additionally, the BSP implements the capability to specify that frame sync signals be ignored until instructed otherwise, and provides a dedicated operating mode which facilitates its use with PCM interfaces. The BSPCE contains the control and status bits that are used in the implementation of these enhanced BSP features and the ABU. The 10 LSBs of BSPCE are dedicated to the enhanced features control, whereas the 6 MSBs are used for ABU control, which is discussed in section 9.3.2, Autobuffering Unit (ABU) Operation, on page 9-40. Figure 922 shows the BSPCE bit positions and Table 99 summarizes the function of the BSPCE bits. The value of the BSPCE upon reset is 3. This results in standard mode operation compatible with the serial port.

Figure 922. BSP Control Extension Register (BSPCE) Diagram Serial Port Control Bits

1510 9 8 7 6 5 40 ABU control PCM
R/W

FIG

FE

CLKP
R/W

FSP
R/W

CLKDV
R/W

R/W

R/W

Note:

R = Read, W = Write

Serial Ports

9-37

Buffered Serial Port (BSP) Interface

Table 99. BSP Control Extension Register (BSPCE) Bit Summary Serial Port Control Bits
Bit 1510 Name ABU control PCM Reset value Function Reserved for autobuffering unit control (see section 9.3.2, Autobuffering Unit (ABU) Operation, on page 9-40). Pulse Code Modulation Mode. This control bit puts the serial port in pulse code modulation (PCM) mode. The PCM mode only affects the transmitter. BDXR-toBXSR transfer is not affected by the PCM bit value. PCM = 0 PCM = 1 Pulse code modulation mode is disabled. Pulse code modulation mode is enabled. In PCM mode, BDXR is transmitted only if its most significant (215) bit is set to 0. If this bit is set to 1, BDXR is not transmitted and BDX is put in high impedance during the transmission period.

FIG

Frame Ignore. This control bit operates only in transmit continuous mode with external frame and in receive continuous mode. FIG = 0 Frame sync pulses following the first frame pulse restart the transfer. Frame sync pulses following the first frame pulse that initiates a transfer operation are ignored.

FIG = 1

FE

Format Extension. The FE bit in conjunction with FO in SPC (section 9.2.3, Setting the Serial Port Configuration, on page 9-8) specifies the word length. When FO FE = 00, the format is 16-bit words; when FO FE = 01, the format is 10-bit words; when FO FE = 10, the format is 8-bit words; and when FO FE = 11, the format is 12-bit words. Note that for 8-, 10-, and 12-bit words, the received words are right justified and the sign bit is extended to form a 16-bit word. Words to transmit must be right justified. See Table 910 for the word length configurations. Clock Polarity. This control bit specifies when the data is sampled by the receiver and transmitter. CLKP = 0 Data is sampled by the receiver on BCLKR falling edge and sent by the transmitter on BCLKX rising edge. Data is sampled by the receiver on BCLKR rising edge and sent by the transmitter on BCLKX falling edge.

CLKP

CLKP = 1

FSP

Frame Sync Polarity. This control bit specifies whether frame sync pulses (BFSX and BFSR) are active high or low. FSP = 0 FSP = 1 Frame sync pulses (BFSX and BFSR) are active high. Frame sync pulses (BFSX and BFSR) are active low.

9-38

Buffered Serial Port (BSP) Interface

Table 99. BSP Control Extension Register (BSPCE) Bit Summary Serial Port Control Bits (Continued)
Bit 40 Name CLKDV Reset value 00011 Function Internal Transmit Clock Division factor. When the MCM bit of BSPC is set to 1, CLKX is driven by an on-chip source having a frequency equal to 1/(CLKDV+1) of CLKOUT. CLKDV range is 031. When CLKDV is odd or equal to 0, the CLKX duty cycle is 50%. When CLKDV is an even value (CLKDV=2p), the CLKX high and low state durations depend on CLKP. When CLKP is 0, the high state duration is p+1 cycles and the low state duration is p cycles; when CLKP is 1, the high state duration is p cycles and the low state duration is p+1 cycles.

Table 910. Buffered Serial Port Word Length Configuration

FO 0 0 1 1 FE 0 1 0 1 Buffered Serial Port Word Length Configuration 16-bit words transmitted and received. (Reset values) 10-bit words transmitted and received. 8-bit words transmitted and received. 12-bit words transmitted and received.

These enhanced features allow greater flexibility in serial port interface in a variety of areas. In particular, the frame ignore feature offers a capability which allows a mechanism for effectively compressing transferred data packets if they are not transferred in 16 bit format. This feature is used with continuous receptions and continuous transmits with external frame sync. When FIG = 0, if a frame sync pulse occurs after the initial one, the transfer is restarted; when FIG = 1, this frame sync is ignored. Setting FIG to 1 allows, for example, effectively achieving continuous 16-bit transfers under circumstances where frame sync pulses occur every 8-, 10- or 12-bits. Without using FIG, each transfer of less than 16 bits requires an entire 16-bit memory word, and each 16 bits transferred as two 8-bit bytes requires two memory words and two transfer operations, rather than one of each. Using FIG, therefore, can result in a significant improvement in buffer size requirement in both autobuffered and standard mode, and a significant improvement in CPU cycle overhead required to handle serial port transfers in standard mode. Figure 923 shows an example with the BSP configured in 16-bit format but with a frame sync after 8 bits.
Serial Ports
9-39

Buffered Serial Port (BSP) Interface

Figure 923. Transmit Continuous Mode with External Frame and FIG = 1 (Format Is 16 Bits)
CLKX/ CLKR Frame ignored FSX/FSR

DX/DR

MSB

RRDY

XRDY

DXR reloaded

9.3.2

Autobuffering Unit (ABU) Operation

Since ABU functionality is a superset of standard mode serial port operation, the following sections should be read prior to reading this section: section 9.2, Serial Port Interface, on page 9-4, and section 9.3.1, BSP Operation in Standard Mode, on page 9-35 Also, you should note that when operating in autobuffering mode, the serial port control and status bits in BSPC and BSPCE function in the same fashion as in standard mode. The ABU implements the capability to move data transferred on the serial port to and from internal 54x memory independent of CPU intervention. The ABU utilizes five memory-mapped registers: the address transmit register (AXR), the block size transmit register (BKX), the address receive register (ARR), and the block size receive register (BKR), along with the BSPCE. These registers are summarized in Table 911.

Table 911. Autobuffering Unit Registers

Address Register BSPCE AXR BKX ARR BKR Description 16-bit BSP control extension register 11-bit BSP address transmit register (ABU) 11-bit BSP transmit buffer size register (ABU) 11-bit BSP address receive register (ABU) 11-bit BSP receive buffer size register (ABU)

See section 8.2, Peripheral Memory-Mapped Registers.

9-40

Buffered Serial Port (BSP) Interface

Figure 924 shows the block diagram of the ABU. The BSPCE contains bits which control ABU operation and will be discussed in detail later in this section. AXR, BKX, ARR, and BKR, along with their associated circular addressing logic, allow address generation for accessing words to be transferred between the 54x internal memory and the BSP data transmit register (BDXR) and BSP data receive register (BDRR) in autobuffering mode. The address and block size registers as well as circular addressing are also discussed in detail later in this section. Note that the 11-bit memory mapped AXR, BKX, ARR, and BKR registers are read as 16-bit words, with the five most significant bits read as zeroes and the 11-bit register contents right justified in the least significant 11 bits. If autobuffering is not used, these registers can be used for general purpose storage of 11-bit data. The transmit and receive sections of the ABU can be enabled separately. When either section is enabled, access to its corresponding serial port data register (BDXR or BDRR) through software is limited. The BDRR can only be read, and the BDXR can only be written when the ABU is disabled. The BDRR can only be written when the BSP is in reset. The BDXR can be read any time. When either transmit or receive autobuffering is disabled, that section operates in standard mode, and its portion of the ABU is transparent. The ABU also implements CPU interrupts when transmit and receive buffers have been halfway or entirely filled or emptied. These interrupts take the place of the transmit and receive interrupts in standard mode operation (the receive interrupt is the CPU). They are not generated in autobuffering mode. This mechanism features an autodisabling capability that can be used to automatically terminate autobuffering when either the half-of-buffer or bottom-of-buffer boundary is crossed. These features are described in detail later in this section.

Serial Ports

9-41

Buffered Serial Port (BSP) Interface

Figure 924. ABU Block Diagram

54x memory interface

DATA BUS ADDRESS BUS

11

Read

Write

MUX
11 11

Autobuffering unit module 54x CPU interface ABU control BXINT RRDY BMINT BRINT

AXR
16

ARR

BKX

BKR XRDY Control

BCLKX BFSX

BDXR

BSPCE WXINT BXINT

BDX BDR

BXSR BRSR

Serial port control logic WRINT

BMINT Interrupt control

Interrupt logic

BRINT

BCLKR BFSR BDRR BSPC

Serial port interface module

Burst or continuous mode, as described in section 9.2, Serial Port Interface, can be used in conjunction with the autobuffering capability. Note that due to the nature of autobuffering mode, however, if burst mode with internal frame sync is selected, this will effectively result in continuous transmission with FSX generated by the BSP at the start of each transmission.
9-42

Buffered Serial Port (BSP) Interface

The internal 54x memory used for autobuffering consists of a 2K-word block of dual-access memory that can be configured as data, program, or both (as with other dual-access memory blocks). This memory can also be used by the CPU as general purpose storage, however, this is the only memory block in which autobuffering can occur. Since the BSP is implemented on several different TMS320 devices, the actual base address of the ABU memory may not be the same in all cases. The memory map for the particular device being used should be consulted for the actual base address of its ABU memory. When the ABU is enabled, this 2K-word block of memory can still be accessed by the CPU within data and/or program spaces. Conflicts may therefore occur between the CPU and the ABU if the 2K-word block is accessed at the same time by both. If a conflict does occur, priority is given to the ABU, resulting in the CPU access being delayed by one cycle. Accordingly, the worst case situation is that a CPU access could be delayed one cycle each time the ABU accesses the memory block, that is, for every new word transmitted or received. Note that when on-chip program memory is secured using the ROM protection feature, the 2K-word block of ABU memory cannot be mapped to program memory. For further information regarding the ROM protection feature, see section 3.5, Program and Data Security, on page 3-30. When the ABU is enabled for both transmit and receive, if transmit and receive requests from the serial port interface occur at same time, the transmit request takes priority over the receive request. In this case, the transmit memory access occurs first, delaying the receive memory access by generating a wait state. When the transmit memory access is completed, the receive memory access takes place.

9.3.2.1

Autobuffering Control Register

The most-significant six bits in the BSPCE constitute the ABU control register (ABUC). Some of these bits are read only, while others are read/write. Figure 925 shows the ABUC bit positions and Table 912 summarizes the function of each ABUC bit in the BSPCE. The value of the BSPCE upon reset is 3.

Figure 925. BSP Control Extension Register (BSPCE) Diagram ABU Control Bits

15 14 13 12 11 10 90 HALTR
R/W

RH
R

BRE
R/W

HALTX
R/W

XH
R

BXE
R/W

Serial Port control

Note:

R = Read, W = Write

Serial Ports

9-43

Buffered Serial Port (BSP) Interface

Table 912. BSP Control Extension Register (BSPCE) Bit Summary ABU Control Bits
Bit 15 Name HALTR Reset value 0 Function Autobuffering Receive Halt. This control bit determines whether autobuffering receive is halted when the current half of the buffer has been received. HALTR = 0 HALTR = 1 Autobuffering continues to operate when the current half of the buffer has been received. Autobuffering is halted when the current half of the buffer has been received. When this occurs, the BRE bit is cleared to 0 and the serial port continues to operate in standard mode.

14

RH

Receive Buffer Half Received. This read-only bit indicates which half of the receive buffer has been filled. Reading RH when the RINT interrupt occurs (seen either as a program interrupt or by polling IFR) is a convenient way to identify which boundary has just been crossed. RH = 0 RH = 1 The first half of the buffer has been filled and that receptions are currently placing data in the second half of the buffer. The second half of the buffer has been filled and that receptions are currently placing data in the first half of the buffer.

13

BRE

Autobuffering Receive Enable. This control bit enables autobuffering receive. BRE = 0 BRE = 1 Autobuffering is disabled and the serial port interface operates in standard mode. Autobuffering is enabled for the receiver.

12

HALTX

Autobuffering Transmit Halt. This control bit determines whether autobuffering transmit is halted when the current half of the buffer has been transmitted. HALTX = 0 HALTX = 1 Autobuffering continues to operate when the current half of the buffer has been transmitted. Autobuffering is halted when the current half of the buffer has been transmitted. When this occurs, the BXE bit is cleared to 0 and the serial port continues to operate in standard mode.

9-44

Buffered Serial Port (BSP) Interface

Table 912. BSP Control Extension Register (BSPCE) Bit Summary ABU Control Bits (Continued)
Bit 11 Name XH Reset value 0 Function Transmit Buffer Half Transmitted. This read-only bit indicates which half of the transmit buffer has been transmitted. Reading XH when the XINT interrupt occurs (seen either as a program interrupt or by polling IFR) is a convenient way to identify which boundary has just been crossed. XH = 0 The first half of the buffer has been transmitted and transmissions are currently taking data from the second half of the buffer. The second half of the buffer has been transmitted and transmissions are currently taking data from the first half of the buffer.

XH = 1

10

BXE

Autobuffering Transmit Enable. This control bit enables the autobuffering transmit. BXE = 0 BXE = 1 Autobuffering is disabled and the serial port operates in standard mode. Autobuffering is enabled for the transmitter.

90

Serial Port control

Serial Port Interface Control bits (see section 9.3.1.2, Enhanced BSP Features, on page 9-37).

9.3.2.2

Autobuffering Process
The autobuffering process occurs between the ABU and the 2K-word block of ABU memory. Each time a serial port transfer occurs, the data involved is automatically transferred to or from a buffer in the 2K-word block of memory under control of the ABU. During serial port transfers in autobuffering mode, interrupts are not generated with each word transferred as they are in standard mode operation. This prevents the overhead of having the CPU directly involved in each serial port transfer. Interrupts are generated to the CPU only each time one of the half-buffer boundaries is crossed. Within the 2K-word block of ABU memory, the starting address and size of the buffers allocated is programmable using the 11-bit address registers (AXR and ARR) and the 11-bit block size registers (BKX and BKR). The transmit and receive buffers can reside in independent areas, overlapping areas or the same area, which allows transmitting from a buffer while receiving into the same buffer if desired.
Serial Ports
9-45

Buffered Serial Port (BSP) Interface

The autobuffering process utilizes a circular addressing mechanism to access buffers within the 2K word block of ABU memory. This mechanism operates in the same fashion for transmit and receive. For each direction (transmit or receive), two registers specify the buffer size and the current address in the buffer. These registers are the block size and address register for transmit and receive (BKX, BKR, ARX, ARR, respectively). Each of the block size and address register pairs fully specify the top and bottom of buffer addresses for transmit and receive. Note that this circular addressing mechanism only effects accesses into the 2K-word block by the ABU. Accesses to this memory by the CPU are performed strictly according to the addressing mode(s) selected in the assembly language instructions which perform the memory access. The circular addressing mechanism automatically recirculates ABU memory accesses through the specified buffer, returning to the top of the buffer each time the bottom of the buffer is reached. The circular addressing mechanism is initialized by loading BKX/R with the exact size of the desired buffer (as opposed to size1) and ARX/R with a value which contains both the base address of the buffer within the 2K word block and the initial starting address within this buffer (this is explained in detail below). Often the initial starting address within the buffer is 0, indicating the start of the buffer (the top-of-buffer address), but the initial starting address may be any point within the defined buffer range. Once initialized, BKX/R can be considered to consist of two parts; the most significant or higher part (BKH), which corresponds to the all of the most significant 0 bits of BKX/R, and the lower part (BKL), which is the remaining bits, of which the most significant bit is a 1 and whose bit position is designated bit position N. The N bit position also defines the two parts (ARH and ARL) of the address register. The top of buffer address (TBA) is defined by the concatenation of ARH with N+1 least significant 0 bits. The bottom of buffer address (BBA) is defined by the concatenation of ARH and BKL1, and the current address within the buffer is specified by the complete contents of ARX/R. A circular buffer of size BKX/R must therefore start on an N-bit boundary (the N least significant bits of the address register are 0) where N is smallest integer that satisfies 2N > BKX/R, or at the lowest address within the 2K memory block. The buffer consists of two halves: the address range for the first half is TBA (BKL/2) 1 and for the second half BKL/2 (BKL 1). Figure 926 illustrates all of the relationships between the defined buffer and the BKX/R and ARX/R registers, the bottom of circular buffer address (BBA), and the top of circular buffer address (TBA).

9-46

Buffered Serial Port (BSP) Interface

Figure 926. Circular Addressing Registers

TBA ARH 00 Top of Buffer

10 ARH

N ARL

0 FIRST HALF Current location in buffer

Address register (ARX/R) ARH 10 00 BKH N 1 BKL BBA ARH BKL Bottom of Buffer +1 SECOND HALF 0 BKL >>1 Second Half Start

Block size register (BKX/R)

The minimum block size for an ABU buffer is two; the maximum block size is 2047, and any buffer of 2047 to 1024 words must start at a relative address of 0x0000 with respect to the base address of the 2K block of ABU memory. If either of the address registers (AXR or ARR) is loaded with a value specifying a location that is outside the range of the currently allocated buffer size as defined by BKX/R, improper operation may result. Subsequent memory accesses will be performed starting at the location specified, despite the fact that they will be to locations which are outside the range of the desired buffer, and the ARX/R will be incremented with each access until its contents reach the next permitted buffer start address. Any further accesses are then performed using the correct circular buffering algorithm with the new ARX/R contents as the updated buffer start address. It should be noted that any accesses performed with improperly loaded ARX/Rs may therefore unexpectedly corrupt some memory locations. The following example illustrates some of these functional aspects of the autobuffering process. Consider a transmit buffer of size 5 (BKX = 5) and a receive buffer of size 8 (BKR = 8) as shown in Figure 927. The transmit buffer may start at any relative address that is a multiple of 8 (address 0x0000, 0x0008, 0x0010, 0x0018, ..., 0x07F8), and the receive buffer may start at any relative address that is a multiple of 16 (0x0000, 0x0010, 0x0020, ..., 0x07F0). In this
Serial Ports
9-47

Buffered Serial Port (BSP) Interface

example, the transmit buffer starts at relative address 0x0008 and the receive buffer starts at relative address 0x0010. AXR may therefore contain any value in the range 0x00080x000C and ARR may contain any value in the range 0x00100x0017. If AXR in this example had been loaded with the value 0x000D (not acceptable in a modulo 5 buffer), memory accesses would be performed and AXR incremented until it reaches address 0x0010 which is an acceptable starting address for a modulo 5 buffer. Note, however, that if this had occurred, AXR would then specify a transmit buffer starting at the same base address as the receive buffer, which may cause improper buffer operation.

Figure 927. Transmit Buffer and Receive Buffer Mapping Example

0000h

Transmit BKX = 5

0008h 000Ah 000Ch AXR

0010h Receive 0014h BKR = 8 0017h ARR

The autobuffering process is activated upon request from serial port interface when XRDY or RRDY goes high, indicating that a word has been received. The required memory access is then performed, following which an interrupt is generated if half of the defined buffer (first or second) has been processed. The RH and XH flags in BSPCE indicate which half has been processed when the interrupt occurs.
9-48

Buffered Serial Port (BSP) Interface

When autodisabling is selected (HALTX or HALTR bit is set), then when the next half (first or second) buffer boundary is encountered, the autobuffering enable bit in the BSPCE (BXE or BRE) is cleared so that autobuffering is disabled and does not generate any further requests. When transmit autobuffering is halted, transmission of the current XSR contents and the last value loaded in DXR are completed, since these transfers have already been initiated. Therefore, when using the HALTX function, some delay will normally occur between crossing a buffer boundary and transmission actually stopping. If it is necessary to identify when transmission has actually ended, software should poll for the condition of XRDY = 1 and XSREMPTY = 0, which occurs after last bit has been transmitted. In the receiver, when using HALTR, since autobuffering is stopped when the most recent buffer boundary is crossed, future receptions may be lost, unless software begins servicing receive interrupts at this point, since BDRR is no longer being read and transferred to memory automatically by the ABU. For explanation of how the serial port operates in standard mode when DRR is not being read, refer to section 9.2.6, Serial Port Interface Exception Conditions, on page 9-26. The sequence of events involved in the autobuffering process is summarized as follows: 1) The ABU performs the memory access to the buffer. 2) The appropriate address register is incremented unless the bottom of buffer has been reached, in which case the address register is modified to point to the top of buffer address. 3) Generate an BXINT or BRINT and update XH/RH if the half buffer or bottom of buffer boundary has been crossed. 4) Autodisable the ABU if this function has been selected and if the half buffer or bottom of buffer boundary has been crossed.

9.3.3

System Considerations for BSP Operation

This section discusses several system-level considerations of BSP operation. These considerations include initialization timing issues, software initialization of the ABU, and power down mode operation.

Serial Ports

9-49

Buffered Serial Port (BSP) Interface

9.3.3.1

Timing of Serial Port Initialization

The 54x device utilizes a fully static design, and accordingly, in both the serial port and the BSP, serial port clocks need not be running between transfers or prior to initialization. Therefore, proper operation can still result if FSX/FSR occurs simultaneously with CLKX/CLKR starting. Regardless of whether serial port clocks have been running previously, however, the timing of serial port initialization, and most importantly, when the port is taken out of reset, can be critical for proper serial port operation. The most significant consideration of this is when the port is taken out of reset with respect to when the first frame sync pulse occurs. Initialization timing requirements differ on the serial port and the BSP. On the serial port, the serial port may be taken out of reset at any time with respect to FSX/FSR, however, if XRST/RRST go high during or after the frame sync, the frame sync may be ignored. In standard mode operation on the BSP for receive, and for transmit with external frame sync (TXM = 0), the BSP must be taken out of reset at least two full CLKOUT cycles plus 1/2 serial port clock cycle prior to the edge of the clock which detects the active frame sync pulse (whether the clock has been running previously or not) for proper operation. See Figure 928. Transmit operations with internal clock and frame sync are not subject to this requirement since frame sync is internally generated automatically (after XRST is cleared (set to 1)) when BDXR is loaded. Note, however, that if external serial port clock is used with internal frame sync, frame sync generation may be delayed depending on the timing of clearing XRST with respect to the clock. Figure 928 illustrates the standard mode BSP initialization timing requirements for the transmitter. The figure shows standard mode operation with external frame (TXM = 0) and clock (MCM = 0), active high frame sync (FSP = 0), and data sampled on rising edge (CLKP = 0). In this example, if the BFSX pulse occurs during the first two BCLKXs after the transmit section is taken out of reset, the transmit frame is ignored and BDX is placed in the high impedance state.

9-50

Buffered Serial Port (BSP) Interface

Figure 928. Standard Mode BSP Initialization Timing

BCLKX

BFSX

BDX

1 CLKOUT +1/2 Serial Port clock cycle XRST

In autobuffering mode, for receive, and transmit with external frame sync (TXM = 1), the BSP must be taken out of reset at least six CLKOUT cycles plus 1/2 serial port clock cycle prior to the edge of the clock which detects the active frame sync pulse (whether the clock has been running previously or not) for proper operation. This is due to the time delay for the ABU logic to be activated. See Figure 929. Transmit operations with internal clock and frame sync are not subject to this requirement since frame sync is internally generated automatically after XRST is cleared. Note, however, that if external serial port clock is used with internal frame sync, and if the clock is not running when XRST is cleared, frame sync generation may be delayed depending on the timing of clearing XRST with respect to the clock. Figure 929 illustrates autobuffering mode initialization timing requirements for the transmitter with external clock and frame sync. The figure shows standard mode operation with external frame (TXM = 0) and clock (MCM = 0), active high frame sync (FSP = 0), and data sampled on rising edge (CLKP = 0).

Serial Ports

9-51

Buffered Serial Port (BSP) Interface

Figure 929. Autobuffering Mode Initialization Timing

BCLKX

BFSX

BDX

6 CLKOUT +1/2 Serial Port clock cycle XRST

XRDY

9.3.3.2

Initialization Examples
In order to start or restart BSP operation in standard mode, the same steps are performed in software as with initializing the serial port (see section 9.2, Serial Port Interface, on page 9-4), in addition to which, the BSPCE must be initialized to configure any of the enhanced features desired. To start or restart the BSP in autobuffering mode, a similar set of steps must also be performed, in addition to which, the autobuffering registers must be initialized. As an illustration of the proper operation of a buffered serial port, Example 93 and Example 94 define a sequence of actions. This illustration is based on the use of interrupts to handle the normal I/O between the serial port and CPU. The 545 peripheral configuration has been used as a reference for these examples. The examples illustrate initializing the buffered serial port for autobuffering mode operation. In both cases, assume that transmit and receive interrupts are used to service the ABU interrupts, however, polling of the interrupt flag register (IFR) could also be used. Both the transmit and receive sections can be initialized at the same time or separately depending upon system requirements. Example 93 initializes the serial port for transmit operations only, with burst mode, external frame sync, and external clock selected. The selected data format is 16 bits, with frame sync and clock polarities selected to be high true. Transmit autobuffering is enabled by setting the BXE bit in the ABUC section of BSPCE, and HALTX has been set to 1, which causes transmission to halt when half of the defined buffer is transmitted. Example 94 initializes the serial port for receive operations only, with continuous mode selected. Frame sync and clock polarities are selected to be

9-52

Buffered Serial Port (BSP) Interface

low true, data format is 16 bits, and frame ignore is selected so that two received data bytes are packed into a single received word to minimize memory requirements. Receive autobuffering is enabled by setting the BRE bit in the ABUC section of BSPCE. In Example 93 and Example 94, the transmit and receive interrupts used are those that the BSP occupies on the 542, 543, 545, 546, 548, and 549, the devices that include the BSP. However, on other devices that use the BSP, different interrupts may be used; and therefore, you should consult the appropriate device documentation.

Example 93. BSP Transmit Initialization Routine

Action 1) Reset and initialize the serial port by writing 0008h to BSPC. Description This places both the transmit and receive portions of the serial port in reset and sets up the serial port to operate with externally generated FSX and CLKX signals and FSX required for transmit/receive of each 16-bit word. Eliminate any interrupts that may have occurred before initialization. Enable transmit interrupts. Interrupts must be globally enabled for the CPU to respond.

2) 3) 4)

Clear any pending serial port interrupts by writing 0020h to IFR. Enable the serial port interrupts by ORing 0020h with IMR. Enable interrupts globally (if necessary) by clearing the INTM bit in ST1. Initialize the ABU transmit by writing 1400h to BSPCE. Write the buffer start address to AXR. Write the buffer size to BKX. Start the serial port by writing 0048h to BSPC.

5) 6) 7) 8)

This causes the BSP to stop transmitting at the end of the buffer until another FSX is received. Identify the first buffer address to the ABU. Identify the buffer size to the ABU. This takes the transmit portion of the serial port out of reset and starts operations with the conditions defined in steps 1 and 5.

Serial Ports

9-53

Buffered Serial Port (BSP) Interface

Example 94. BSP Receive Initialization Routine

Action 1) Reset and initialize the serial port by writing 0000h to BSPC. Clear any pending serial port interrupts by writing 0010h to IFR. Enable the serial port interrupts by ORing 0010h with IMR. Enable interrupts globally (if necessary) by clearing the INTM bit in ST1. Initialize the ABU receive by writing 2160h to BSPCE. Write the buffer start address to ARR. Write the buffer size to BKR. Start the serial port by writing 0080h to BSPC. Description This places the receive portion of the serial port in reset and sets up the serial port to operate in continuous receive mode with 16-bit words. Eliminate any interrupts that may have occurred before initialization. Enable receive interrupts. Interrupts must be globally enabled for the CPU to respond.

2) 3) 4)

5) 6) 7) 8)

This causes the BSP to receive continuously and not restart if a new FSR is received. Identify the first buffer address to the ABU. Identify the buffer size to the ABU. This takes the receive portion of the serial port out of reset and starts operations with the conditions defined in steps 1 and 5.

9.3.4

Buffer Misalignment Interrupt (BMINT) 549 only

BMINT is generated when a frame sync occurs and the ABU transmit or receive buffer pointer is not at the top of the the buffer address. This is useful for detecting several potential error conditions on the serial interface, including extraneous and missed clocks and frame sync pulses. A BMINT interrupt, therefore, indicates that one or more words may have been lost on the serial interface. BMINT is useful for detecting buffer misalignment only when the buffer pointer(s) are initially loaded with the top of the buffer address and a frame of data contains the same number of words as the buffer length. These are the only conditions under which a frame sync occurring at a buffer address other than the top of the buffer constitute an error condition. In cases where these conditions are met, a frame sync always occurs when the buffer pointer is at the top of the buffer address (if the interface is functioning properly). If BMINT is enabled under conditions other than those described, interrupts can be generated under circumstances other than actual buffer misalignment. In these cases, BMINT should generally be masked in the IMR register so that the processor ignores this interrupt.

9-54

Buffered Serial Port (BSP) Interface

BMINT is available when the device is operating in the auto-buffering mode with continuous transfers, the FIG bit cleared to 0, and with external serial clocks or frames.

9.3.5

BSP Operation in Power-Down Mode

The 54x offers several power down modes which allow part or all of the device to enter a dormant state and dissipate considerably less power than when running normally. Power down mode may be invoked in several ways, including either executing the IDLE instruction or driving the HOLD input low with the HM status bit set to 1. The BSP, like other peripherals (timer, standard serial port), can take the CPU out of IDLE using the transmit interrupt (BXINT) or receive interrupt (BRINT). When in IDLE or HOLD mode, the BSP continues to operate, as is the case with the serial port. When in IDLE2/3, unlike the serial port and other on-chip peripherals which are stopped with this power-down mode, the BSP can still be operated. In standard mode, if the BSP is using external clock and frame sync while the device is in IDLE2/3, the port will continue to operate, and a transmit interrupt (BXINT) or receive interrupt (BRINT) will take the device out of IDLE2/3 mode if INTM = 0 before the device executes the IDLE 2 or IDLE 3 instruction. With internal clock and/or frame sync, the BSP remains in IDLE2/3 until the CPU resumes operation. In autobuffering mode, if the BSP is using external clock and frame sync while the device is in IDLE2/3, a transmit/receive event will cause the internal BSP clock to be turned on for the cycles required to perform the DXR (or DRR) to memory transfer. The internal BSP clock is then turned off automatically as soon as the transfer is complete so the device will remain in IDLE2/3. The device is awakened from IDLE2/3 by the ABU transmit interrupt (BXINT) or receive interrupt (BRINT) when the transmit/receive buffer has been halfway or entirely emptied or filled if INTM = 0 before the device executes the IDLE 2 or IDLE 3 instruction.

Serial Ports

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Time-Division Multiplexed (TDM) Serial Port Interface

9.4 Time-Division Multiplexed (TDM) Serial Port Interface

The time-division multiplexed (TDM) serial port allows the 54x device to communicate serially with up to seven other devices. The TDM port, therefore, provides a simple and efficient interface for multiprocessing applications. The TDM serial port is a superset of the serial port described in section 9.2 on page 9-4. By means of the TDM bit in the TDM serial port control register (TSPC), the port can be configured in multiprocessing mode (TDM = 1) or stand-alone mode (TDM = 0). When in stand-alone mode, the port operates as described in section 9.2. When in multiprocessing mode, the port operates as described in this section. The port can be shut down for low power consumption via the XRST and RRST bits, as described in section 9.2.

9.4.1

Basic Time-Division Multiplexed Operation

Time-division multiplexing is the division of time intervals into a number of subintervals, with each subinterval representing a communications channel according to a prespecified arrangement. Figure 930 shows a 4-channel TDM scheme. Note that the first time slot is labeled chan 1 (channel 1), the next chan 2 (channel 2), etc. Channel 1 is active during the first communications period and during every fourth period thereafter. The remaining three channels are interleaved in time with channel 1.

Figure 930. Time-Division Multiplexing

Full Interval (frame) Word Transfer Interval chan chan chan chan chan chan chan chan chan chan chan 1 2 3 4 1 2 3 4 1 2 3 0

time

The 54x TDM port uses eight TDM channels. Which device is to transmit and which device or devices is/are to receive for each channel may be independently specified. This results in a high degree of flexibility in interprocessor communications.

9.4.2

TDM Serial Port Interface Registers

The TDM serial port operates through six memory-mapped registers and two other register (TRSR and TXSR) that are not directly accessible to the program, but are used in the implementation of the double-buffering capability. These eight registers are listed in Table 913.

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Time-Division Multiplexed (TDM) Serial Port Interface

Table 913. TDM Serial Port Registers

Address Register TRCV TDXR TSPC TCSR TRTA TRAD TRSR TXSR Description TDM data receive register TDM data transmit register TDM serial port control register TDM channel select register TDM receive/transmit address register TDM receive address register TDM data receive shift register TDM data transmit shift register

See section 8.2, Peripheral Memory-Mapped Registers.

TDM data receive register (TRCV). The 16-bit TDM data receive register (TRCV) holds the incoming TDM serial data. The TRCV has the same function as the DRR, described on page 9-5. TDM data transmit register (TDXR). The 16-bit TDM data transmit register (TDXR) holds the outgoing TDM serial data. The TDXR has the same function as the DXR, described on page 9-5. TDM serial port control register (TSPC). The 16-bit TDM serial port control register (TSPC) contains the mode control and status bits of the TDM serial port interface. The TSPC is identical to the SPC (Figure 93) except that bit 0 serves as the TDM mode enable control bit in the TSPC. The TDM bit configures the port in TDM mode (TDM = 1) or stand-alone mode (TDM = 0). In stand-alone mode, the port operates as a standard serial port as described on page 9-4. TDM channel select register (TCSR). The 16-bit TDM channel select register (TCSR) specifies in which time slot(s) each 54x device is to transmit. TDM receive/transmit address register (TRTA). The 16-bit TDM receive/ transmit address register (TRTA) specifies in the eight LSBs (RA0RA7) the receive address of the 54x device and in the eight MSBs (TA0TA7) the transmit address of the 54x device. TDM receive address register (TRAD). The 16-bit TDM receive address register (TRAD) contains various information regarding the status of the TDM address line (TADD).
Serial Ports
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Time-Division Multiplexed (TDM) Serial Port Interface

TDM data receive shift register (TRSR). The 16-bit TDM data receive shift register (TRSR) controls the storing of the data, from the input pin, to the TRCV. The TRSR has the same function as the RSR, described on page 9-5. TDM data transmit shift register (TXSR). The 16-bit TDM data transmit shift register (TXSR) controls the transfer of the outgoing data from the TDXR and holds the data to be transmitted on the data-transmit (TDX) pin. The TXSR has the same function as the XSR, described on page 9-5.

9.4.3

TDM Serial Port Interface Operation

Figure 931(a) shows the 54x TDM port architecture. Up to eight devices can be placed on the four-wire serial bus. This four-wire bus consists of a conventional serial ports bus of clock, frame, and data (TCLK, TFRM, and TDAT) wires plus an additional wire (TADD) that carries the device addressing information. Note that the TDAT and TADD signals are bidirectional signals and are often driven by different devices on the bus during different time slots within a given frame of operation.

Figure 931. TDM 4-Wire Bus

(a) Device 0 Device 1 Device 7 TFRM TADD TCLK TDAT (b) TDX TDR TFSX TFSR TCLKX TCLKR TFRM TADD TCLK TDAT

54x

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Time-Division Multiplexed (TDM) Serial Port Interface

The TADD line, which is driven by a particular device for a particular time slot, determines which device(s) in the TDM configuration should execute a valid TDM receive during that time slot. This is similar to a valid serial port read operation, as described in section 9.2, Serial Port Interface, on page 9-4 except that some corresponding TDM registers are named differently. The TDM receive register is TRCV, and the TDM receive shift register is TRSR. Data is transmitted on the bidirectional TDAT line. Note that in Figure 931(b) the device TDX and TDR pins are tied together externally to form the TDAT line. Also, note that only one device can drive the data and address line (TDAT and TADD) in a particular slot. All other devices TDAT and TADD outputs should be in the high-impedance state during that slot, which is accomplished through proper programming of the TDM port control registers (this is described in detail later in this section). Meanwhile, in that particular slot, all the devices (including the one driving that slot) sample the TDAT and TADD lines to determine if the current transmission represents valid data to be read by any one of the devices on the bus (this is also discussed in detail later in this section). When a device recognizes an address to which it is supposed to respond, a valid TDM read then occurs, the value is transferred from TRSR to TRCV. A receive interrupt (TRINT) is generated, which indicates that TRCV has valid receive data and can be read. All TDM port operations are synchronized by the TCLK and TFRM signals. Each of them are generated by only one device (typically the same device), referred to as the TCLK and TFRM source(s). The word master is not used here because it implies that one device controls the other, which is not the case, and TCSR must be set to prevent slot contention. Consequently, the remaining devices in the TDM configuration use these signals as inputs. Figure 931(b) shows that TCLKX and TCLKR are externally tied together to form the TCLK line. Also, TFRM and TADD originate from the TFSX and TFSR pins respectively. This is done to make the TDM serial port also easy to use in standard mode. TDM port operation is controlled by six memory-mapped registers. The layout of these registers is shown in Figure 932. The TRCV and TDXR registers have the same functions as the DRR and DXR registers respectively, described in section 9.2, Serial Port Interface. The TSPC is identical to the SPC except that bit 0 serves as the TDM mode enable control bit in the TSPC. This bit configures the port in TDM mode (TDM = 1) or stand-alone mode (TDM = 0). In stand-alone mode, the port operates as a standard serial port as described in section 9.2. Refer to section 9.4.6, Examples of TDM Serial Port Interface Operation, on page 9-64 for additional information about the function of the bits in these registers.
Serial Ports
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Time-Division Multiplexed (TDM) Serial Port Interface

Figure 932. TDM Serial Port Registers Diagram

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRCV TDXR TSPC Receive Data Transmit Data IN0 X Free X Soft X X X X X XRDY RRDY X X IN1 X RRST XRST TXM MCM CH7 RA7 A7 CH6 RA6 A6 CH5 RA5 A5 CH4 RA4 A4 X 0 0 TDM TCSR TRTA CH3 RA3 A3 CH2 CH1 CH0 RA2 A2 RA1 A1 RA0 A0 TA7 X TA6 X TA5 X2 TA4 X1 TA3 X0 TA2 S2 TA1 S1 TA0 S0 TRAD Note: X=Dont care.

When TDM mode is selected, the DLB and FO bits in the TSPC are hard-configured to 0, resulting in no access to the digital loopback mode and in a fixed word length of 16 bits (a different type of loopback is discussed in the example in section 9.4.6 on page 9-64). Also, the value of FSM does not affect the port when TDM = 1, and the states of the underflow and overrun flags are indeterminate (section 9.4.5, TDM Serial Port Interface Exception Conditions, on page 9-64 explains how exceptions are handled in TDM mode). If TDM = 1, changes made to the contents of the TSPC become effective upon completion of channel 7 of the current frame. Thus the TSPC value cannot be changed for the current frame; any changes made will take effect in the next frame.

The source device for the TCLK and TFRM timing signals is set by the MCM and TXM bits, respectively. The TCLK source device is identified by setting the MCM bit of its TSPC to 1. Typically, this device is the same one that supplies the TDM port clock signal TCLK. The TCLKX pin is configured as an input if MCM = 0 and an output if MCM = 1. In the latter case (internal 54x clock), the device whose MCM = 1 supplies the clock (TCLK frequency = one fourth of CLKOUT frequency) for all devices on the TDM bus. The clock can be supplied by an external source if MCM = 0 for all devices. TFRM can also be supplied externally if TXM = 0. An external TFRM, however, must meet TDM receive timing specifications with respect to TCLK for proper operation. No more than one device should have MCM or TXM set to 1 at any given time. The specification of which device is to supply clock and framing signals is typically made only once, during system initialization. The TDM channel select register (TCSR) of a given device specifies in which time slot(s) that device is to transmit. A 1 in any one or more of bits 07 of the TCSR sets the transmitter active during the corresponding time slot. Again, a key system-level constraint is that no more than one device can transmit during the same time slot; devices do not check for bus contention, and slots
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Time-Division Multiplexed (TDM) Serial Port Interface

must be consistently assigned. As in TSPC operation, a write to TCSR during a particular frame is valid only during the next frame. However, a given device can transmit in more than one slot. This is discussed in more detail in section 9.4.4, TDM Mode Transmit and Receive Operations, on page 9-62 with an emphasis on the utilization of TRTA, TDXR, and TCSR in this respect. The TDM receive/transmit address register (TRTA) of a given device specifies two key pieces of information. The lower half specifies the receive address of the device, while the upper half of TRTA specifies the transmit address. The receive address (RA7RA0, refer to Figure 932) is the 8-bit value that a device compares to the 8-bit value it samples on the TADD line in a particular slot to determine whether it should execute a valid TDM receive. The receive address, therefore, establishes the slots in which that device may receive, dependent on the addresses present in those slots, as specified by the transmitting devices. This process occurs on each device during every slot. The transmit address (TA7TA0, refer to Figure 932) is the address that the device drives on the TADD line during a transmit operation on an assigned slot. The transmit address establishes which receiving devices may execute a valid TDM receive on the driven data. Only one device at a time can drive a transmit address on TADD. Each processor bit-wise-logically-ANDs the value it samples on the TADD line with its receive address (RA7RA0). If this operation results in a nonzero value, then a valid TDM receive is executed on the processor(s) whose receive addresses match the transmitted address. Thus, for one device to transmit to another, there must be at least one bit in the upper half of the transmitting devices TRTA (the transmit address) with a value of 1 that matches one bit with a value of 1 in the lower half of TRTA (the receive address) of the receiving device. This method of configuration of TRTA allows one device to transmit to one or more devices, and for any one device to receive from one or more than one transmitter. This can also allow the transmitting device to control which devices receive, without the receive address on any of the devices having to be changed. The TDM receive address register (TRAD) contains various information regarding the status of the TADD line which can be polled to verify the previous values of this signal and to verify the relationship between instruction cycles and TDM port timing. Bits 1311 (X2X0) contain the current slot number value, regardless of whether a valid data receive was executed in that slot or not. This value is latched at the beginning of the slot and retained only until the end of the slot.
Serial Ports
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Time-Division Multiplexed (TDM) Serial Port Interface

Bits 108 (S02S0) hold the number of the last slot plus one (modulo eight) in which data was received (that is, if the last valid data read occurred in slot 5 in the previous frame, these bits would contain the number six). This value is latched during the TDM receive interrupt (TRINT) at the end of the slot in which the last valid data receive occurred, and maintained until the end of the next slot in which a valid receive occurs. Bits 70 (A7A0) hold the last address sampled on the TADD line, regardless of whether a valid data receive was executed or not. This value is latched halfway through each slot (so the value on the TADD may be shifted in) and maintained until halfway through the next slot, whether a valid receive is executed or not.

9.4.4

TDM Mode Transmit and Receive Operations

Figure 933 shows the timing for TDM port transfers. The TCLK and TFRM signals are generated by the timing source device. The TCLK frequency is one fourth the frequency of CLKOUT if generated by a 54x device. The TFRM pulse occurs every 128 TCLK cycles and is timed to coincide with bit 0 of slot 7, which is the last bit of the previous frame. The relationship of TFRM and TCLK allows 16 data bits for each of eight time slots to be driven on the TDAT line, which also permits the processor to execute a maximum of 64 instructions during each slot, assuming that a 54x internal clock is used. Beginning with slot 0 and with the MSB first, the transmitter drives 16 data bits for each slot, with each bit having a duration of one TCLK cycle, with the exception of the first bit of each slot, which lasts only half of one bit time. Note that data is both clocked onto the TDAT line by the transmitting device and sampled from the TDAT line by receiving devices on the rising edge of TCLK (see the data sheet for detailed TDM interface timings).

Figure 933. Serial Port Timing (TDM Mode)

TCLK TDAT TADD TFRM
bit 17 bit 07 bit 150 a00 bit 140 a10 bit 130 a20 bit 80 bit 70 bit 00 a70 bit 151 bit 141 a01 a11

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Time-Division Multiplexed (TDM) Serial Port Interface

Simultaneous with data transfer, the transmitting device also drives the TADD line with the transmit address for each slot. This information, unlike that on TDAT, is only one byte long and is transmitted with the LSB first for the first half of the slot. During the second half of the slot (that is, the last eight TCLK periods) the TADD line is driven high. The TDM receive logic samples the TADD line only for the first eight TCLK periods, ignoring it during the second half of the slot. Therefore, the transmitting device (if not a 54x) could drive TADD high or low during that time period. Note that, like TDAT, the first TADD bit transmitted lasts for only one half of one TCLK cycle. If no device on the TDM bus is configured to transmit in a slot (that is, none of the devices has a 1 for the corresponding slot in their TCSR), that slot is considered empty. In an empty slot, both TADD and TDAT are high impedance. This condition has the potential for spurious receives, however, because TDAT and TADD are always sampled, and a device performs a valid TDM reception if its receive address matches the address on the TADD line. To avoid spurious reads, a 1-kilohm pull-down resistor must be tied to the TADD line. This causes the TADD line to read low on empty slots. Otherwise, any noise on the TADD line that happens to match a particular receive address would result in a spurious read. If power dissipation is a concern and the resistor is not desired, then an arbitrary processor with transmit address equal to 0h can drive empty slots by writing to TDXR in those slots. Slot manipulation is explained later in this section. The 1-kilohm resistor is not required on the TDAT line. An empty TDM slot can result in the following cases: the first obvious case, as mentioned above, occurs when no device has its TCSR configured to transmit in that slot. A second more subtle case occurs when TDXR has not been loaded before a transmit slot in a particular frame. This may also happen when the TCSR contents are changed, since the actual TCSR contents are not updated until the next TFRM pulse occurs. Therefore, any subsequent change takes effect only in the next frame. The same is true for the receive address (the lower half of TRTA). The transmit address (upper half of TRTA), however, and TDXR, clearly, may be changed within the current frame for a particular slot, assuming that the slot has not yet been reached when the instruction to load the TRTA or TDXR is executed. Note that it is not necessary to load the transmit address each time TDXR is loaded; when a TDXR load occurs and a transmission begins, the current transmit address in TRTA is transmitted on TADD. The current slot number may be obtained by reading the X2X0 bits in TRAD. This affords the flexibility of reconfiguring the TDM port on a slot-by-slot basis, and even slot sharing if desired. The key to utilizing this capability is to understand the timing relationship between the instructions being executed and the frame/slots of the TDM port. If the TDM port is to be manipulated on a slot-bySerial Ports
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Time-Division Multiplexed (TDM) Serial Port Interface

slot basis, changes must be made to appropriate registers quickly enough for the desired effect to take place at the desired time. It is also important to take into account that the TCSR and the receive address (lower half of TRTA) take effect only at the start of a new frame, while the transmit address (upper half of TRTA) and TDXR (transmit data) can take effect at the start of a new slot, as mentioned previously. Note that if the transmit address is being changed on the fly, care should be exercised not to corrupt the receive address, since both addresses are located in the TRTA, thus maintaining the convention of allowing the transmitting device to specify which devices can receive.

9.4.5

TDM Serial Port Interface Exception Conditions

Because of the nature of the TDM architecture, with the ability for one processor to transmit in multiple slots, the concepts of overrun and underflow become indeterminate. Therefore, the overrun and underflow flags are not active in TDM mode. In the receiver, if TRCV has not been read and a valid receive operation is initiated (because of the value on TADD and the devices receive address), the present value of TRCV is overwritten; the receiver is not halted. On the other hand, if TDXR has not been updated before a transmission, the TADD or TDAT lines are not driven, and these pins remain in the high-impedance state. This mode of operation prevents spurious transmits from occurring. If a TFRM pulse occurs at an improper time during a frame, the TDM port is not able to continue functioning properly, since slot and bit numbers become ambiguous when this occurs. Therefore, only one TFRM should occur every 128 TCLK cycles. Unlike the serial port, the TDM port cannot be reinitialized with a frame sync pulse during transmission. To correct an improperly timed TFRM pulse, the TDM port must be reset.

9.4.6

Examples of TDM Serial Port Interface Operation

The following is an example of TDM serial port operation, showing the contents of some of the key device registers involved, and explaining the effect of this configuration on port operation. In this example, eight devices are connected to the TDM serial port as shown in Figure 934. Table 914 shows the TADD value during each of the eight channels given the transmitter and receiver designations shown. This example shows the configuration for eight devices to communicate with each other. In this example, device 0 broadcasts to all other device addresses during slot 0. In subsequent time slots, devices 17 each communicate to one other processor.

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Time-Division Multiplexed (TDM) Serial Port Interface

Figure 934. TDM Example Configuration Diagram

Device 0 Channel 0 (TCSR=01h) TA = FEh, RA = 01h Device 1 Channel 7 (TCSR=80h) TA = 01h, RA = 04h Device 2 Channel 6 (TCSR=40h) TA = 02h, RA = 04h Device 3 Channel 5 (TCSR=20h) TA = 04h, RA = 08h

TFRM TADD TCLK TDAT

Device 4 Channel 4 (TCSR=10h) TA = 08h, RA = 10h

Device 5 Channel 3 (TCSR= 08h) TA = 10h, RA = 20h

Device 6 Channel 2 (TCSR= 04h) TA = 20h, RA = 40h

Device 7 Channel 1 (TCSR= 02h) TA = 40h, RA = 80h

Table 914. Interprocessor Communications Scenario

Channel 0 1 2 3 4 5 6 7 TADD Data FEh 40h 20h 10h 08h 04h 02h 01h Transmitter Device 0 7 6 5 4 3 2 1 Receiver Device(s) 17 6 5 4 3 2 1 0

Table 915 shows the TDM serial port register contents of each device that results in the scenario given in Table 914. Device 0 provides the clock and frame control signals for all channels and devices. The TCSR and TRTA contents specify which device is to transmit on a given channel and which devices are to receive.
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Table 915. TDM Register Contents

Device 0 1 2 3 4 5 6 7 TSPC xxF9h xxC9h xxC9h xxC9h xxC9h xxC9h xxC9h xxC9h TRTA FE01h 0102h 0204h 0408h 0810h 1020h 2040h 4080h TCSR xx01h xx80h xx40h xx20h xx10h xx08h xx04h xx02h

In this example, the transmit address of a given device (the upper byte of TRTA) matches the receive address (the lower byte of TRTA) of the receiving device. Note, however, that it is not necessary for the transmit and receive addresses to match exactly; the matching operation implemented in the receiver is a bitwise AND operation. Thus, it is only necessary that one bit in the field matches for a receive to occur. The advantage of this scheme is that a transmitting device can select the device or devices to receive its transmitted data by simply changing its transmit address (as long as each devices receive address is unique, the receive address of the receiving device does not need to be changed). In the example, device 0 can transmit to any combination of the other devices by merely writing to the upper byte of TRTA. Therefore, if a transmitting device changed its TRTA to 8001h on the fly, it would transmit only to device 7. A device may also transmit to itself, because both the transmit and receive operations are executed on the rising edge of TCLK (see the 54x data sheet for TDM interface timings). To enable this type of loopback, it is necessary to use the standard TDM port interface connections as shown in Figure 931. Then, if device 0 has a TRTA of 0101h, it would transmit only to itself. As an illustration of the proper operation of a TDM serial port, Example 95 through Example 98 define a sequence of actions. This illustration is based on the use of interrupts to handle the normal I/O between the serial port and CPU. The 542 peripheral configuration has been used as a reference for these examples. In Example 95 the procedure for a one-way transmit of a sequence of values from device 0 to device 1 is shown. Device 0 transmits in slot 0 and has a transmit address of 01h. Example 97 shows the procedure for device 1. It has a receive address of 01h.
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Example 95. TDM Serial Port Transmit Initialization Routine

Action 1) Reset and initialize the TDM serial port by writing 0039h to TSPC. Clear any pending TDM serial port transmit interrupts by writing 0080h to IFR. Enable the TDM serial port interrupts by ORing 0080h with IMR. Enable interrupts globally (if necessary) by clearing the INTM bit in ST1. Write 0001h to TCSR. Write 0100h to TRTA. Start the serial port by writing 0049h to TSPC. Perform a handshake to verify that the receiving device is ready to receive data. Write the first data value to TDXR (if not already done in step 8). Description This places both the transmit and receive portions of the TDM serial port in reset and sets up the serial port to operate with internally generated TFRM and TCLK signals in TDM mode. Eliminate any interrupts that may have occurred before initialization.

2)

3) 4)

Enable transmit interrupts. Interrupts must be globally enabled for the CPU to respond.

5) 6) 7) 8)

This selects time slot 0 as the transmission time slot for this device. This sets up this device to transmit data to the device receiving at address 01h. It also sets up this device to ignore all received data. This takes the transmit portion of the serial port out of reset and starts operations with the conditions defined in steps 1, 5 and 6. For a single device pair, this could make use of BIO and XF. For several devices this might mean that the device generating TFRM and TCLK broadcasts a command to all other devices until each one returns an acknowledge. This initiates serial port transmit operations since TADD and TDAT are not driven if new data is not written to TDXR.

9)

Example 96. TDM Serial Port Transmit Interrupt Service Routine

Action 1) 2) Save any context that may be modified on the stack. Write TDXR with a new value from a predetermined location in memory. Restore the context that was saved in step 1. Return from the ISR with an RETE to reenable interrupts. Description The operating context of the interrupted code must be maintained. Write the new transmit data for the ISR.

3) 4)

The operating context of the interrupted code must be maintained. Interrupts must be reenabled for the CPU to respond to the next interrupt.

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Example 97. TDM Serial Port Receive Initialization Routine

Action 1) Reset and initialize the TDM serial port by writing 0009h to TSPC. Clear any pending TDM serial port receive interrupts by writing 0040h to IFR. Enable the TDM serial port interrupts by ORing 0040h with IMR. Enable interrupts globally (if necessary) by clearing the INTM bit in ST1. Write 0000h to TCSR. Write 0001h to TRTA. Perform a handshake to notify the transmitting device that it is okay to send data. Description This places both the transmit and receive portions of the TDM serial port in reset and sets up the serial port to operate with externally generated TFRM and TCLK signals in TDM mode. Eliminate any interrupts that may have occurred before initialization.

2)

3) 4)

Enable receive interrupts. Interrupts must be globally enabled for the CPU to respond.

5) 6) 7)

This sets up this device to not transmit in any time slot. This sets up this device to not address any device. It also sets up this device to receive data sent to address 01h. For a single device pair, this could make use of BIO and XF. For several devices, this might mean that the device waits for a broadcast command and then returns an acknowledge.

Example 98. TDM Serial Port Receive Interrupt Service Routine

Action 1) 2) Save any context that may be modified on the stack. Read TDRR and write the value to a predetermined location in memory. Restore the context that was saved in step 1. Return from the ISR with an RETE to reenable interrupts. Description The operating context of the interrupted code must be maintained. Read the new received data for the ISR.

3) 4)

The operating context of the interrupted code must be maintained. Interrupts must be reenabled for the CPU to respond to the next interrupt.

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Chapter 10

External Bus Operation

This chapter describes the external bus operation and control for memory and I/O accesses. Some of the external bus operation and control features of the 54x include software wait states, bank-switching logic, and hold logic. The 54x supports a wide range of system interfacing requirements. The 5410 enhanced external parallel interface (XIO) is not described in this chapter. See the 5410 datasheet for details about the external memory interface.

Topic

Page

10.1 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 External Bus Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.3 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.4 External Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.5 Start-Up Access Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.6 Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

10-1

External Bus Interface

10.1 External Bus Interface

The 54x external interface consists of data buses, address buses, and a set of control signals for accessing off-chip memory and I/O ports. Table 101 lists key signals for the external interface.

Table 101. Key External Interface Signals

541 542, 543, 545, 546 150 150 548, 549 5410 220 150 5402 190 150 5420 Description 170 150 Address bus Data bus External memory access strobe Program space select Data space select I/O access strobe I/O space select Read/write signal Data ready to complete cycle Hold request Hold acknowledge Micro state complete Instruction acquisition Interrupt acknowledge

Signal Name A0A15 D0D15 MSTRB PS DS IOSTRB IS R/W READY HOLD HOLDA MSC IAQ IACK

n n n n n n n n n n n n

n n n n n n n n n n n n

n n n n n n n n n n n n

n n n n n n n

The parallel interface consists of two mutually-exclusive interfaces controlled by the MSTRB and IOSTRB signals. MSTRB is activated for memory accesses (program or data), and IOSTRB is used to access I/O ports. The R/W signal controls the direction of the accesses. The external ready input signal (READY) and the software-generated wait states allow the processor to interface with memory and I/O devices of varying speeds. When communicating with slower devices, the CPU waits until the other device completes its function and sends the READY signal to continue execution.
10-2

External Bus Interface

In some cases, wait states are needed only when transitions are made between two external memory devices. The programmable bank-switching logic provides automatic insertion of a wait state in these situations. The hold mode allows an external device to take control of the 54x external buses to access the resources in the 54x external program, data, and I/O memory spaces. Two hold mode types, normal mode and concurrent DMA mode are available. When the CPU addresses internal memory, the data bus is placed in the highimpedance state. However, the address bus and the memory-select signals (program select (PS), data select (DS), and I/O select (IS)) maintain the previous state. The MSTRB, IOSTRB, R/W, IAQ, and MSC signals remain inactive. If the address visibility mode (AVIS) bit, located in the PMST, is set to 1, the internal program address is placed on the address bus with an active IAQ. When the CPU addresses external data or I/O space, the extended address lines are driven to logic 0. This is also the case when the CPU addresses internal memory with the AVIS (address visibility) set to 1.

External Bus Operation

10-3

External Bus Priority

10.2 External Bus Priority

The 54x CPU has one program bus (PB), three data buses (CB, DB, and EB), and four address buses (PAB, CAB, DAB, and EAB). The CPU can access its buses simultaneously because of its pipelined structure; however, the external interface can support only one access per cycle. A pipeline conflict occurs if, in a single cycle, the CPU accesses external memory twice to fetch an instruction, a data-memory operand, or an external I/O device. This pipeline conflict is automatically resolved by a predetermined priority, defined by the stage of the pipeline. Figure 101 shows multiple CPU accesses to fetch an instruction, and to write and read data operands over the external interface in one cycle. Data accesses have a higher priority than program-memory fetches: the programmemory fetch cannot begin until all CPU data accesses are completed.

Figure 101. External Bus Interface Priority

CLKOUT PB Fetch CB/DB Reads EB Write A(22 0)

D(15 0)

Write

Read

Read

Fetch

Pipeline conflicts occur when the program and data are in external memory and a single-operand write instruction is followed by a dual-operand read or a 32-bit operand read. The following sequence of instructions shows the pipeline conflict discussed.
ST T,*AR6 LD *AR4+,A ||MAC *AR5+, B ;Smem write operation ;Xmem and Ymem read operation

Chapter 7, Pipeline, describes pipeline operation and conflicts in detail.

10-4

External Bus Control

10.3 External Bus Control

Two units in the 54x control the external bus: the wait-state generator and the bank-switching logic. These units are controlled by two registers, the software wait-state register (SWWSR) and the bank-switching control register (BSCR).

10.3.1 Wait-State Generator

The software-programmable wait-state generator can extend external bus cycles by up to seven machine cycles (14 machine cycles on 549, 5402, 5410 and 5420 devices), providing a convenient means to interface the 54x to slower external devices. Devices that require more than seven wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are shut off. Shutting off these paths from the internal clocks allows the device to run with lower power consumption. The software-programmable wait-state generator is controlled by the 16-bit software wait-state register (SWWSR), which is memory-mapped to address 0028h in data space. The program and data spaces each consist of two 32K-word blocks; the I/O space consists of one 64K-word block. Each of these blocks has a corresponding 3-bit field in the SWWSR. These fields are shown in Figure 102 and described in Table 102. The SWWSR bit fields of the 548, 549, 5402, 5410, and 5420 are described in Table 103. The value of a 3-bit field in SWWSR specifies the number of wait states to be inserted for each access in the corresponding space and address range. The minimum value, which adds no wait states, is 0 (000b). A value of 7 (111b) provides the maximum number of wait states.

Figure 102. Software Wait-State Register (SWWSR) Diagram

15 Reserved/XPA
R

1412 I/O
R/W

119 Data
R/W

86 Data
R/W

53 Program
R/W

20 Program
R/W

XPA bit on 548, 549, 5402, 5410, and 5420 only

External Bus Operation

10-5

External Bus Control

Table 102. Software Wait-State Register (SWWSR) Bit Summary

Bit 15 1412 119 86 53 20 Name Reserved I/O Data Data Program Program Reset Value 0 1 1 1 1 1 Function Reserved. In the 548, and 549, this bit changes the operation of the program fields (see Table 103). I/O space. The field value (07) corresponds to the number of wait states for I/O space 0000FFFFh. Data space. The field value (07) corresponds to the number of wait states for data space 8000FFFFh. Data space. The field value (07) corresponds to the number of wait states for data space 00007FFFh. Program space. The field value (07) corresponds to the number of wait states for program space 8000FFFFh. Program space. The field value (07) corresponds to the number of wait states for program space 00007FFFh.

Figure 103. Software Wait-State Control Register (SWCR) Diagram

15 XSWWR Reserved 1 SWSM 0

When SWWSM is set to 1, the wait states are multiplied by two extending the maximum number of wait states from 7 to 14. The 549, 5402, 5410, and 5420 have an extra bit (software wait-state multiplier, SWSM) that resides in SWCR, which is memory mapped to address 002Bh in data space.

10-6

External Bus Control

Table 103. 548/549/5402/5410/5420 Software Wait-State Register (SWWSR) Bit Summary

Bit 15 1412 119 86 53 Name XPA I/O Data Data Program Reset Value 0 1 1 1 1 Function Extended program address control. Selects the address ranges selected by the program fields. I/O space. The field value (07) corresponds to the number of wait states for I/O space 0000FFFFh. Data space. The field value (07) corresponds to the number of wait states for data space 8000FFFFh. Data space. The field value (07) corresponds to the number of wait states for data space 00007FFFh. Program space. The field value (07) corresponds to the number of wait states for:

20 Program 1

XPA = 0: xx8000 xxFFFFh XPA = 1: 400000h7FFFFF

Program space. The field value (07) corresponds to the number of wait states for:

XPA = 0: xx0000xx7FFFh XPA = 1: 0000003FFFFFh

Figure 104 is a block diagram of the wait-state generator logic for external program space. When an external program access is decoded, the appropriate field of the SWWSR is loaded into the counter. If the field is not 000, a not-ready signal is sent to the CPU and the wait-state counter is started. The not-ready condition is maintained until the counter decrements to 0 and the external READY line is set high. The external READY and the wait-state READY are ORed together to generate the CPU WAIT signal. The READY line is machine-sampled at the falling edge of CLKOUT. The processor detects READY only if a minimum of two software wait states are programmed. The external READY line is not sampled until the last wait-state cycle.

External Bus Operation

10-7

External Bus Control

Figure 104. Software Wait-State Generator Block Diagram

SWWSR PSEL CPU A15 A G 1-to-2 decoder Y0 Y1 53 20 External logic CYCLE 3-bit counter

WAIT

READY

At reset, all fields in the SWWSR are set to 111b (SWWSR = 7FFFh), the maximum number of wait states for external accesses. This feature ensures that the CPU can communicate with slow external memories during processor initialization.

Table 104. Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States
Number of CLKOUT1 Cycles Hardware Wait State Number of Wait States 0 1 2 3 Read NA NA 3 4 Write NA NA 4n 5n Software Wait State Read 1 2 3 4 Write 2n 3n 4n 5n

Where n is the number of consecutive write cycles.

10.3.2 Bank-Switching Logic

Programmable bank-switching logic allows the 54x to switch between external memory banks without requiring external wait states for memories that need several cycles to turn off. The bank-switching logic automatically inserts one cycle when accesses cross memory-bank boundaries inside program or data space. Bank switching is defined by the bank-switching control register (BSCR), which is memory-mapped at address 0029h. Figure 105 shows the BSCR
10-8

External Bus Control

and its fields are described in Table 105. For more information about bankswitching logic, see the device-specific datasheet.

Figure 105. Bank-Switching Control Register (BSCR) Diagram

1512 BNKCMP
R/W

11 PS DS
R/W

109 Reserved

8 IPIRQ
R/W

73 Reserved

2 HBH
R/W

1 BH
R/W

0 EXIO
R/W

Table 105. Bank-Switching Control Register (BSCR) Bit Summary

Bit 1512 Name BNKCMP Reset Value Function Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 1215) are compared, resulting in a bank size of 4K words. Bank sizes from 4K words to 64K words are allowed. Table 106 on page 10-11 shows the relationship between BNKCMP and the address range. Program readdata read access. Inserts an extra cycle between consecutive accesses of program read and data read, or data read and program read. PSDS = 0 PSDS = 1 109 8 73 2 Reserved IPIRQ Reserved HBH No extra cycles are inserted by this feature except when banks are crossed. One extra cycle is inserted between consecutive accesses of program read and data read, or data read and program read.

11

PSDS

These bits are reserved. Interprocessor interrupt request bit. These bits are reserved. HPI bus holder bit.

External Bus Operation

10-9

External Bus Control

Table 105. Bank-Switching Control Register (BSCR) Bit Summary (Continued)

Bit 1 Name BH Reset Value 0 Function Bus holder. Controls the bus holder: BH = 0 BH = 1 0 EXIO 0 The bus holder is disabled. The bus holder is enabled. The data bus, D(150), is held in the previous logic level.

External bus interface off. The EXIO bit controls the external-bus-off function. EXIO = 0 EXIO = 1 The external-bus-off function is disabled. The external-bus-off function is enabled. The address bus, data bus, and control signals become inactive after completing the current bus cycle. Table 107 on page 10-11 lists the state of the signals when the external bus interface is disabled. The DROM, MP/MC, and OVLY bits in PMST and the HM bit in ST1 cannot be modified.

10-10

External Bus Control

Table 106 summarizes the relationship between BNKCMP, the address bits to be compared, and the bank size. BNKCMP values not listed in the table are not allowed. Table 107 lists the state of the ports when the external bus interface is disabled (EXIO = 1).

Table 106. Relationship Between BNKCMP and Bank Size

BNKCMP Bit 15 0 1 1 1 1 Bit 14 0 0 1 1 1 Bit 13 0 0 0 1 1 Bit 12 0 0 0 0 1 MSBs to Compare None 15 1514 1513 1512 Bank Size (16-Bit Words) 64K 32K 16K 8K 4K

Table 107. State of Signals When External Bus Interface is Disabled (EXIO = 1)
Signal A(220) D(150) PS, DS, IS MSTRB, IOSTRB State Previous state High impedance High level High level Signal R/W MSC IAQ State High level High level High level

The EXIO and BH bits control the use of the external address and data buses. These bits should be set to 0 for normal operation. To reduce power dissipation, especially if external memory is never or only infrequently accessed, EXIO and BH can be set to 1. When the EXIO bit in BSCR is set to 1, the CPU cannot modify the the HM bit in ST1 and cannot modify the memory map by changing the value of the DROM, MP/MC, and OVLY bits in PMST.

External Bus Operation

10-11

External Bus Control

The 54x has an internal register that contains the MSBs (as defined by the BNKCMP field) of the last address used for a read or write operation in program or data space. If the MSBs of the address used for the current read do not match those contained in this internal register, the MSTRB (memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSBs for the read of the current address. If the MSBs of the address used for the current read match the bits in the register, a normal read cycle occurs. If repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. An extra cycle is inserted only if a read memory access is followed by another read memory access. This feature can be disabled by clearing BNKCMP to 0. The 54x bank-switching mechanism automatically inserts one extra cycle in the following cases:

A program-memory read followed by another program-memory or datamemory read from a different memory bank. A program-memory read followed by a data-memory read when the PSDS bit is set to 1. A program-memory read followed by another program-memory read from a different page (with the 548, 549, 5402, and 5420). A data-memory read followed by another program-memory or datamemory read from a different memory bank. A data-memory read followed by a program-memory read when the PSDS bit is set to 1.

Figure 106 illustrates the addition of an inactive cycle when memory banks are switched.

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External Bus Control

Figure 106. Bank Switching Between Memory Reads

CLKOUT

Address

Data

Read

Read

Read

R/W

PS or DS

MSTRB

Extra cycle

Figure 107 illustrates the insertion of the extra cycle between a consecutive program read and a data read.

Figure 107. Bank Switching Between Program Space and Data Space
CLKOUT

Address

Data

Read

Read

Read

R/W

PS

DS

MSTRB

Extra cycle

External Bus Operation

10-13

External Bus Interface Timing

10.4 External Bus Interface Timing

All external bus accesses complete in an integral number of CLKOUT cycles. One CLKOUT cycle is defined as the time from one falling edge to the next falling edge of CLKOUT. Some external bus accesses with no wait states, for example, memory writes, or I/O writes and I/O reads, take two cycles. Memory reads take one cycle; however, if a memory read follows a memory write, or vice versa, the memory read takes an additional half-cycle. The following sections discuss zero wait-state accesses, unless otherwise specified.

10.4.1 Memory Access Timing

The MSTRB signal is low for the active portion of reads and writes; an active portion of a memory access lasts (at least) one CLKOUT cycle. In addition, a transition CLKOUT cycle occurs before and after the active portion for writes. During this transition cycle:

MSTRB is high. R/W changes on CLKOUTs rising edge when required. The address changes on CLKOUTs rising edge in the following cases. In all other instances, the address changes on the CLKOUT falling edge.

J J J J

The previous CLKOUT cycle was the active portion of a memory write. A memory read is followed by a memory write. A memory read is followed by an I/O write. A memory read is followed by an I/O read.

PS, DS, or IS changes, if necessary, when the address changes.

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External Bus Interface Timing

Figure 108 shows a read-read-write sequence with MSTRB active and no wait states. The data is read as late in the cycle as possible to allow for maximum access time from a valid address. Although the external writes take two cycles, internally they require only one cycle if no accesses to the external interface are in progress. This helps maintain processing throughput at the maximum level possible. The timing diagram illustrates these concepts:

Back-to-back reads from the same bank are single-cycle accesses. MSTRB stays low during back-to-back reads. MSTRB goes high for one cycle during read-to-write transitions to frame the address and R/W signal changes.

Figure 108. Memory Interface Operation for Read-Read-Write

CLKOUT

Address

Data

Read

Read

Write data

R/W

PS

DS

MSTRB

External Bus Operation

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External Bus Interface Timing

Figure 109 shows a write-write-read sequence with MSTRB active and no wait states. The address and data written are held valid approximately one half-cycle after MSTRB changes. The timing diagram illustrates these concepts:

MSTRB goes high at the end of every write cycle to disable the memory while the address and/or R/W signal changes. Each write takes two cycles. A read following a write takes two cycles.

Figure 109. Memory Interface Operation for Write-Write-Read

CLKOUT Address Data R/W DS, PS IS MSTRB Assuming that an I/O write preceded the first memory write Write data Write data Read

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External Bus Interface Timing

Figure 1010 shows a read-read-write sequence using MSTRB active and one wait state. Because the reads are normally one cycle, they are extended by one additional cycle for the wait state. However, the write, which is already two cycles, is extended to three cycles.

Figure 1010. Memory Interface Operation for Read-Read-Write (Program-Space Wait States)
CLKOUT

Address

Data

Read

Read

Write data

R/W

PS

DS

MSTRB

Wait state

Wait state

Wait state

External Bus Operation

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External Bus Interface Timing

10.4.2 I/O Access Timing

In I/O accesses, the active portion of reads and writes lasts two cycles (with no wait states). Otherwise, the timing for these accesses is the same as for memory accesses. During these cycles, the address changes on the falling edge of CLKOUT, except for a memory access to I/O access sequence. IOSTRB is low from one rising edge to the next rising edge of the CLKOUT cycle. Figure 1011 shows a read-write-read sequence for IOSTRB with no wait states. For IOSTRB accesses, reads and writes require a minimum of two cycles. Some off-chip peripherals can change their status bits during reads or writes; therefore, it is important that addresses remain valid when communicating with those peripherals. For reads and writes with IOSTRB active, IOSTRB is completely framed by the address to meet this requirement. The timing diagram illustrates these concepts:

Each I/O access takes two cycles. IOSTRB goes high at the end of each access to frame address and R/W signal changes.

Figure 1011. Parallel I/O Interface Operation for ReadWriteRead

CLKOUT

Address

Data

I/O read

I/O write

I/O read

R/W

IS

IOSTRB

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External Bus Interface Timing

Figure 1012 shows the same I/O space access with one wait-state access. Each read and write access is extended by an additional cycle.

Figure 1012. Parallel I/O Operation for Read-Write-Read (I/O-Space Wait States)
CLKOUT

Address I/O read Data I/O write I/O read

R/W

IS

IOSTRB

Wait state

Wait state

Wait state

10.4.3

Memory and I/O Access Timing

Figure 1013 through Figure 1020 show the various transitions between memory reads and writes, and I/O reads and writes over the external interface bus. The timing diagrams illustrate these concepts:
- I/O reads and writes take at least three cycles when they follow a memory

read or write.
- Memory reads take two cycles when they follow an I/O read or write.

External Bus Operation

10-19

External Bus Interface Timing

Figure 1013. Memory Read and I/O Write

CLKOUT

Address

Data

Read

I/O write

R/W

PS

IS

MSTRB

IOSTRB

Figure 1014. Memory Read and I/O Read

CLKOUT

Address I/O read Data Read

R/W

PS

IS

MSTRB

IOSTRB

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External Bus Interface Timing

Figure 1015. Memory Write and I/O Write

CLKOUT

Address

Data

Write data

I/O Write

R/W

PS

IS

MSTRB

IOSTRB

Figure 1016. Memory Write and I/O Read

CLKOUT

Address I/O read Data Write data

R/W

PS

IS

MSTRB

IOSTRB

External Bus Operation

10-21

External Bus Interface Timing

Figure 1017. I/O Write and Memory Write

CLKOUT

Address

Data

I/O write

Write

R/W

PS

IS

MSTRB

IOSTRB

Figure 1018. I/O Write and Memory Read

CLKOUT

Address

Data

I/O write

Read

R/W

PS

IS

MSTRB

IOSTRB

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External Bus Interface Timing

Figure 1019. I/O Read and Memory Write

CLKOUT

Address I/O read Data Write

R/W

PS

IS

MSTRB

IOSTRB

Figure 1020. I/O Read and Memory Read

CLKOUT

Address I/O read Data Read

R/W

PS

IS

MSTRB

IOSTRB

External Bus Operation

10-23

Start-Up Access Sequences

10.5 Start-Up Access Sequences

The 54x transitions between active and inactive states when entering or leaving one of four modes: IDLE1, IDLE2, reset, or IDLE3. Entering or leaving the first two modes, IDLE1 or IDLE2, requires no special consideration because the clocks to both the CPU and the on-chip peripherals remain active. However, special considerations are necessary when entering or leaving the other two modes:

10.5.1 Reset

Reset. Hardware initialization takes place. IDLE3. The device makes a transition from a state where neither the CPU nor the on-chip peripherals are being clocked to an active state.

Figure 1021 shows the reset sequence of the external bus. For proper reset operation, the RS signal must be active for at least two CLKOUT cycles. However, power-up and IDLE3 power-down mode require the reset signal to be active for more than two CLKOUT cycles. See section 6.11, Power-Down Modes, on page 6-50 for more detailed information. When the 54x acknowledges a reset, the CPU terminates program execution and forces the program counter to FF80h. The address bus is driven with FF80h while RS is low. The device enters its reset state, in reference to the external bus, according to three steps: 1) Four cycles after RS is asserted low, PS, MSTRB, and IAQ are driven high. 2) Five cycles after RS is asserted low, R/W is driven high, the data bus (if driven) goes into the high-impedance state, and the address bus is driven with 00FF80h. 3) The device enters its reset state. When reset becomes inactive, program execution starts from the program memory location FF80h. The instruction acquisition signal (IAQ) and the interrupt acknowledge signal (IACK) become active, as shown in Figure 1021, regardless of the state of the MP/MC signal.

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Start-Up Access Sequences

The device enters its active state, in reference to the external bus, according to three steps: 1) Five cycles after RS is asserted high, PS is driven low. 2) Six cycles after RS is asserted high, MSTRB and IACK are driven low. 3) One half-cycle later, the device is ready to read data and the device moves into its active state.

Figure 1021. External Bus Reset Sequence

RS

CLKOUT

Address

Previous state

FF80h

Data

R/W

PS

MSTRB IAQ or IACK

Reset state
Notes:

Bank switching

1) RS is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. 2) During reset, the data bus, is placed in high impedance and the control signals are de-asserted. 3) The reset vector is fetched with seven wait states. 4) The bank-switching cycle is inserted in the first access after reset.

External Bus Operation

10-25

Start-Up Access Sequences

10.5.2 IDLE3
The execution of the IDLE 3 instruction initiates the IDLE3 power-down mode. In this power-down mode, the PLL is halted completely to reduce power consumption. In the IDLE mode, the input clock can be kept running without additional power consumption because a transfer gate inside the 54x isolates the clock from the internal logic. The PLL must be restarted and locked before the 54x can resume processing when it exits IDLE3. This power-down mode is terminated by activating the external interrupt pins, INTn, NMI and RS, in a particular sequence. Table 108 shows the wake-up time of IDLE3 with the INTn and NMI signals. These times are defined for the hardware-configurable PLL. The times for the software programmable PLL are given in section 8.5.2. When an interrupt pin goes low, an internal counter counts the input clock cycles. The initial value loaded in the counter depends on the PLL multiplication factor to ensure the counter down-time is greater than 50 ms for a 40 MIPS DSP.

Table 108. Counter Down-Time With PLL Multiplication Factors at 40 MHz Operation
PLL Multiplication Factor 1 1.5 2 2.5 3 4 4.5 5 Equivalent CLKOUT Cycles (N) 2048 3072 2048 2560 3072 2048 2304 2560 Counter Down-Time at 40 MHz (ms) 51.2 76.8 51.2 64 76.8 51.2 57.6 64

Counter Start Value 2048 2048 1024 1024 1024 512 512 512

The counter down-times in Table 108 are valid when the input clock frequency is such that the CLKOUT frequency is 40 MHz when the PLL is locked. After the counter counts down to 0, the output from the locked PLL is fed to the internal logic.
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Start-Up Access Sequences

A low pulse (minimum duration of 10 ns) of an external interrupt causes the 54x to wake up from IDLE3 (see Figure 1022). The locked PLL clock is fed into the CPU after n cycles. An additional three cycles are needed before the 54x comes out of IDLE3. However, the 54x does not need an extra two cycles for interrupt synchronization because the interrupt pulse initializes the interrupt synchronization, which is used to detect the interrupt immediately after the 54x wake-up. When reset is used to wake up from IDLE3, the counter is not used; the output from the PLL is immediately fed to the internal logic and the CLKOUT pin is asserted. The lock-up time is 50 s for the PLL and CLKOUT to be stable. Therefore, it is necessary to keep the reset line low during this 50-ms lock-up time so that the 54x does not start processing using an unstable clock.

Figure 1022. IDLE3 Wake-Up Sequence

Normal PLL operation CLKOUT INTn, NMI IDLE3 power down PLL lock and wake up Normal

External Bus Operation

10-27

Hold Mode

10.6 Hold Mode

Two signals, HOLD and HOLDA, allow an external device to take control of the processors buses. The processor acknowledges receiving a HOLD signal from an external device by bringing HOLDA low. The 54x enters the hold mode and places its external address buses, data buses, and control signals into high impedance. The hold mode (HM) status bit, located in ST1, determines the following operating modes for the hold function:

Normal mode suspends program execution during a low HOLD signal. Concurrent mode allows program execution to continue operating from internal memory (ROM or RAM).

When HM = 1, the 54x operates in the normal mode. When HM = 0, the 54x operates in the concurrent mode. In this mode, the 54x enters the hold state only if program execution is from external memory or if an external-memory operand is being accessed. However, if program execution is from internal memory and no external memory operands are accessed, the 54x enters the hold state externally but program execution continues internally. Thus, a program can continue executing while an external operation is performed. This makes the system operation more efficient. Program execution ceases until HOLD is removed if the 54x is in a hold state with HM = 0 and an internally executing program requires an external access, or a branch to an external address. Also, if a repeat instruction that requires the use of the external bus is executing with HM = 0 when a hold occurs, the hold state is entered after the current bus cycle. If a hold occurs when a repeat instruction is executing with HM = 1, the 54x halts the execution after the current bus cycle, for either internal or external accesses. Upon reset, HM is cleared to 0. HM is set and reset by the SSBX and RSBX instructions, respectively. HOLD is not treated as an interrupt. The hold is accepted while executing the IDLE1 instruction regardless of the HM values. The hold is not accepted while executing the IDLE2 or IDLE3 instructions regardless of the HM value. If HOLD is received, the CPU continues to execute the IDLE instruction even though the external buses and the control signals are placed in high impedance. Figure 1023 shows the timing for HOLD and HOLDA. If HOLD meets the setup time before CLKOUT is low, a minimum of three machine cycles are needed before the buses and control signals go into high impedance. The HOLD is an external asynchronous input which is not latched. The external device must keep HOLD low. The external device can determine that the hold state has been entered when it receives a HOLDA signal from the 54x.
10-28

Hold Mode

If the 54x is in the middle of a multicycle instruction, it finishes the instruction before entering the hold state. After the instruction is completed, the buses are placed into high impedance. This also applies to instructions that become multicycle because wait states are added. After HOLD is de-asserted, program execution resumes at the same instruction from which it was halted. HOLDA is removed synchronously with HOLD, as shown in Figure 1023. If the setup time is met, the processor requires two machine cycles (HM = 0) or three machine cycles (HM = 1) before the buses and control signals become valid.

10.6.1 Interrupts During Hold

All interrupts are disabled while HOLD is active with HM = 1. If an interrupt is received during this period, the interrupt is latched and remains pending; therefore, HOLD does not affect any interrupt flags or registers. When HM = 0, interrupts function normally.

10.6.2 Hold and Reset

If HOLD is asserted while RS is active, normal reset operation occurs internally, but all buses and control lines remain or become high impedance and HOLDA is asserted, as shown in Figure 1024 (a) and (b). However, if RS is asserted while HOLD and HOLDA are active, the CPU is reset and the data bus, address bus, and control signals remain in high impedance, as shown in Figure 1024 (c) and (d). If HOLD is de-asserted while RS is active, HOLDA is de-asserted normally in response, and the address, data, and control lines are driven according to the active reset state, as shown in Figure 1024 (a) and (d). However, if RS is deasserted while HOLD and HOLDA are active, the operation of the device depends on the state of the MP/MC pin. If MP/MC is high, the CPU begins fetching the reset vector when the hold mode is exited. If MP/MC is low, the CPU fetches the reset vector internally and continues processing, unless it requires an external access before the hold mode is exited. Figure 1024 (b) and (c) show examples of the case in which RS is de-asserted while HOLD and HOLDA are active.

External Bus Operation

10-29

Hold Mode

Figure 1023. HOLD and HOLDA Minimum Timing for HM = 0

CLKOUT HOLD HOLDA Address Data R/W PS, DS, or IS MSTRB IOSTRB Bank Switching

Notes:

1) The timing shows the hold mode when HM = 0. When HM = 1, another cycle is required before HOLDA becomes inactive. 2) The first cycle after releasing the hold mode is a cycle of bank switching.

10-30

Hold Mode

Figure 1024. HOLD and RS Interaction

(a) Hold is Asserted While Reset is Active and De-asserted While Reset is Active
CLKOUT RS HOLD HOLDA Address Data R/W PS/DS/IS MSTRB IOSTRB IAQ or IACK Bank switching FF80h FF80h

(b) Hold is Asserted While Reset is Active and De-asserted While Reset is Inactive
CLKOUT RS HOLD HOLDA Address Data R/W PS/DS/IS MSTRB IOSTRB Bank switching IAQ or IACK MP/MC =0 MP/MC =1 FF80h FF80h

External Bus Operation

10-31

Hold Mode

Figure 1024. HOLD and RS Interaction (Continued)

(c) Hold is Asserted and De-asserted While Reset is Inactive.
CLKOUT RS HOLD HOLDA Address Data R/W PS/DS/IS MSTRB IOSTRB Bank switching IAQ or IACK MP/MC =0
MP/MC = 1

FF80h

(d) Hold is Asserted While Reset is Inactive and De-asserted While Reset is Active
CLKOUT RS HOLD HOLDA Address Data R/W PS/DS/IS MSTRB IOSTRB IAQ or IACK Bank switching FF80h

10-32

Appendix A Appendix A

Design Considerations for Using XDS510 Emulator

This appendix assists you in meeting the design requirements of the Texas Instruments XDS510 emulator with respect to IEEE-1149.1 designs and discusses the XDS510 cable (manufacturing part number 2617698-0001). This cable is identified by a label on the cable pod marked JTAG 3/5V and supports both standard 3-V and 5-V target system power inputs. The term JTAG, as used in this book, refers to TI scan-based emulation, which is based on the IEEE 1149.1 standard. For more information concerning the IEEE 1149.1 standard, contact IEEE Customer Service: Address: IEEE Customer Service 445 Hoes Lane, PO Box 1331 Piscataway, NJ 08855-1331 Phone: FAX: (800) 678IEEE in the US and Canada (908) 9811393 outside the US and Canada (908) 9819667 Telex: 833233

Topic
A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8

Page
Designing Your Target Systems Emulator Connector (14-Pin Header) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Emulator Cable Pod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Emulator Cable Pod Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Emulation Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Connections Between the Emulator and the Target System . . . . . . A-10 Physical Dimensions for the 14-Pin Emulator Connector . . . . . . . . A-14 Emulation Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-16

A-1

Designing Your Target Systems Emulator Connector (14-Pin Header)

A.1 Designing Your Target Systems Emulator Connector (14-Pin Header)

JTAG target devices support emulation through a dedicated emulation port. This port is accessed directly by the emulator and provides emulation functions that are a superset of those specified by IEEE 1149.1. To communicate with the emulator, your target system must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure A1. Table A1 describes the emulation signals. Although you can use other headers, the recommended unshrouded, straight header has these DuPont connector systems part numbers: 65610114 65611114 67996114 67997114

Figure A1. 14-Pin Header Signals and Header Dimensions933

TMS TDI PD (VCC) TDO TCK_RET TCK EMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TRST GND no pin (key) GND GND GND EMU1 Header Dimensions: Pin-to-pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal

While the corresponding female position on the cable connector is plugged to prevent improper connection, the cable lead for pin 6 is present in the cable and is grounded, as shown in the schematics and wiring diagrams in this appendix.

A-2

Designing Your Target Systems Emulator Connector (14-Pin Header)

Table A1. 14-Pin Header Signal Descriptions

Signal EMU0 EMU1 GND PD(VCC) Description Emulation pin 0 Emulation pin 1 Ground Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to VCC in the target system. Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod. This signal can be used to drive the system test clock. Test clock return. Test clock input to the emulator. May be a buffered or unbuffered version of TCK. Test data input Test data output Test mode select Test reset I O Emulator State I I Target State I/O I/O

TCK

TCK_RET

TDI TDO TMS TRST

O I O O

I O I I

I = input; O = output Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on electrical current considerations.)

Design Considerations for Using XDS510 Emulator

A-3

Bus Protocol

A.2 Bus Protocol

The IEEE 1149.1 specification covers the requirements for the test access port (TAP) bus slave devices and provides certain rules, summarized as follows:

The TMS and TDI inputs are sampled on the rising edge of the TCK signal of the device. The TDO output is clocked from the falling edge of the TCK signal of the device.

When these devices are daisy-chained together, the TDO of one device has approximately a half TCK cycle setup time before the next devices TDI signal. This timing scheme minimizes race conditions that would occur if both TDO and TDI were timed from the same TCK edge. The penalty for this timing scheme is a reduced TCK frequency. The IEEE 1149.1 specification does not provide rules for bus master (emulator) devices. Instead, it states that the device expects a bus master to provide bus slave compatible timings. The XDS510 provides timings that meet the bus slave rules.

A-4

Emulator Cable Pod

A.3 Emulator Cable Pod

Figure A2 shows a portion of the emulator cable pod. The functional features of the pod are:

TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By default, these signals are not terminated. TCK is driven with a 74LVT240 device. Because of the high-current drive (32-mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied to TCK_RET, you can use the parallel terminator in the pod. TMS and TDI can be generated from the falling edge of TCK_RET, according to the IEEE 1149.1 bus slave device timing rules. TMS and TDI are series-terminated to reduce signal reflections. A 10.368-MHz test clock source is provided. You can also provide your own test clock for greater flexibility.

Figure A2. Emulator Cable Pod Interface

5V 180 JP1 TDO (pin 7) 10.368 MHz D 74LVT240 Q 33 33 TMS (pin 1) 270 74F175 Q

Y Y
GND (pins 4,6,8,10,12)

Y Y
TDI (pin 3)

EMU0 (pin 13) 74AS1034 EMU1 (pin 14) 5V 180 270 JP2 74AS1004

TCK (pin 11)

TRST (pin 2)

TCK_RET (pin 9)

PD(VCC) (pin 5) 100 RESIN TL7705A

The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system test clock source.

Design Considerations for Using XDS510 Emulator

A-5

Emulator Cable Pod Signal Timing

A.4 Emulator Cable Pod Signal Timing

Figure A3 shows the signal timings for the emulator cable pod. Table A2 defines the timing parameters illustrated in the figure. These timing parameters are calculated from values specified in the standard data sheets for the emulator and cable pod and are for reference only. Texas Instruments does not test or guarantee these timings. The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system test clock source.

Figure A3. Emulator Cable Pod Timings

1 TCK_RET 2 TMS, TDI 4 5 6 3

TDO

Table A2. Emulator Cable Pod Timing Parameters

No. 1 2 3 4 5 6 Parameter tc(TCK) tw(TCKH) tw(TCKL) td(TMS) tsu(TDO) th(TDO) Description Cycle time, TCK_RET Pulse duration, TCK_RET high Pulse duration, TCK_RET low Delay time, TMS or TDI valid for TCK_RET low Setup time, TDO to TCK_RET high Hold time, TDO from TCK_RET high Min 35 15 15 6 3 12 20 Max 200 Unit ns ns ns ns ns ns

A-6

Emulation Timing Calculations

A.5 Emulation Timing Calculations

Example A1 and Example A2 help you calculate emulation timings in your system. For actual target timing parameters, see the appropriate data sheet for the device you are emulating. The examples use the following assumptions: tsu(TTMS) td(TTDO) td(bufmax) td(bufmin) tbufskew Setup time, target TMS or TDI to TCK high Delay time, target TDO from TCK low Delay time, target buffer maximum Delay time, target buffer minimum Skew time, target buffer between two devices in the same package: [td(bufmax) td(bufmin)] 0.15 Duty cycle, assume a 40/60% duty cycle clock 10 ns 15 ns 10 ns 1 ns 1.35 ns

tTCKfactor

0.4 (40%)

Also, the examples use the following values from Table A2 on page A-6: td(TMSmax) tsu(TDOmin) Delay time, emulator TMS or TDI from TCK_RET low, maximum Setup time, TDO to emulator TCK_RET high, minimum 20 ns 3 ns

There are two key timing paths to consider in the emulation design:

The TCK_RET-to-TMS or TDI path, called tpd(TCK_RET-TMS/TDI) (propagation delay time) The TCK_RET-to-TDO path, called tpd(TCK_RET-TDO)

In the examples, the worst-case path delay is calculated to determine the maximum system test clock frequency.

Design Considerations for Using XDS510 Emulator

A-7

Emulation Timing Calculations

Example A1. Key Timing for a Single-Processor System Without Buffers

t pd

TCK_RET-TMS TDI

t pd

TCK_RETTDO

+ t ) + (20 ns0.410 ns) + 75 ns, or 13.3 MHz t )t + t ) + (15 ns0.4 3 ns) + 45 ns, or 22.2 MHz
TMSmax TCKfactor d TTDO TCKfactor

td

)t

su TTMS

su TDOmin

In this case, because the TCK_RET-to-TMS/TDI path requires more time to complete, it is the limiting factor.

Example A2. Key Timing for a Single- or Multiple-Processor System With Buffered Input and Output
t pd (TCK_RET

*TMS TDI) +

t d (TMSmax)

)t

su (TTMS)

) 2t

bufmax

t TCKfactor

ns + (20 ns ) 10 0.4 ) 2(10) ns)

+ 54 ns,
t pd (TCK_RET

or 18.5 MHz

*TDO)

t d (TTDO)

)t

su (TDOmin)

)t

d (bufskew)

TCKfactor

ns + (15 ns ) 3 0.4 ) 1.35 ns) + 58.4 ns, or 20.7 MHz

In this case also, because the TCK_RET-to-TMS/TDI path requires more time to complete, it is the limiting factor.
A-8

Emulation Timing Calculations

In a multiprocessor application, it is necessary to ensure that the EMU0 and EMU1 lines can go from a logic low level to a logic high level in less than 10 s, this parameter is called rise time, tr. This can be calculated as follows: tr = 5(Rpullup Ndevices Cload_per_device) = 5(4.7 kW 16 15 pF) = 5(4.7 103 W 16 15 = no 12 F) = 5(1128 10 9 ) = 5.64 s

Design Considerations for Using XDS510 Emulator

A-9

Connections Between the Emulator and the Target System

A.6 Connections Between the Emulator and the Target System

It is extremely important to provide high-quality signals between the emulator and the JTAG target system. You must supply the correct signal buffering, test clock inputs, and multiple processor interconnections to ensure proper emulator and target system operation. Signals applied to the EMU0 and EMU1 pins on the JTAG target device can be either input or output. In general, these two pins are used as both input and output in multiprocessor systems to handle global run/stop operations. EMU0 and EMU1 signals are applied only as inputs to the XDS510 emulator header.

A.6.1 Buffering Signals

If the distance between the emulation header and the JTAG target device is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, no buffering is necessary. Figure A4 shows the simpler, no-buffering situation. The distance between the header and the JTAG target device must be no more than 6 inches. The EMU0 and EMU1 signals must have pullup resistors connected to VCC to provide a signal rise time of less than 10 s. A 4.7-k resistor is suggested for most applications.

Figure A4. Emulator Connections Without Signal Buffering

6 inches or less VCC JTAG device EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5 VCC

Figure A5 shows the connections necessary for buffered transmission signals. The distance between the emulation header and the processor is greater than 6 inches. Emulation signals TMS, TDI, TDO, and TCK_RET are buffered through the same device package.
A-10

Connections Between the Emulator and the Target System

Figure A5. Emulator Connections With Signal Buffering

Greater than 6 inches VCC JTAG device EMU0 EMU1 TRST TMS TDI TDO TCK 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5 VCC

The EMU0 and EMU1 signals must have pullup resistors connected to VCC to provide a signal rise time of less than 10 s. A 4.7-k resistor is suggested for most applications. The input buffers for TMS and TDI should have pullup resistors connected to VCC to hold these signals at a known value when the emulator is not connected. A resistor value of 4.7 k or greater is suggested. To have high-quality signals (especially the processor TCK and the emulator TCK_RET signals), you may have to employ special care when routing the printed wiring board trace. You also may have to use termination resistors to match the trace impedance. The emulator pod provides optional internal parallel terminators on the TCK_RET and TDO. TMS and TDI provide fixed series termination. Because TRST is an asynchronous signal, it should be buffered as needed to ensure sufficient current to all target devices.

Design Considerations for Using XDS510 Emulator

A-11

Connections Between the Emulator and the Target System

A.6.2 Using a Target-System Clock

Figure A6 shows an application with the system test clock generated in the target system. In this application, the emulators TCK signal is left unconnected.

Figure A6. Target-System-Generated Test Clock

Greater than 6 inches VCC JTAG device EMU0 EMU1 TRST TMS TDI TDO TCK NC 13 14 2 1 3 7 11 9 Emulator header EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND System test clock GND GND GND GND GND 4 6 8 10 12 PD 5 VCC

Note:

When the TMS and TDI lines are buffered, pullup resistors must be used to hold the buffer inputs at a known level when the emulator cable is not connected.

There are two benefits in generating the test clock in the target system:

The emulator provides only a single 10.368-MHz test clock. If you allow the target system to generate your test clock, you can set the frequency to match your system requirements. In some cases, you may have other devices in your system that require a test clock when the emulator is not connected. The system test clock also serves this purpose.

A-12

Connections Between the Emulator and the Target System

A.6.3 Configuring Multiple Processors

Figure A7 shows a typical daisy-chained multiprocessor configuration that meets the minimum requirements of the IEEE 1149.1 specification. The emulation signals are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system. One of the benefits of this interface is that you can slow down the test clock to eliminate timing problems. Follow these guidelines for multiprocessor support:

The processor TMS, TDI, TDO, and TCK signals must be buffered through the same physical device package for better control of timing skew. The input buffers for TMS, TDI, and TCK should have pullup resistors connected to VCC to hold these signals at a known value when the emulator is not connected. A resistor value of 4.7 k or greater is suggested. Buffering EMU0 and EMU1 is optional but highly recommended to provide isolation. These are not critical signals and do not have to be buffered through the same physical package as TMS, TCK, TDI, and TDO.

Figure A7. Multiprocessor Connections

JTAG device TDO TRST TMS TCK TDI EMU0 EMU1 JTAG device TDO TMS TRST TCK TDI EMU0 EMU1 VCC VCC Emulator header 13 14 2 1 3 7 11 9 EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET GND GND GND GND GND GND 4 6 8 10 12 PD 5

Design Considerations for Using XDS510 Emulator

A-13

Physical Dimensions for the 14-Pin Emulator Connector

A.7 Physical Dimensions for the 14-Pin Emulator Connector

The JTAG emulator target cable consists of a 3-foot section of jacketed cable that connects to the emulator, an active cable pod, and a short section of jacketed cable that connects to the target system. The overall cable length is approximately 3 feet 10 inches. Figure A8 and Figure A9 (page A-15) show the physical dimensions for the target cable pod and short cable. The cable pod box is nonconductive plastic with four recessed metal screws.

Figure A8. Pod/Connector Dimensions

2.70 in., nominal 4.50 in., nominal 9.50 in., nominal

0.90 in., nominal Emulator cable pod Connector

Short, jacketed cable

See Figure A9
Note: All dimensions are in inches and are nominal dimensions, unless otherwise specified. Pin-to-pin spacing on the connector is 0.100 inches in both the X and Y planes.

A-14

Physical Dimensions for the 14-Pin Emulator Connector

Figure A9. 14-Pin Connector Dimensions

0.20 i nch, nominal

Cable 0.66 inch, nominal

Connector, side view 0.100 inch, nominal (pin spacing)

13 11 9 7 14 12 10 8 6 4 2

Key, pin 6

Cable
5 3 1

0.87 inch, nominal 0.100 inch, nominal (pin spacing)

Connector, front view 2 rows of pins

Design Considerations for Using XDS510 Emulator

A-15

Emulation Design Considerations

A.8 Emulation Design Considerations

This section describes the use and application of the scan path linker (SPL), which can simultaneously add all four secondary JTAG scan paths to the main scan path. It also describes the use of the emulation pins and the configuration of multiple processors.

A.8.1 Using Scan Path Linkers

You can use the TI ACT8997 scan path linker (SPL) to divide the JTAG emulation scan path into smaller, logically connected groups of 4 to 16 devices. As described in the Advanced Logic and Bus Interface Logic Data Book, the SPL is compatible with the JTAG emulation scanning. The SPL is capable of adding any combination of its four secondary scan paths into the main scan path. A system of multiple, secondary JTAG scan paths has better fault tolerance and isolation than a single scan path. Since an SPL has the capability of adding all secondary scan paths to the main scan path simultaneously, it can support global emulation operations, such as starting or stopping a selected group of processors. TI emulators do not support the nesting of SPLs (for example, an SPL connected to the secondary scan path of another SPL). However, you can have multiple SPLs on the main scan path. Scan path selectors are not supported by this emulation system. The TI ACT8999 scan path selector is similar to the SPL, but it can add only one of its secondary scan paths at a time to the main JTAG scan path. Thus, global emulation operations are not assured with the scan path selector. You can insert an SPL on a backplane so that you can add up to four device boards to the system without the jumper wiring required with nonbackplane devices. You connect an SPL to the main JTAG scan path in the same way you connect any other device. Figure A10 shows how to connect a secondary scan path to an SPL.

A-16

Emulation Design Considerations

Figure A10. Connecting a Secondary JTAG Scan Path to a Scan Path Linker

SPL DTCK TDI TMS TCK TRST TDO DTDO0 DTMS0 DTDI0 DTDO1 DTMS1 DTDI1 TDI DTDO2 DTMS2 DTDI2 DTDO3 DTMS3 DTDI3 TMS TCK TRST TDO TDI TMS TCK TRST TDO ... JTAG N JTAG 0

The TRST signal from the main scan path drives all devices, even those on the secondary scan paths of the SPL. The TCK signal on each target device on the secondary scan path of an SPL is driven by the SPLs DTCK signal. The TMS signal on each device on the secondary scan path is driven by the respective DTMS signals on the SPL. DTDO0 on the SPL is connected to the TDI signal of the first device on the secondary scan path. DTDI0 on the SPL is connected to the TDO signal of the last device in the secondary scan path. Within each secondary scan path, the TDI signal of a device is connected to the TDO signal of the device before it. If the SPL is on a backplane, its secondary JTAG scan paths are on add-on boards; if signal degradation is a problem, you may need to buffer both the TRST and DTCK signals. Although degradation is less likely for DTMSn signals, you may also need to buffer them for the same reasons.

Design Considerations for Using XDS510 Emulator

A-17

Emulation Design Considerations

A.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL)

Example A3 and Example A4 help you to calculate the key emulation timings in the SPL secondary scan path of your system. For actual target timing parameters, see the appropriate device data sheet for your target device. The examples use the following assumptions: tsu(TTMS) td(TTDO) td(bufmax) td(bufmin) t(bufskew) Setup time, target TMS/TDI to TCK high Delay time, target TDO from TCK low Delay time, target buffer, maximum Delay time, target buffer, minimum Skew time, target buffer, between two devices in the same package: [td(bufmax) td(bufmin)] 0.15 Duty cycle, TCK assume a 40/60% clock 10 ns 15 ns 10 ns 1 ns 1.35 ns

t(TCKfactor)

0.4 (40%)

Also, the examples use the following values from the SPL data sheet: Delay time, SPL DTMS/DTDO from TCK low, maximum tsu(DTDLmin) Setup time, DTDI to SPL TCK high, minimum td(DTCKHmin) Delay time, SPL DTCK from TCK high, minimum td(DTCKLmax) Delay time, SPL DTCK from TCK low, maximum There are two key timing paths to consider in the emulation design: td(DTMSmax) 31 ns 7 ns 2 ns 16 ns

The TCK-to-DTMS/DTDO path, called tpd(TCK-DTMS) The TCK-to-DTDI path, called tpd(TCK-DTDI)

A-18

Emulation Design Considerations

Of the following two cases, the worst-case path delay is calculated to determine the maximum system test clock frequency.

Example A3. Key Timing for a Single-Processor System Without Buffering (SPL)

t pd

TCK-DTMS

td

DTMSmax

)t

d DTCKHmin

)t

su TTMS

tpd

TCK-DTDI

ns + (31 ns ) 20.4 ) 10 ns) + 107.5 ns, or 9.3 MHz t )t )t + t + (15 ns ) 16 ns ) 7 ns) 0.4 + 9.5 ns, or 10.5 MHz
d TTDO d DTCKLmax TCKfactor

t TCKfactor

su DTDLmin

In this case, the TCK-to-DTMS/DTDL path is the limiting factor.

Example A4. Key Timing for a Single- or Multiprocessor-System With Buffered Input and Output (SPL)

t pd (TCK-TDMS)

t d (DTMSmax)

)t

DTCKHmin

)t

su (TTMS)

)t

(bufskew)

t pd (TCKDTDI)

+ (31 ns ) 2 ns ) 10 ns ) 1.35 ns) 0.4 + 110.9 ns, or 9.0 MHz t )t )t + t

d (TTDO) d DTCKLmax TCKfactor

t TCKfactor

su (DTDLmin)

)t

d (bufskew)

) + (15 ns ) 15 ns0.4 7 ns ) 10 ns) + 120 ns, or 8.3 MHz

In this case, the TCK-to-DTDI path is the limiting factor.
Design Considerations for Using XDS510 Emulator
A-19

Emulation Design Considerations

A.8.3 Using Emulation Pins

The EMU0/1 pins of TI devices are bidirectional, 3-state output pins. When in an inactive state, these pins are at high impedance. When the pins are active, they provide one of two types of output:

Signal Event. The EMU0/1 pins can be configured via software to signal internal events. In this mode, driving one of these pins low can cause devices to signal such events. To enable this operation, the EMU0/1 pins function as open-collector sources. External devices such as logic analyzers can also be connected to the EMU0/1 signals in this manner. If such an external source is used, it must also be connected via an open-collector source. External Count. The EMU0/1 pins can be configured via software as totem-pole outputs for driving an external counter. If the output of more than one device is configured for totem-pole operation, then these devices can be damaged. The emulation software detects and prevents this condition. However, the emulation software has no control over external sources on the EMU0/1 signal. Therefore, all external sources must be inactive when any device is in the external count mode.

TI devices can be configured by software to halt processing if their EMU0/1 pins are driven low. This feature combined with the signal event output, allows one TI device to halt all other TI devices on a given event for system-level debugging. If you route the EMU0/1 signals between multiple boards, they require special handling because they are more complex than normal emulation signals. Figure A11 shows an example configuration that allows any processor in the system to stop any other processor in the system. Do not tie the EMU0/1 pins of more than 16 processors together in a single group without using buffers. Buffers provide the crisp signals that are required during a RUNB (run benchmark) debugger command or when the external analysis counter feature is used.

A-20

Emulation Design Considerations

Figure A11. EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns

Target board 1

Backplane XCNT_ENABLE EMU0/1-IN

... ...

Device 1

PAL EMU0/1-OUT

Pullup resistor

TCK

To emulator EMU0 Opencollector drivers

Pullup resistor EMU0/1 Device n

...

Device 1

Notes:

1) The low time on EMU0/1-IN should be at least one TCK cycle and less than 10 ms. Software sets the EMU0/1-OUT pin to a high state. 2) To enable the open-collector driver and pullup resistor on EMU1 to provide rise/fall times of less than 25 ns, the modification shown in this figure is suggested. Rise times of more than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger analysis menu is used.

These seven important points apply to the circuitry shown in Figure A11 and the timing shown in Figure A12:

Open-collector drivers isolate each board. The EMU0/1 pins are tied together on each board. At the board edge, the EMU0/1 signals are split to provide both input and output connections. This is required to prevent the open-collector drivers from acting as latches that can be set only once. The EMU0/1 signals are bused down the backplane. Pullup resistors must be installed as required.
Design Considerations for Using XDS510 Emulator
A-21

... ...

Opencollector drivers

Pullup resistor EMU0/1 Device n

Target board m

...

Emulation Design Considerations

The bused EMU0/1 signals go into a programmable logic array device PAL whose function is to generate a low pulse on the EMU0/1-IN signal when a low level is detected on the EMU0/1-OUT signal. This pulse must be longer than one TCK period to affect the devices but less than 10 s to avoid possible conflicts or retriggering once the emulation software clears the devices pins. During a RUNB debugger command or other external analysis count, the EMU0/1 pins on the target device become totem-pole outputs. The EMU1 pin is a ripple carry-out of the internal counter. EMU0 becomes a processor-halted signal. During a RUNB or other external analysis count, the EMU0/1-IN signal to all boards must remain in the high (disabled) state. You must provide some type of external input (XCNT_ENABLE) to the PAL to disable the PAL from driving EMU0/1-IN to a low state.

If you use sources other than TI processors (such as logic analyzers) to drive EMU0/1, their signal lines must be isolated by open-collector drivers and be inactive during RUNB and other external analysis counts. You must connect the EMU0/1-OUT signals to the emulation header or directly to a test bus controller.

Figure A12. Suggested Timings for the EMU0 and EMU1 Signals
TCK

EMU0/1-OUT

EMU0/1-IN

A-22

Emulation Design Considerations

Figure A13. EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 ns
Target board 1

Backplane XCNT_ENABLE EMU0/1-IN

... ... ...

Device 1

PAL EMU0/1-OUT

Pullup resistor

TCK

To Emulator EMU0 Circuitry required for >25-ns rise/fall time modification Opencollector drivers

Pullup resistor EMU0/1 Device n

...

AND To emulator EMU1

EMU1 Up to m boards

Device 1

EMU1 signal from other boards

Notes:

1) The low time on EMU0/1-IN should be at least one TCK cycle and less than 10 ms. Software will set the EMU0/1-OUT port to a high state. 2) To enable the open-collector driver and pullup resistor on EMU1 to provide rise/fall time of greater than 25 ns, the modification shown in this figure is suggested. Rise times of more than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger analysis menu is used.

Design Considerations for Using XDS510 Emulator

... ...

Opencollector drivers

Pullup resistor EMU0/1 Device n

Target board m

...

A-23

Emulation Design Considerations

You do not need to have devices on one target board stop devices on another target board using the EMU0/1 signals (see the circuit in Figure A14). In this configuration, the global-stop capability is lost. It is important not to overload EMU0/1 with more than 16 devices.

Figure A14. EMU0/1 Configuration Without Global Stop

Target board 1 Pullup resistor
...

EMU0/1 Device n

Pullup resistor To emulator EMU0/1

Device 1

...

...

Target board m

...

Pullup resistor
...

EMU0/1 Device n

Device 1

...

Note:

The open-collector driver and pullup resistor on EMU1 must be able to provide rise/fall times of less than 25 ns. Rise times of more than 25 ns can cause the emulator to detect false edges during the RUNB command or when the external counter selected from the debugger analysis menu is used. If this condition cannot be met, then the EMU0/1 signals from the individual boards must be ANDed together (as shown in Figure A14) to produce an EMU0/1 signal for the emulator.

A.8.4 Performing Diagnostic Applications

For systems that require built-in diagnostics, it is possible to connect the emulation scan path directly to a TI ACT8990 test bus controller (TBC) instead of the emulation header. The TBC is described in the Texas Instruments Advanced Logic and Bus Interface Logic Data Book. Figure A15 shows the scan path connections of n devices to the TBC.
A-24

Emulation Design Considerations

Figure A15. TBC Emulation Connections for n JTAG Scan Paths

Clock VCC

TBC

TCKI TDO TMS0 TMS1 TDI TMS EMU0 EMU1 TRST TCK TDO JTAG0

TMS2/EVNT0 TMS3/EVNT1 TMS4/EVNT2 TMS5/EVNT3 TCKO TDI0 TDI1

TDI TMS

JTAGN

EMU0 EMU1 TRST TCK TDO

In the system design shown in Figure A15, the TBC emulation signals TCKI, TDO, TMS0, TMS2/EVNT0, TMS3/EVNT1, TMS5/EVNT3, TCKO, and TDI0 are used, and TMS1, TMS4/EVNT2, and TDI1 are not connected. The target devices EMU0 and EMU1 signals are connected to VCC through pullup resistors and tied to the TBCs TMS2/EVNT0 and TMS3/EVNT1 pins, respectively. The TBCs TCKI pin is connected to a clock generator. The TCK signal for the main JTAG scan path is driven by the TBCs TCKO pin. On the TBC, the TMS0 pin drives the TMS pins on each device on the main JTAG scan path. TDO on the TBC connects to TDI on the first device on the main JTAG scan path. TDI0 on the TBC is connected to the TDO signal of the last device on the main JTAG scan path. Within the main JTAG scan path, the TDI signal of a device is connected to the TDO signal of the device before it. TRST for the devices can be generated either by inverting the TBCs TMS5/EVNT3 signal for software control or by logic on the board itself.

Design Considerations for Using XDS510 Emulator

A-25

Appendix B Appendix A

Development Support and Part Order Information

This appendix provides development support information, device part numbers, and support tool ordering information for the 54x. Each 54x support product is described in the TMS320 DSP Development Support Reference Guide. In addition, more than 100 third-party developers offer products that support the TI TMS320 family. For more information, refer to the TMS320 Third-Party Support Reference Guide. For information on pricing and availability, contact the nearest TI Field Sales Office or authorized distributor. See the list at the back of this book.

Topic
B.1 B.2

Page
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Part Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

Development Support and Part Order Information

B-1

Development Support

B.1 Development Support

This section describes the development support provided by Texas Instruments.

B.1.1 Development Tools

TI offers an extensive line of development tools for the 54x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

Code Generation Tools

The optimizing ANSI C compiler translates ANSI C language directly into highly optimized assembly code. You can then assemble and link this code with the TI assembler/linker, which is shipped with the compiler. This product is currently available for PCs (DOS, DOS extended memory, OS/2), HP workstations, and SPARC workstations. See the TMS320C54x Optimizing C Compiler Users Guide for detailed information about this tool. The assembler/linker converts source mnemonics to executable object code. This product is currently available for PCs (DOS, DOS extended memory, OS/2). The 54x assembler for HP and SPARC workstations is available only as part of the optimizing 54x compiler. See the TMS320C54x Assembly Language Tools Users Guide for detailed information about available assembly-language tools.

System Integration and Debug Tools

The simulator simulates (via software) the operation of the 54x and can be used in C and assembly software development. This product is currently available for PCs (DOS, Windows), HP workstations, and SPARC workstations. See the TMS320C54x C Source Debugger Users Guide for detailed information about the debugger. The XDS510 emulator performs full-speed in-circuit emulation with the 54x, providing access to all registers as well as to internal and external memory of the device. It can be used in C and assembly software development and has the capability to debug multiple processors. This product is currently available for PCs (DOS, Windows, OS/2), HP workstations, and SPARC workstations. This product includes the emulator board (emulator box, power supply, and SCSI connector cables in the HP and SPARC versions), the 54x C source debugger and the JTAG cable.

B-2

Development Support

Because the C2xx, C3x, C4x, and C5x XDS510 emulators also come with the same emulator board (or box) as the 54x, you can buy the 54x C Source Debugger Software as a separate product called the 54x C Source Debugger Conversion Software. This enables you to debug 54x applications with a previously purchased emulator board. The emulator cable that comes with the C3x XDS510 emulator cannot be used with the 54x. You need the JTAG emulation conversion cable (see section B.2) instead. The emulator cable that comes with the C5x XDS510 emulator can be used with the 54x without any restriction. See the TMS320C54x C Source Debugger Users Guide) for detailed information about the 54x emulator.

The TMS320C54x evaluation module (EVM) is a PC/AT plug-in card that lets you evaluate certain characteristics of the 54x digital signal processor to see if it meets your application requirements. The 54x EVM carries a 541 DSP on board to allow full-speed verification of 54x code. The EVM has 5K bytes of on-chip program/data RAM, 28K bytes of on-chip ROM, two serial ports, a timer, access to 64K bytes each of external program and data RAM, and an external analog interface for evaluation of the 54x family of devices for applications. See the TMS320C54x Evaluation Module Technical Reference for detailed information about the 54x EVM.

B.1.2 Third-Party Support

The TMS320 family is supported by products and services from more than 100 independent third-party vendors and consultants. These support products take various forms (both as software and hardware), from cross-assemblers, simulators, and DSP utility packages to logic analyzers and emulators. The expertise of those involved in support services ranges from speech encoding and vector quantization to software/hardware design and system analysis. To ask about third-party services, products, applications, and algorithm development packages, contact the third party directly. Refer to the TMS320 ThirdParty Support Reference Guide for addresses and phone numbers.

Development Support and Part Order Information

B-3

Development Support

B.1.3 Technical Training Organization (TTO) TMS320 Workshops

54x DSP Design Workshop. This workshop is tailored for hardware and software design engineers and decision-makers who will be designing and utilizing the 54x generation of DSP devices. Hands-on exercises throughout the course give participants a rapid start in developing 54x design skills. Microprocessor/assembly language experience is required. Experience with digital design techniques and C language programming experience is desirable. These topics are covered in the 54x workshop:

B.1.4 Assistance

54x architecture/instruction set Use of the PC-based software simulator Use of the 54x assembler/linker C programming environment System architecture considerations Memory and I/O interfacing Development support

For registration information, pricing, or to enroll, call (800)3365236, ext. 3904.

For assistance to TMS320 questions on device problems, development tools, documentation, software upgrades, and new products, you can contact TI. See If You Need Assistance in Preface for information.

B-4

Part Order Information

B.2 Part Order Information

This section describes the part numbers of 54x devices, development support hardware, and software tools.

B.2.1 Device and Development Support Tool Nomenclature Prefixes

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 device has one of three prefix designators: TMX, TMP, or TMS. Each support tool has one of two possible prefix designators: TMDX or TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices and tools (TMS/TMDS). This development flow is defined below. Device Development Evolutionary Flow: TMX TMP The part is an experimental device that is not necessarily representative of the final devices electrical specifications. The part is a device from a final silicon die that conforms to the devices electrical specifications but has not completed quality and reliability verification. The part is a fully qualified production device.

TMS

Support Tool Development Evolutionary Flow: TMDX The development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS The development-support product is a fully qualified development support product. TMX and TMP devices and TMDX development support tools are shipped with the following disclaimer: Developmental product is intended for internal evaluation purposes. TMS devices and TMDS development support tools have been fully characterized, and the quality and reliability of the device has been fully demonstrated. Texas Instruments standard warranty applies to these products. Note: It is expected that prototype devices (TMX or TMP) have a greater failure rate than standard production devices. Texas Instruments recommends that these devices not be used in any production system, because their expected end-use failure rate is still undefined. Only qualified production devices should be used.

Development Support and Part Order Information

B-5

Part Order Information

B.2.2 Device Nomenclature

TI device nomenclature includes the device family name and a suffix. Figure B1 provides a legend for reading the complete device name for any 54x device family member.

B-6

Part Order Information

Figure B1. TMS320 DSP Device Nomenclature

TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = experimental device prototype device qualified device MIL-STD-883C High Rel (non-883C) C 542 PGE (L) TEMPERATURE RANGE (DEFAULT: 0C TO 70C) H = 0C to 50C L = 0C to 70C S = 55C to 100C M = 55C to 125C A = 40C to 85C PACKAGE TYPE N = plastic DIP J = ceramic DIP JD = ceramic DIP side-brazed GB = ceramic PGA FZ = ceramic CC FN = plastic leaded CC FD = ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PQ = 132-pin plastic bumpered QFP PGE = 144-pin plastic TQFP GGU = 144-pin BGA PGF = 176-pin plastic TQFP GGW= 176-pin BGA DEVICE 1x DSP: 10 14 15 2x DSP: 25 26 2xx DSP: 203 204 3x DSP: 30 31 32 4x DSP: 40 44 5x DSP: 50 51 52 DIP = Dual-In-Line Package PGA = Pin Grid Array CC = Chip Carrier QFP = Quad Flat Package TQFP = Thin Quad Flat Package BGA = Ball Grid Array 54x DSP: 541 542 543 6x DSP: 6201 6201 6701 6211 545 546 548 549 5402 5410 5420 53 56 57 206 209 240 16 17

DEVICE FAMILY 320 = TMS320 Family

TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM LC = Low-Voltage CMOS (3.3 V) VC = Low-Voltage CMOS [3 V (2.5 V or 1.8 V core)]

Development Support and Part Order Information

B-7

Part Order Information

B.2.3 Development Support Tools

Table B1 lists the development support tools available for the 54x, the platform on which they run, and their part numbers.

Table B1. Development Support Tools Part Numbers

Development Tool Assembler/Linker C Compiler/Assembler/Linker C Compiler/Assembler/Linker C Source Debugger Conversion Software C Source Debugger Conversion Software Evaluation Module (EVM) Simulator (C language) Simulator (C language) XDS510 Emulator XDS510WS Emulator PC (DOS ) Platform Part Number TMDS324L850-02 TMDS324L855-02 TMDS324L555-08 TMDS32401L0 TMDS32406L0 TMDX3260051 TMDS324L851-02 TMDS324L551-09 TMDS00510 TMDS00510WS TMDS3080002

t PC (DOSt, Windowst, OS/2t) HP (HP-UXt) / SPARCt (Sun OSt) PC (DOSt, Windowst, OS/2t) (XDS510t) HP (HP-UXt) / SPARCt (Sun OSt) (XDS510WSt) PC (DOSt, Windowst, OS/2t) PC (DOSt, Windowst) HP (HP-UXt) / SPARCt (Sun OSt) PC (DOSt, Windowst, OS/2t) HP (HP-UXt) / SPARCt (Sun OSt)
(SCSI)

3 V/5 V PC/SPARC JTAG Emulation Cable XDS510

t / XDS510WSt

Includes XDS510 board and JTAG cable; TMDS32401L0 C-source debugger conversion software not included Includes XDS510WS box, SCSI cable, power supply, and JTAG cable; TMDS32406L0 C-source debugger conversion software not included

B-8

Appendix C Appendix A

Submitting ROM Codes to TI

The size of a printed circuit board is a consideration in many DSP applications. To make full use of the board space, Texas Instruments offers this ROM code option that reduces the chip count and provides a single-chip solution. This option allows you to use a code-customized processor for a specific application while taking advantage of:

Greater memory expansion Lower system cost Less hardware and wiring Smaller PCB

If a routine or algorithm is used often, it can be programmed into the on-chip ROM of a TMS320 DSP. TMS320 programs can also be expanded by using external memory; this reduces chip count and allows for a more flexible program memory. Multiple functions are easily implemented by a single device, thus enhancing system capabilities. TMS320 development tools are used to develop, test, refine, and finalize the algorithms. The microprocessor/microcomputer (MP/MC) mode is available on all ROM-coded TMS320 DSP devices when accesses to either on-chip or off-chip memory are required. The microprocessor mode is used to develop, test, and refine a system application. In this mode of operation, the TMS320 acts as a standard microprocessor by using external program memory. When the algorithm has been finalized, the code can be submitted to Texas Instruments for masking into the on-chip program ROM. At that time, the TMS320 becomes a microcomputer that executes customized programs from the onchip ROM. Should the code need changing or upgrading, the TMS320 can once again be used in the microprocessor mode. This shortens the fieldupgrade time and avoids the possibility of inventory obsolescence. Figure C1 illustrates the procedural flow for developing and ordering TMS320 masked parts. When ordering, there is a one-time, nonrefundable charge for mask tooling. A minimum production order per year is required for any masked-ROM device. ROM codes will be deleted from the TI system one year after the final delivery.
C-1

Submitting ROM Codes to TI

Figure C1. TMS320 ROM Code Submittal Flowchart

Customer TMS320 Design

Customer submits: TMS320 New Code Release Form Print Evaluation and Acceptance Form (PEAF) Purchase order for mask prototypes TMS320 code

Texas Instruments responds: Customer code input into TI system Code sent back to customer for verification

No

Customer approves algorithm

Yes TI produces prototypes

No

Customer approves prototypes (minimum production order required)

Yes TMS320 production

C-2

Submitting ROM Codes to TI

The TMS320 ROM code may be submitted in one of the following forms:

3-1/2-inch floppy: COFF format from macro-assembler/linker (preferred) 5-1/4-inch floppy: COFF format from macro-assembler/linker Modem (BBS): COFF format from macro-assembler/linker EPROM (others): TMS27C64 PROM: TBP28S166, TBP28S86

When code is submitted to TI for masking, the code is reformatted to accommodate the TI mask-generation system. System-level verification by the customer is therefore necessary to ensure the reformatting remains transparent and does not affect the execution of the algorithm. The formatting changes involve the removal of address-relocation information (the code address begins at the base address of the ROM in the TMS320 device and progresses without gaps to the last address of the ROM) and the addition of data in the reserved locations of the ROM for device ROM test. Because these changes have been made, a checksum comparison is not a valid means of verification. With each masked-device order, the customer must sign a disclaimer that states: The units to be shipped against this order were assembled, for expediency purposes, on a prototype (that is, nonproduction qualified) manufacturing line, the reliability of which is not fully characterized. Therefore, the anticipated inherent reliability of these prototype units cannot be expressly defined. and a release that states: Any masked ROM device may be resymbolized as TI standard product and resold as though it were an unprogrammed version of the device, at the convenience of Texas Instruments. The use of the ROM-protect feature does not hold for this release statement. Additional risk and charges are involved when the ROM-protect feature is selected. Contact the nearest TI Field Sales Office for more information on procedures, leadtimes, and cost associated with the ROM-protect feature.

Submitting ROM Codes to TI

C-3

Appendix D Appendix A

Summary of Updates in This Document

This appendix provides a summary of the updates in this version of the document. Updates within paragraphs appear in a bold typeface.

Page:
iii

Changed or Added:
Changed the second sentence of the first paragraph to: This book, the first volume of a 5-volume set, serves as a reference for the TMS320C54x DSP and provides information for developing hardware and software applications using the 54x. Added the following two paragraphs: Many device references are shown with an apostrophe ( ) replacing the usual alphanumeric prefix (ex. 549 instead of TMS320C549). You should consult the device-specific datasheet if you need more information about the devices nomenclature. This users guide contains limited information about the enhanced peripherals available on the 5402, 5410, and 5420 devices. For detailed information on the enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

vi 1-6

Added volume 5 of the TMS320C54x DSP Reference Set to Related Documentation From Texas Instruments. Changed the first second-level bullet under Memory to:

192K words 16-bit addressable memory space (64K-words program, 64K-words data, and 64K-words I/O), with extended program memory in the 548, 549, 5402, 5410, and 5420.

Added the following information to the configuration table at the bottom of the page:
Device 5402 5410 5420 Program ROM 4 16 0 Program/Data ROM 0 0 0 DARAM SARAM 16 8 32 0 56 168

Summary of Updates in This Document

D-1

Summary of Updates in This Document

Page:
1-7

Changed or Added:
Changed the first sentence of the note below the option table to:
The 541B, 545A, 546A, 548, 549, 5402, 5410, and 5420 have a software-pro-

grammable PLL and two additional saturation modes.

1-8

Added the following information to the ports table at the top of the page:
Serial Ports Host Port Interface 1 1 1 MultiChannel Buffered 2 3 6 Time-Division Multiplexed 0 0 0

Device 5402 5410 5420

Synchronous 0 0 0

Buffered 0 0 0

Added the following information to the power supply, speed, and package table.
Device
VC5402

Power Supply 3.3 V (1.8 core) 3.3 V (2.5 core) 3.3 V (1.8 core)

Speed 10 ns 10 ns 10 ns

Package 144-pin TQFP/144-pin Micro Star BGA

t t t

VC5410
VC5420

144-pin TQFP/176-pin Micro Star BGA 144-pin TQFP/144-pin Micro Star BGA

2-5

Added the following information to Table 22, Program and Data Memory on the TMS320C54x Devices:
Memory Type ROM: Program Program/data DARAM SARAM 5402 4K 4K 0 16K 0 5410 16K 16K 0 8K 56K 5420 0 0 0 32K 168K

D-2

Summary of Updates in This Document

Page:
2-5

Changed or Added:
Changed the second paragraph in section 2.2.1, On-Chip ROM, to the following: On devices with a small amount of ROM (2K words), the ROM contains a bootloader that is useful for booting to faster on-chip or external RAM. For bootloading details on all 54x devices except the 548, 549, 5402, and 5410, see TMS320C54x DSP Reference Set, Volume 4: Applications Guide. For bootloading details on the 548, 549, and 5410, see TMS320C548/549 Bootloader Technical Reference. Changed the first sentence of the third paragraph in section 2.2.1, On-Chip ROM, to the following: On devices with larger amounts of ROM, a portion of the ROM may be mapped into both data and program space (except the 5410).

2-11

Changed the first sentence in section 2.7.2, Software-Programmable Wait-State Generator, to: The software-programmable wait-state generator extends external bus cycles up to seven machine cycles (14 machine cycles in the 549, 5402 5410, and 5420) to interface with slower off-chip memory and I/O devices.

2-12

Added the following information to Table 23, Host Port Interfaces on the TMS320C54x Devices:
Host Port Interface Standard 8-bit HPI Enhanced 8-bit HPI Enhanced 16-bit HPI 5402 0 1 0 5410 0 1 0 5420 0 0 1

2-14

Added the following information to Table 24, Serial Port Interfaces on the TMS320C54x Devices:
Serial Ports Synchronous Buffered Multichannel Buffered TDM 5402 0 0 2 0 5410 0 0 3 0 5420 0 0 6 0

2-16

Changed the first sentence in section 2.9, External Bus Interface, to: The 54x can address up to 64K words of data memory, 64K words of program memory (8M words in the 548, 549, and 5410; 1M words in the 5402; 256K words in the 5420), and up to 64K words of 16-bit parallel I/O ports.
Summary of Updates in This Document
D-3

Summary of Updates in This Document

Page:
3-1

Changed or Added:
Changed the fourth sentence in the first paragraph to: In some devices, the memory structure has been modified through overlay and paging schemes to allow additional memory space.

3-2

Deleted the following sentence from the first paragraph in section 3.1, Memory Space: Together, these three spaces provide a total address range of 192K words (except in the 548, 549, 5402, 5410, and 5420). Changed the fourth paragraph to: There are three CPU status register bits that affect memory configuration. The effects of these bits are device-specific.

3-6 3-7 3-8 3-9 3-10 3-11 3-12

Replaced Figure 34, Memory Maps for the 548, with an updated figure. Replaced Figure 35, Memory Maps for the 549, with an updated figure. Added Figure 36, Extended Program Memory Maps for the 548 and 549. Added Figure 37, Memory Maps for the 5402. Added Figure 38, Extended Program Memory for the 5402. Added Figure 39, Memory Maps for the 5410. Added Figure 310, Extended Program Memory Maps for the 5410 (On-chip RAM Not Mapped in Program Space and Data Space, OVLY = 0). Added Figure 311, Extended Program Memory Maps for the 5410 (On-chip RAM Mapped in Program Space and Data Space, OVLY = 1).

3-13

Added Figure 312, Data Memory Map for the 5420 Relative to CPU Subsystems A and B. Added Figure 313, Program Memory Maps for the 5420 Relative to CPU Subsystems A and B. Changed the first sentence in section 3.2, Program Memory, to: The external program memory on the 54x devices (except on the 548, 549, 5402, 5410, and 5420) addresses up to 64K 16-bit words.

3-14

3-15

D-4

Summary of Updates in This Document

Page:
3-15

Changed or Added:
Added the following information to Table 31, On-Chip Program Memory Available on the TMS320C54x Devices:
Device 5402 5410 5420 ROM (MP/MC = 0) 4K 16K DARAM (OVLY = 1) 16K 8K 32K SARAM (OVLY = 1) 56K 168K

3-17

Added ROM blocks for the 5402 and 5410 in Figure 314, On-Chip ROM Block Organization. Changed the first paragraph in section 3.2.4, On-Chip ROM Code Contents and Mapping, to: The 54x devices (except 5420) provide a variety of ROM sizes (4K, 16K, 24K, 28K, or 48K words). On 54x devices with on-chip bootloader ROM, the 2K words (at F800h to FFFFh) may contain one or more of the following, depending on the specific device:

3-18

3-19

Changed the label above the memory map on the right to:
542/543/548/549/5402/5410

Changed the description at address FF00h in both memory maps to:

Reserved

3-20

Moved the contents of section 3.1.1 to section 3.2.5 and changed the heading to: Extended Program Memory (Available on 548/549/5402/5410/5420) Changed the first paragraph to: The 548, 549, 5402, 5410, and 5420 use a paged extended memory scheme in program space to allow access of up to 8192K words of program memory. To implement this scheme, the 548, 549, 5402, 5410, and 5420 include several additional features: Changed the first bulleted statement to:

23 address lines, instead of 16 (20 address lines in the 5402, and 18 in the 5420)
Summary of Updates in This Document
D-5

Summary of Updates in This Document

Page:
3-20

Changed or Added:
Changed the second paragraph to: Program memory in the 548, 549, 5402, 5410, and 5420 is organized into 128 pages (16 pages in the 5402, and 4 in the 5420) that are each 64K words in length, as shown in Figure 316.

3-21

Changed the sentence above the first bulleted list to: To facilitate page switching through software, the 548, 549, 5402, 5410, and 5420 have six special instructions that affect the XPC: Changed the sentence above the second bulleted list to: The following two 54x instructions are extended in the 548, 549, 5402, 5410, and 5420 to use 23 bits (20 bits in the 5402, and 18 in the 5420):

3-22

Added the following information to Table 32, On-Chip Data Memory Available on the TMS320C54x Devices:
Device 5402 5410 5420 Program/Data ROM (DROM = 1) 4K 16K DARAM 16K 8K 32K SARAM 56K 168K

3-23

Changed the second paragraph in section 3.3.2 to: The organization of the first 1K of DARAM on all 54x devices includes the memory-mapped CPU and peripheral registers, 32 words of scratch-pad DARAM, and 896 words of DARAM.

3-25 3-26

Added Figure 319, On-Chip RAM Block Organization (5402/5410/5420) Changed the first bullet as follows:

The peripheral registers are used as control and data registers in peripheral circuits. These registers reside within addresses 0020h005F and reside on a dedicated peripheral bus structure. For a list of peripherals on a particular 54x device, see section 8.2, Peripheral Memory-Mapped Registers, on page 8-2.

D-6

Summary of Updates in This Document

Page:
3-27

Changed or Added:
Changed the XPC description at address 1E in Table 33, CPU Memory-Mapped Registers, to:
Address 1E Name XPC Description Program counter extension register (548, 549, 5402, 5410, and 5420)

3-29

Changed the heading of section 3.3.4.11 to:

Program Counter Extension Register (XPC, Available on 548/549/5402/ 5410/5420)

4-6 to 4-8 Changed the note below Figure 43 and Table 43 to:
Refer to the device-specific datasheet to determine if these bits are supported.

5-6

Changed the second sentence in the note at the bottom of the page to: However, because the 548, 549, and 5410 have 23 address lines (20 address lines in the 5402, and 18 in the 5420), the program-memory location in these devices is specified by the lower 23 bits of accumulator A.

6-2

Changed the second and third sentences of the first paragraph to: The 54x can address a total of 64K words of program memory using the program address bus (PAB). Table 61 shows devices that have additional program memory address lines that provide external access to as many as 128 64K-word pages. Added Table 61, Devices With Additional Program Memory Address Lines. Changed the sentence below the fifth bulleted item to: One additional register is used in the 548, 549, 5402, 5410, and 5420 to address extended memory:

6-5

Changed the first sentence in the first paragraph to: XPC is a 7-bit register that selects the extended page of program memory for the 548, 549, 5402, 5410, and 5420. For more information about extended program memory in these devices, see section 3.1.1, Extended Program Memory, on page 3-10.

6-8

Changed the heading of section 6.3.3 to: Far Branches (Available on TMS320C548/549/5402/5410/5420)
Summary of Updates in This Document
D-7

Summary of Updates in This Document

Page:
6-8

Changed or Added:
Changed the first sentence of section 6.3.3 to: To allow branches to extended memory, the 548, 549, 5402, 5410, and 5420 include two far branch instructions: Changed the bulleted list to:

FB[D] branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified by the the instruction. FBACC[D] branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified in the designated accumulator.

Changed the first sentence under the bulleted list to: Table 66 shows the far branch instructions in the 548, 549, 5402, 5410, and 5420 (both nondelayed and delayed) and the number of cycles needed to execute these instructions. 6-11 Changed the heading of section 6.4.3 to: Far Calls (Available on TMS320C548/549/5402/5410/5420) Changed the first sentence in section 6.4.3 to: To allow calls to extended memory, the 548, 549, 5402, 5410, and 5420 include two far call instructions: Changed the bulleted list to:

The FCALL instruction pushes XPC onto the stack, pushes PC onto the stack, and branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified by the the instruction. The FCALA pushes XPC onto the stack, pushes PC onto the stack, and branches to the 23-bit address (20-bit addresses in the 5402 and 18-bit addresses in the 5420) specified in the designated accumulator.

Changed the first sentence of the paragraph below the bulleted list to: Table 69 shows the far call instructions in the 548, 549, 5402, 5410, and 5420 (nondelayed and delayed) and the number of cycles needed to execute these instructions. 6-12 Changed the second paragraph in section 6.5, Returns, to: The 548, 549, 5402, 5410, and 5420 offer an additional return instruction: an unconditional far return, both nondelayed and delayed.
D-8

Summary of Updates in This Document

Page:
6-14

Changed or Added:
Changed the heading of section 6.5.3 to: Far Returns (Available on TMS320C548/549/5402/5410/5420) Changed the first sentence in section 6.5.3 to: To allow returns from extended memory, the 548, 549, 5402, 5410, and 5420 include two far return instructions:

6-15

Changed the first sentence to: Table 612 shows the far return instructions in the 548, 549, 5402, 5410, and 5420 (nondelayed and delayed) and the number of cycles needed to execute these instructions.

6-25

Changed the fifth bulleted item to:

6-29

XPC is cleared (548, 549, 5402, 5410, and 5420)

Added the following registers to Figure 62, Interrupt Flag Register (IFR) Diagram:

(h) 5402 IFR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

INT3

TINT1 or DMAC0 BXINT0 BRINT0 TINT0 DMAC1

(i) 5410 IFR

15 14 13 12 11 10 9 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

(j) 5420 IFR

15 14 13 12 11 10 9 8 RSVD 7 6 5 4 3 TINT 2 RSVD 1 INT1 0 INT0

Resvd

IPINT DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

Summary of Updates in This Document

D-9

Summary of Updates in This Document

Page:
6-30

Changed or Added:
Added the following registers to Figure 63, Interrupt Mask Register (IMR) Diagram:

(h) 5402 IMR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

INT3

TINT1 or DMAC0 BXINT0 BRINT0 TINT0 DMAC1

(i) 5410 IMR

15 14 13 12 11 10 9 8 INT3 7 6 5 4 3 TINT 2 INT2 1 INT1 0 INT0

Resvd

DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

(j) 5420 IMR

15 14 13 12 11 10 9 8 RSVD 7 6 5 4 3 TINT 2 RSVD 1 INT1 0 INT0

Resvd

IPINT DMAC5 DMAC4

BXINT1 BRINT1 or or HPINT DMAC3 DMAC2

BXINT2 BRINT2 or or BXINT0 BRINT0 DMAC1 DMAC0

6-33

Added the following note: Note: The program counter extension register, XPC, does not get pushed to the top of the stack; that is, it does not get saved on the stack. Therefore, if an ISR is located on a different page from the vector table, you must push the XPC on the stack prior to branching to the ISR. A FRET [E] can be used to return from the ISR.

6-45 6-46 6-48

Added Table 626, 5402 Interrupt Locations and Priorities. Added Table 627, 5410 Interrupt Locations and Priorities. Added Table 628, 5420 Interrupt Locations and Priorities.

D-10

Summary of Updates in This Document

Page:
7-27

Changed or Added:
Added the following information to Table 71, DARAM Blocks:
Device 5402 5410 5420 (each subsystem) Block Size 8K words 2K words 8K words Number of Blocks 2 4 2

8-1

Added the following second paragraph: Enhanced peripherals, available on specific 54x devices, are not discussed at length in this chapter. For detailed information on the enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

8-2

Added section 8.1, Available On-chip Peripherals, and inserted the bulleted list of peripherals from page 1. Changed the fourth bulleted item to:

Host port interface 8-bit standard (542, 545, 548, 549) 8-bit enhanced (5402, 5410 see note below) 16-bit enhanced (5420 see note below)

J J J

Added the seventh bulleted item:

Multichannel buffered serial port (McBSP) (5402, 5410, and 5420 see note below)

Added the following note below the bulleted list: Note: Enhanced Peripherals

For more detailed information on the enhanced peripherals, see volume 5 of this reference set: TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302. Deleted the following sentence from the second paragraph in section 8.2, Peripheral Memory-Mapped Registers: Note that all accesses to memory-mapped peripheral registers require two machine cycles.
Summary of Updates in This Document
D-11

Summary of Updates in This Document

Page:
8-3 8-4

Changed or Added:
Deleted the figure titled TMS320C54x Peripheral Memory Mapped Registers. Added registers for the 5402, 5410, and 5420 devices to Figure 81, TMS320C54x Peripheral Memory-Mapped Registers. Added Table 88, 5402 Peripheral-Memory Mapped Registers. Added Table 89, 5410 Peripheral-Memory Mapped Registers. Added Table 810, 5420 Peripheral-Memory Mapped Registers. Added Table 811, 5402/5410/5420 McBSP Sub-addressed Registers. Added Table 812, 5402/5410/5420 DMA Sub-addressed Registers. Deleted the following sentence from section 8.3, General-Purpose I/O: For more information about the I/O memory space and accesses using the external bus, see section 3.4, I/O Memory, on page 3-27, and chapter 10, External Bus Operation. Deleted the figure titled BIO Timing Diagram.

8-11 8-13 8-15 8-17 8-18 8-20

8-21

Deleted the last sentence of the paragraph in section 8.4, Timer, and added the following: The timer resolution is the CPU clock rate of the processor.The high dynamic range of the timer is achieved with a 16-bit counter with a 4-bit prescaler. The 5402 and the 5420 have two on-chip timers.

8-23

Changed the second sentence of the first paragraph to: The timer is driven by a prescaler that is decremented by 1 at every CPU clock cycle. Changed the last sentence of the second paragraph to: The timer is clocked by the CPU clock. Changed Figure 83, Timer Block Diagram, to show that the timer is clocked by the CPU clock. Added the following note to the bottom of the page:
Note that on the 5402, the timer1 output (TOUT1) is only available when the HPI-8 is disabled, and the TOUT1 bit is set in the GPIO control register.

D-12

Summary of Updates in This Document

Page:
8-24

Changed or Added:
Changed the sixth and seventh sentences of the first paragraph to: PSC is clocked by the device CPU clock. Each CPU clock decrements PSC by 1. Changed the sentence above the equation to: The timer interrupt (TINT) rate is equal to the CPU clock frequency divided by two independent factors: Changed the sentence below the equation to: In the equation, tc(C) is the period of CPU clock, u is the sum of the TDDR contents plus 1, and v is the sum of the PRD contents plus 1. Changed timer initialization step number three to: Start the timer by reloading TCR to initialize TDDR. Enable the timer by setting TSS to 0 and TRB to 1 to reload the timer period. Added the following note to the bottom of the page:
Note that on the 5402, the timer1 output (TOUT1) is only available when the HPI-8 is disabled, and the TOUT1 bit is set in the GPIO control register.

8-26

Changed the first bulleted item to:

A crystal resonator with the internal oscillator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the 54x. The CLKMD pins must be configured to enable the internal oscillator.

Changed the last sentence in the paragraph under the bulleted list to: The 541B, 545A, 546A, 548, 549, 5402, 5410, and 5420 devices use a software-programmable PLL. 8-27 Replaced all references to internal source with oscillator enabled in Table 815, Clock Mode Configurations. Changed the heading of section 8.5.2 to: Software-Programmable PLL (541B/545A/546A/ 548/549/5402/5410/5420) Added the following note below the last paragraph:
The VC5420 device does not have CLKMD pins. Following reset, the 5420 operates in bypass mode (PLL is off).

Summary of Updates in This Document

D-13

Summary of Updates in This Document

Page:
8-28

Changed or Added:
Changed the clock mode descriptions at 4000h and 7000h in Table 816, Clock Mode Setting at Reset (541B/545A/546A/548/549/5410), to:
CLKMD1 1 1 CLKMD CLKMD2 CLKMD3 Reset Value 0 1 0 1 4000h 7000h Clock Mode Divide-by-2, internal oscillator enabled Divide-by-2, internal oscillator enabled{

Changed the note below Table 816 to:

Reserved on 549 and 5410

Added Table 817, Clock Mode Settings at Reset (5402). 8-31 Added the following note below Table 819, Pll Multiplier ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL:
This is the default mode for the 5420 after reset.

8-32

Changed the 549 Only note referencing the graph in Figure 87, PLL Lockup Time Versus CLKOUT Frequency, to: 549, and 5410

8-33

Changed the first and second sentences of the third paragraph under Switching Clock Mode From PLL Mode to DIV Mode to: The switch to DIV mode takes effect in 6 CLKIN cycles plus 3.5 PLL cycles for all PLLMUL values except 1111b. For a PLLMUL value of 1111b, the switch to DIV mode takes effect in 12 CLKIN cycles plus 3.5 PLL cycles.

8-34

Changed the second sentence of the paragraph under the numbered list to: When the PLLCOUNT timer reaches 0, the new PLL mode takes effect after 6 CLKIN cycles plus 3.5 PLL cycles.

8-37

Changed the first sentence in section 8.6, Host Port Interface, to: The standard host port interface (HPI) is available on the 542, 545, 548, and 549 devices.

D-14

Summary of Updates in This Document

Page:
8-37

Changed or Added:
Added the following second paragraph: Enhanced host port interfaces are available on the 5402, 5410 (HPI-8) and 5420 (HPI-16) devices. This chapter does not describe these enhanced HPIs. For more information on the HPI-8 and HPI-16, see volume 5 of this reference set, TMS320C54x DSP, Enhanced Peripherals, literature number SPRU302.

9-1

Added the third bulleted item:

9-2

Multichannel buffered serial Port (McBSP) interface

Added the following information to Table 91, Serial Ports on the TMS320C54x Devices:
Standard Synchronous Serial Ports 0 0 0 Buffered Serial Ports 0 0 0 Multichannel Buffered Serial Ports 2 3 6 Time-Division Multiplexed Serial Ports 0 0 0

Device 5402 5410 5420

9-3

Added the following reference to Table 92, Sections that Cover the Serial Ports:
Serial Port MCBSP Mode Multichannel See . . . TMS320C54x DSP Enhanced Peripherals Volume 5 (literature number SPRU302)

9-4

Changed the first paragraph to: Four different types of serial port interfaces are available on 54x devices. The basic standard serial port interface is implemented on 541, 545, and 546 devices. The TDM serial port interface is implemented on the 542, 543, 548, and 549 devices. The 542, 543, 545, 546, 548, and 549 devices include a buffered serial port (BSP) that implements an automatic buffering feature, which greatly reduces CPU overhead required in handling serial data transfers. The 5402, 5410, and 5420 devices include multichannel buffered serial ports (McBSPs). See Table 91 for information about the features included in various 54x devices.

Summary of Updates in This Document

D-15

Summary of Updates in This Document

Page:
10-1

Changed or Added:
Added the following paragraph: The 5410 enhanced external parallel interface (XIO) is not described in this chapter. See the 5410 datasheet for details about the external memory interface.

10-2

Added signal names and descriptions for the 5402, 5410, and 5420 devices to Table 101, Key External Interface Signals, as follows:

Signal Name A0A15 D0D15 MSTRB PS DS IOSTRB IS R/W READY HOLD HOLDA MSC IAQ IACK

548, 549 5410 220 150

5402 190 150

5420 Description 170 150 Address bus Data bus External memory access strobe Program space select Data space select I/O access strobe I/O space select Read/write signal Data ready to complete cycle Hold request Hold acknowledge Micro state complete Instruction acquisition Interrupt acknowledge

n n n n n n n n n n n n

n n n n n n n n n n n n

n n n n n n n

10-3

Added the following paragraph: When the CPU addresses external data or I/O space, the extended address lines are driven to logic 0. This is also the case when the CPU addresses internal memory with the AVIS (address visibility) set to 1.

D-16

Summary of Updates in This Document

Page:
10-5

Changed or Added:
Changed the first sentence in the first paragraph in section 10.3.1, Wait State Generator, to: The software-programmable wait-state generator can extend external bus cycles by up to seven machine cycles (14 machine cycles on 549, 5402, 5410, and 5420 devices), providing a convenient means to interface the 54x to slower external devices. Added the following sentence to the third paragraph in section 10.3.1, Wait State Generator,: The SWWSR bit fields of the 548, 549, 5402, 5410, and 5420 are described in Table 103. Changed the note below Figure 102, Software Wait-State Register (SWWSR) Diagram, to:
XPA bit on 548, 549, 5402, 5410, and 5420 only

10-6

Changed the title of Figure 103 to Software Wait-State Register (SWWSR) Bit Summary, and changed the figure as follows:
15 XSWWR Reserved 1 SWSM 0

Added the second paragraph below Figure 103, Software Wait-State Register (SWWSR) Bit Summary, as follows: The 549, 5402, 5410, and 5420 have an extra bit (software wait-state multiplier, SWSM) that resides in SWCR, which is memory mapped to address 002Bh in data space. 10-7 Changed the title of Table 103 to:

548/549/5402/5410/5420 Software Wait-State Register (SWWSR) Bit Summary

10-9
1512 BNKCMP
R/W

Changed Figure 105, Bank-Switching Control Register (BSCR) Diagram, as follows:

11 PS DS
R/W

109 Reserved

8 IPIRQ
R/W

73 Reserved

2 HBH
R/W

1 BH
R/W

0 EXIO
R/W

Summary of Updates in This Document

D-17

Summary of Updates in This Document

Page:
10-9

Changed or Added:
Changed the name and function descriptions in Table 105, Bank-Switching Control Register (BSCR) Bit Summary, as follows:
Bit 11 Name PSDS Reset Value Function Program read-data read access. Inserts an extra cycle between consecutive accesses of program read and data read, or data read and program read. PSDS = 0 PSDS = 1 No extra cycles are inserted by this feature except when banks are crossed. One extra cycle is inserted between consecutive accesses of program read and data read, or data read and program read.

109 8 73 2

Reserved IPIRQ Reserved HBH

These bits are reserved. Interprocessor interrupt request bit. These bits are reserved. HPI bus holder bit.

10-11

Changed the first signal designation in Table 107, State of Signals When External Interface is Disabled (EXIO=1), to:
Signal A(220) State Previous state

10-12

Changed the third bulleted item to:

10-15

A program-memory read followed by another program-memory read from a different page (with the 548, 549, 5402, 5410, and 5420).

Changed Figure 108, Memory Interface Operation for Read-Read-Write, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 109, Memory Interface Operation for Write-Write-Read, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed the last sentence to: However, the write, which is already two cycles, is extended to three cycles.

10-16

10-17

D-18

Summary of Updates in This Document

Page:
10-17

Changed or Added:
Changed Figure 1010, Memory Interface Operation for Read-Read-Write (ProgramSpace Wait States), to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1011, Parallel I/O Interface Operation for Read-Write-Read, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1012, Parallel I/O Operation for Read-Write-Read (I/O-Space Wait States), to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1013, Memory Read and I/O Write, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1014, Memory Read and I/O Read, to show Address as the designation for the second timing event, and Data as the designation for the third timing event.

10-18

10-19

10-20

10-21

Changed Figure 1015, Memory Write and I/O Write, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1016, Memory Write and I/O Read, to show Address as the designation for the second timing event, and Data as the designation for the third timing event.

10-22

Changed Figure 1017, I/O Write and Memory Write, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1018, I/O Write and Memory Read, to show Address as the designation for the second timing event, and Data as the designation for the third timing event.

10-23

Changed Figure 1019, I/O Read and Memory Write, to show Address as the designation for the second timing event, and Data as the designation for the third timing event. Changed Figure 1020, I/O Read and Memory Read, to show Address as the designation for the second timing event, and Data as the designation for the third timing event.

10-25

Changed Figure 1021, External Bus Reset Sequence, to show Address as the designation for the third timing event, and Data as the designation for the fourth timing event. Changed Figure 1023, HOLD and HOLDA Minimum Timing for HM = 0, to show Address as the designation for the fourth timing event, and Data as the designation for the fifth timing event.

10-30

Summary of Updates in This Document

D-19

Summary of Updates in This Document

Page:
10-31

Changed or Added:
Changed Figure 1024, HOLD and RS Interaction, to show Address as the designation for the fifth timing event, and Data as the designation for the sixth timing event in each of the four figures. Added the following description below the Figure 24 caption for each of the four figures: (a) Hold is Asserted While Reset is Active and De-asserted While Reset is Active (b) Hold is Asserted While Reset is Active and De-asserted While Reset is Inactive (c) Hold is Asserted and De-asserted While Reset is Inactive (d) Hold is Asserted While Reset is Inactive and De-asserted While Reset is Active

A-8

Replaced Example B2, Key Timing for a Single- or Multiple-Processor System With Buffered Input and Output, with an updated version. Replaced Figure B1, TMS320 DSP Device Nomenclature, with an updated version.

B-7

D-20

Appendix E Appendix A

Glossary
A
A: See accumulator A. ABU: See autobuffering unit. ABUC: ABU control register. A register that controls the operation of the autobuffering unit. accumulator: A register that stores the results of an operation and provides an input for subsequent arithmetic logic unit (ALU) operations. accumulator A: 40-bit register that stores the result of an operation and provides an input for subsequent arithmetic logic unit (ALU) operations. accumulator B: 40-bit registers that stores the result of an operation and provides an input for subsequent arithmetic logic unit (ALU) operations. accumulator shift mode field (ASM): A 5-bit field in status register 1 (ST1) that specifies a shift value (from 16 to 15) used to shift an accumulator value when executing certain instructions, such as instructions with parallel loads and stores. adder: A unit that adds or subtracts two numbers. address: The location of a word in memory. address bus: A group of connections used to route addresses. The 54x has four 16-bit address busses: CAB, DAB, EAB, and PAB. addressing mode: The method by which an instruction calculates the location of an object in memory. address visibility mode (AVIS): A bit in processor mode status register (PMST) that determines whether or not the internal program address appears on the devices external address bus pins. AG: accumulator guard bits. An 8-bit register that contains bits 3932 (the guard bits) of accumulator A.
E-1

Glossary

AH: accumulator A high word. Bits 3116 of accumulator A. AL: accumulator A low word. Bits150 of accumulator A. ALU: arithmetic logic unit. The part of the CPU that performs arithmetic and logic operations. analog-to-digital (A/D) converter: Circuitry that translates an analog signal to a digital signal. AR0AR7: auxiliary registers 07. Eight 16-bit registers that can be accessed by the CPU and modified by the auxiliary register arithmetic units (ARAUs) and are used primarily for data memory addressing. ARAU: See auxiliary register arithmetic unit. ARP: See auxiliary register pointer. ARR, ARR0, ARR1: ABU address receive register A 16-bit register that specifies the destination address at which the autobuffering unit begins storing received data. ASM: See accumulator shift mode field. autobuffering receiver enable (BRE): A bit in the BSP control extension register (BSPCE) that enables/disables the autobuffering receiver. autobuffering receiver halt (HALTR): A bit in the BSP control extension register (BSPCE) that enables/disables the autobuffer receiver when the current half of the buffer is received. autobuffering transmitter enable (BXE): A bit in the BSP control extension register (BSPCE) that enables/disables the autobuffering transmitter. autobuffering transmitter halt (HALTX): A bit in the BSP control extension extension (BSPCE) that enables/disables the autobuffer transmitter when the current half of the buffer has been transmitted. autobuffering unit: An extension to the synchronous serial port that reads and writes data to the synchronous serial port independent of the CPU. auxiliary register arithmetic unit: An unsigned, 16-bit arithmetic logic unit (ALU) used to calculate indirect addresses using auxiliary registers. auxiliary register file: The area in data memory containing the eight 16-bit auxiliary registers. See also auxiliary registers. auxiliary register pointer (ARP): A 3-bit field in status register 0 (ST0) used as a pointer to the currently-selected auxiliary register, when the device is operating in C5x/C2xx compatibility mode.
E-2

Glossary

auxiliary registers: Eight 16-bit registers (AR7 AR0) that are used as pointers to an address within data space. These registers are operated on by the auxiliary register arithmetic units (ARAUs) and are selected by the auxiliary register pointer (ARP). See also auxiliary register arithmetic unit. AVIS: See address visibility mode bit. AXR, AXR0, AXR1: ABU address transmit register. A 16-bit register that specifies the source address from which the autobuffering unit begins transmitting data.

B
B: See accumulator B. bank-switching control register (BSCR): A 16-bit register that defines the external memory bank size and enables or disables automatic insertion of extra cycles when accesses cross memory bank boundaries. barrel shifter: A unit that rotates bits in a word. BDRR, BDRR0, BDRR1: BSP data receive register. Two 16-bit registers used to receive data through the buffered serial ports. BDRR0 corresponds to buffered serial port 0 and BDRR1 corresponds to buffered serial port 1. BDXR, BDXR0, BDXR1: BSP data transmit register. Two 16-bit registers used to transmit data through the buffered serial ports. BDXR0 corresponds to buffered serial port 0 and BDXR1 corresponds to buffered serial port 1. BG: accumulator B guard bits. An 8-bit register that contains bits 3932 (the guard bits) of accumulator B. BH: accumulator B high word. Bits 3116 of accumulator B. BIO: A general purpose, branch-control, input pin that can be used to monitor the status of peripheral devices. BK: See circular buffer size register. BKR, BKR0, BKR1: ABU receive buffer size register. A 16-bit register that sets the size of the receive buffer for the autobuffering unit. BKX, BKX0, BKX1: ABU transmit buffer size register. A 16-bit register that sets the size of the transmit buffer for the autobuffering unit. BL: accumulator B low word. Bits 150 of accumulator B.
Glossary
E-3

Glossary

block-repeat active flag (BRAF): A bit in status register 1 (ST1) that indicates whether or not a block repeat is currently active. block-repeat counter (BRC): A 16-bit register that specifies the number of times a block of code is to be repeated when a block repeat is performed. block-repeat end address register (REA): A 16-bit memory-mapped register containing the end address of a code segment being repeated. block-repeat start address register (RSA): A 16-bit memory-mapped register containing the start address of a code segment being repeated. BMINT: See buffer misalignment interrupt. boot: The process of loading a program into program memory.

boot loader: A built-in segment of code that transfers code from an external source to program memory at power-up. BRAF: See block-repeat active flag. BRC: See block-repeat counter. BRE: See autobuffering receiver enable. BRINT, BRINT0, BRINT1: See BSP receive interrupt. BRSR: BSP data receive shift register. A 16-bit register that holds serial data received from the BDR pin. See also BDRR. BSCR: See bank-switching control register. BSP: buffered serial port. An enhanced synchronous serial port that includes an autobuffering unit (ABU) that reduces CPU overhead in performing serial operations. BSP receive interrupt (BRINT, BRINT0, BRINT1): A bit in the interrupt flag register (IFR) that indicates the BSP data receive shift register (BRSR) contents have been copied to the BSP data receive register (BDRR). BRINT0 corresponds to buffered serial port 0 and BRINT1 corresponds to buffered serial port 1. BSP transmit interrupt (BXINT, BXINT0, BXINT1): A bit in the interrupt flag register (IFR) that indicates the the BSP data transmit register (BDXR) contents has been copied to the BSP data transmit shift register (BXSR). BXINT0 corresponds to buffered serial port 0 and BXINT1 corresponds to buffered serial port 1. BSPC, BSPC0, BSPC1: Buffered serial port control registers 0 and 1. A 16-bit register that contains status and control bits for the buffered serial port. BSPC0 corresponds to buffered serial port 0 and BSPC1 corresponds to buffered serial port 1.
E-4

Glossary

BSPCE, BSPCE0, BSPCE1: BSP control extension register. A 16-bit register that contains status and control bits for the buffered serial port (BSP) interface. The 10 LSBs of the BSPCE are dedicated to serial port interface control, whereas the 6 MSBs are used for autobuffering unit (ABU) control. buffer misalignment interrupt (BMINT): A 549 feature that detects potential error conditions and indicates lost words on a serial port interface. burst mode: A synchronous serial port mode in which a single word is transmitted following a frame synchronization pulse (FSX and FSR). butterfly: A kernel function for computing an N-point fast Fourier transform (FFT), where N is a power of 2. The combinational pattern of inputs resembles butterfly wings. BXE: See autobuffering transmitter enable. BXSR: BSP data transmit shift register. A 16-bit register that holds serial data to be transmitted from the BDX pin. See also BDXR.

C
C: See carry bit. C16: A bit in status register 1 (ST1) that determines whether the ALU operates in dual 16-bit mode or in double-precision mode. CAB: C address bus. A bus that carries addresses needed for accessing data memory. carry bit (C): A bit in status register 0 (ST0) used by the ALU in extended arithmetic operations and accumulator shifts and rotates. The carry bit can be tested by conditional instructions. CB: C bus. A bus that carries operands that are read from data memory. circular buffer size register (BK): A 16-bit register used by the auxiliary register arithmetic units (ARAUs) to specify the data-block size in circular addressing. CLKDV: See internal transmit clock division factor. CLKP: See clock polarity. CLKOUT off (CLKOFF): A bit in processor mode status register (PMST) that enables/disables the CLKOUT output.
Glossary
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Glossary

clock generator: A device consisting of an internal oscillator and a phaselocked loop (PLL) circuit driven internally by a crystal resonator with the internal oscillator, or externally by a clock source. clock mode (MCM): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that specifies the source of the clock for CLKX. clock polarity (CLKP): A bit in the BSP control extension register (BSPCE) that indicates when the data is sampled by the receiver and sent by the transmitter. CMPT: See compatibility mode. code: A set of instructions written to perform a task; a computer program or part of a program. cold boot: The process of loading a program into program memory at power-up. compare, select, and store unit (CSSU): An application-specific hardware unit dedicated to add/compare/select operations of the Viterbi operator. compatibility mode (CMPT): A bit in status register 1 (ST1) that determines whether or not the auxiliary register pointer (ARP) is used to select an auxiliary register in single indirect addressing mode. compiler mode (CPL): A bit in status register 1 (ST1) that determines whether the CPU uses the data page pointer or the stack pointer to generate data memory addresses in direct addressing mode. continuous mode: A synchronous serial port mode in which only one frame synchronization pulse (FSX and FSR) is necessary to transmit several packets at maximum frequency. CPL: See compiler mode. CSSU: See compare, select, and store unit.

D
DAB: D address bus. A bus that carries addresses needed for accessing data memory. DAB address register (DAR): A register that holds the address to be put on the DAB to address data memory for reads via the DB. DAGEN: See data-address generation logic (DAGEN).
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Glossary

DAR: See DAB address register. DARAM: dual-access RAM. Memory that can be accessed twice in the same clock cycle. data address bus: A group of connections used to route data memory addresses. The 54x has three 16-bit buses that carry data memory addresses: CAB, DAB, and EAB. data-address generation logic (DAGEN): Logic circuitry that generates the addresses for data memory reads and writes. See also programaddress generation logic (PAGEN). data bus: A group of connections used to route data. The 54x has three 16-bit data buses: CB, DB, and EB. data memory: A memory region used for storing and manipulating data. Addresses 00h1Fh of data memory contain CPU registers. Addresses 20h5Fh of data memory contain peripheral registers. data page pointer (DP): A 9-bit field in status register 0 (ST0) that specifies which of 512, 128 16 word pages is currently selected for direct address generation. DP provides the nine MSBs of the data-memory address; the dma provides the lower seven. See also dma. data ROM (DROM): A bit in processor mode status register (PMST) that determines whether or not part of the on-chip ROM is mapped into data space. DB: D bus. A bus that carries operands that are read from data memory. digital loopback mode: A synchronous serial port test mode in which the DLB bit connects the receive pins to the transmit pins on the same device to test if the port is operating correctly. digital loopback mode (DLB) bit: A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that puts the serial port in digital loopback mode. digital-to-analog (D/A) converter: Circuitry that translates a digital signal to an analog signal. direct data-memory address bus: A 16-bit bus that carries the direct address for data memory. direct memory address (dma, DMA) : The seven LSBs of a direct-addressed instruction that are concatenated with the data page pointer (DP) to generate the entire data memory address. See also data page pointer.
Glossary
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Glossary

dma: See direct memory address. DP: See data page pointer. DRB: direct data-memory address bus. A 16-bit bus that carries the direct address for data memory. DROM: See data ROM. DRR, DRR0, DRR1: serial port data receive register. Two 16-bit registers used to receive data through the synchronous serial ports. DRR0 corresponds to synchronous serial port 0 and DRR1 corresponds to synchronous serial port 1. DSP interrupt (DSPINT): A bit in the HPI control register (HPIC) that enables/disables an interrupt from a host device to the 54x. DXR, DXR0, DXR1: serial port data transmit register. Two 16-bit registers used to transmit data through the synchronous serial ports. DXR0 corresponds to synchronous serial port 0 and DXR1 corresponds to synchronous serial port 1.

E
EAB: E address bus. A bus that carries addresses needed for accessing data memory. EAB address register (EAR): A register that holds the address to be put on the EAB to address data memory for reads via the EB. EB: E bus. A bus that carries data to be written to memory. exponent encoder (EXP): A hardware device that computes the exponent value of the accumulator. external interrupt: A hardware interrupt triggered by a pin (INT0INT3).

F
fast Fourier transform (FFT): An efficient method of computing the discrete Fourier transform, which transforms functions between the time domain and frequency domain. The time-to-frequency domain is called the forward transform, and the frequency-to-time domain is called the inverse transformation. See also butterfly. fast return register (RTN): A 16-bit register used to hold the return address for the fast return from interrupt (RETF[D]) instruction.
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Glossary

FE: See format extension. FIG: See frame ignore. format (FO): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that specifies the word length of the serial port transmitter and receiver. format extension (FE): A bit in the BSP control extension register (BSPCE) used in conjunction with the format bit (FO) to specify the word length of the BSP serial port transmitter and receiver. frame ignore (FIG): A bit in the BSP control extension register (BSPCE) used only in transmit continuous mode with external frame and in receive continuous mode. frame synchronization mode (FSM): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that specifies whether frame synchronization pulses (FSX and FSR) are required for serial port operation. frame synchronization polarity (FSP): A bit in the BSP control extension register (BSPCE) that determines the status of the frame synchronization (FSX and FSR) pulses. fractional mode (FRCT): A bit in status register 1 (ST1) that determines whether or not the multiplier output is left-shifted by one bit. Free bit: A bit in the serial port control register (SPC), buffered serial port control register (BSPC), timer control register (TCR), and TDM serial port control register (TSPC) used in conjunction with the Soft bit to determine the state of the serial port or timer clock when a breakpoint is encountered in the high-level language debugger. See also Soft bit. FSM: See frame synchronization mode. FSP: See frame synchronization polarity.

G
general-purpose input/output pins: Pins that can be used to supply input signals from an external device or output signals to an external device. These pins are not linked to specific uses; rather, they provide input or output signals for a variety of purposes. These pins include the generalpurpose BIO input pin and XF output pin.
Glossary
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Glossary

H
HALTR: See autobuffering receiver halt. HALTX: See autobuffering transmitter halt. hardware interrupt: An interrupt triggered through physical connections with on-chip peripherals or external devices. HINT: 54x-to-Host Processor Interrupt. A bit in the HPI control register (HPIC) that enables/disables an interrupt from the 54x to a host device. HM: See hold mode. hold mode (HM): A bit in status register ST1 that determines whether the CPU enters the hold state in normal mode or concurrent mode. host-only mode (HOM): The mode that allows the host to access HPI memory while the 54x is in IDLE2 (all internal clocks stopped) or in reset mode. host port interface (HPI): An 8-bit parallel interface that the CPU uses to communicate with a host processor. HPI address register (HPIA): A 16-bit register that stores the address of the host port interface (HPI) memory block. The HPIA can be preincremented or postincremented. HPI control register (HPIC): A 16-bit register that contains status and control bits for the host port interface (HPI).

I
IFR: See interrupt flag register. IMR: See interrupt mask register. IN0: input 0 bit. A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that allows the CLKR pin to be used as an input. IN0 reflects the current level of the CLKR pin of the device. IN1: input 1 bit. A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that allows the CLKX pin to be used as an input. IN1 reflects the current level of the CLKX pin of the device.
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Glossary

internal transmit clock division factor (CLKDV): A 5-bit field in the BSP control extension register (BSPCE) that determines the internal transmit clock duty cycle. interrupt: A condition caused by internal hardware, an event external to the CPU, or by a previously executed instruction that forces the current program to be suspended and causes the processor to execute an interrupt service routine corresponding to the interrupt. interrupt flag register (IFR): A 16-bit memory-mapped register that flags pending interrupts. interrupt mask register (IMR): A 16-bit memory-mapped register that masks external and internal interrupts. interrupt mode (INTM): A bit in status register 1 (ST1) that globally masks or enables all interrupts. interrupt service routine (ISR): A module of code that is executed in response to a hardware or software interrupt. IPTR: interrupt vector pointer A 9-bit field in the processor mode status register (PMST) that points to the 128-word page where interrupt vectors reside. IR: instruction register. A 16-bit register used to hold a fetched instruction.

L
latency: The delay between when a condition occurs and when the device reacts to the condition. Also, in a pipeline, the necessary delay between the execution of two instructions to ensure that the values used by the second instruction are correct. LSB: least significant bit. The lowest order bit in a word.

M
maskable interrupts: A hardware interrupt that can be enabled or disabled through software. McBSP: See multichannel buffered serial port. MCM: See clock mode. memory map: A map of the addressable memory space accessed by the 54x processor partitioned according to functionality (memory, registers, etc.).
Glossary
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Glossary

memory-mapped register (MMR): The 54x processor registers mapped into page 0 of the data memory space. microcomputer mode: A mode in which the on-chip ROM is enabled and addressable for program accesses. microprocessor/microcomputer (MP/MC): A bit in the processor mode status register (PMST) that indicates whether the processor is operating in microprocessor or microcomputer mode. See also microcomputer mode; microprocessor mode. microprocessor mode: A mode in which the on-chip ROM is disabled for program accesses. micro stack: A stack that provides temporary storage for the address of the next instruction to be fetched when the program address generation logic is used to generate sequential addresses in data space. MSB: most significant bit. The highest order bit in a word. multichannel buffered serial port (McBSP): High-speed, full duplexed, buffered serial ports that allow direct interface to other C54x devices, codecs, and other devices in a system. The McBSPs provide full-duplex communication, multi-buffered data registers, independent framing and clocking for receive and transmit, and a flexible clock generator that can be programmed for internal or external shift clocking. multiplier: A 17-bit 17-bit multiplier that generates a 32-bit product. The multiplier executes multiple operations in a single cycle and operates using either signed or unsigned 2s-complement arithmetic.

N
nested interrupt: A higher-priority interrupt that must be serviced before completion of the current interrupt service routine (ISR). An executing ISR can set the interrupt mask register (IMR) bits to prevent being suspended by another interrupt. nonmaskable interrupt: An interrupt that can be neither masked by the interrupt mask register (IMR) nor disabled by the INTM bit of status register 1 (ST1).

O
OVA: overflow flag A. A bit in status register0 (ST0) that indicates the overflow condition of accumulator A.
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Glossary

OVB: overflow flag B. A bit in status register 0 (ST0) that indicates the overflow condition of accumulator B. overflow: A condition in which the result of an arithmetic operation exceeds the capacity of the register used to hold that result. overflow flag: A flag that indicates whether or not an arithmetic operation has exceeded the capacity of the corresponding register. OVLY: See RAM overlay. OVM: overflow mode bit. A bit in status register 1 (ST1) that specifies how the ALU handles an overflow after an operation.

P
PAB: See program address bus. PAGEN: See program-address generation logic (PAGEN). PB: See program data bus. PC: See program counter. PCM: See pulse coded modulation mode. pipeline: A method of executing instructions in an assembly-line fashion. A 16-bit immediate program-memory

pmad: program-memory address. address.

PMST: processor mode status register. A 16-bit status register that controls the memory configuration of the device. See also ST0, ST1. pop: Action of removing a word from a stack.

PRD: timer period register. A 16-bit register that defines the period for the on-chip timer. program address bus (PAB): A 16-bit bus that provides the address for program memory reads and writes. program-address generation logic (PAGEN): Logic circuitry that generates the address for program-memory reads and writes, and the address for data memory in instructions that require two data operands. This circuitry can generate one address per machine. See also data-address generation logic (DAGEN).
Glossary
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Glossary

program address register (PAR): A register that holds the address to be put on the PAB to address memory for reads via the PB. program controller: Logic circuitry that decodes instructions, manages the pipeline, stores status of operations, and decodes conditional operations. program counter (PC): A 16-bit register that indicates the location of the next instruction to be executed. program counter extension register (XPC): A register that contains the upper 7 bits of the current program memory address. program data bus (PB): A bus that carries the instruction code and immediate operands from program memory. program memory: A memory region used for storing and executing programs. pulse coded modulation mode (PCM): A bit in the BSP control extension register (BSPCE) that enables/disables the BSP transmitter. push: Action of placing a word onto a stack.

R
RAM overlay (OVLY): A bit in the processor mode status register (PMST) that determines whether or not on-chip RAM is mapped into the program space in addition to data space. RC: See repeat counter. REA: See block-repeat end address. receive buffer half received (RH): A bit in the BSP control extension register (BSPCE) that indicates which half of the receive buffer has been received. receive ready (RRDY): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that transitions from 0 to 1 to indicate the data receive shift register (RSR) contents have been copied to the data receive register (DRR) and that data can be read. receiver reset (RRST): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that resets the serial port receiver. receive shift register full (RSRFULL): A bit in the serial port control register (SPC) and buffered serial port control register (BSPC) that indicates if the serial port receiver has experienced overrun.
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Glossary

register: A group of bits used for temporarily holding data or for controlling or specifying the status of a device. repeat counter (RC): A 16-bit register used to specify the number of times a single instruction is executed. reset: A means of bringing the CPU to a known state by setting the registers and control bits to predetermined values and signaling execution to start at a specified address. RH: See receive buffer half received. RINT, RINT0, RINT1: See serial port receive interrupt. RRDY: See receive ready. RRST: See receiver reset. RSA: See block-repeat start address. RSR: data receive shift register. A 16-bit register that holds serial data received from the DR pin. See also data receive register (DRR). RSRFULL: See receive shift register full. RTN: See fast return register.

S
SARAM: single-access RAM. Memory that can be read written once during one clock cycle. saturation on multiplication (SMUL): A bit in the processor mode status register (PMST) that determines whether saturation of a multiplication result occurs before performing the accumulation in a MAC or MAS instruction. saturation on store (SST): A bit in the processor mode status register (PMST) that determines whether saturation of the data from the accumulator occurs before storing in memory. serial port interface: An on-chip full-duplex serial port interface that provides direct serial communication to serial devices with a minimum of external hardware, such as codecs and serial analog-to-digital (A/D) and digital-to-analog (D/A) converters. Status and control of the serial port is specified in the serial port control register (SPC). serial port receive interrupt (RINT, RINT0, RINT1): A bit in the interrupt flag register (IFR) that indicates the data receive shift register (RSR) contents have been copied to the data receive register (DRR). RINT0 corresponds to synchronous serial port 0 and RINT1 corresponds to synchronous serial port 1.
Glossary
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Glossary

serial port transmit interrupt (XINT, XINT0, XINT1): A bit in the interrupt flag register (IFR) that indicates the the data transmit register (DXR) contents has been copied to the data transmit shift register (XSR). XINT0 corresponds to synchronous serial port 0 and XINT1 corresponds to synchronous serial port 1. shared-access mode (SAM): The mode that allows both the 54x and the host to access HPI memory. In this mode, asynchronous host accesses are synchronized internally and, in case of conflict, the host has access priority and the 54x waits one cycle. shared-access mode (SMOD): A bit in the HPI control register (HPIC) that enables/disables the shared access mode (SAM). See also sharedaccess mode (SAM) and host-only mode (HOM). shifter: A hardware unit that shifts bits in a word to the left or to the right. sign-control logic: Circuitry used to extend data bits (signed/unsigned) to match the input data format of the multiplier, ALU, and shifter. sign extension: An operation that fills the high order bits of a number with the sign bit. sign-extension mode (SXM): A bit in status register 1 (ST1) that enables sign extension in CPU operations. SMUL: See saturation on multiplication. Soft bit: A bit in the serial port control register (SPC), buffered serial port control register (BSPC), timer control register (TCR), and TDM serial port control register (TSPC) used in conjunction with the Free bit to determine the state of the serial port or timer clock when a breakpoint is encountered in the high-level language debugger. See also Free bit. software interrupt (SINT): An interrupt caused by the execution of an INTR or TRAP instruction. software wait-state register (SWWSR): A 16-bit register that selects the number of wait states for the program, data, and I/O spaces of off-chip memory. SP: See stack pointer. SPC, SPC0, SPC1: serial port control register. A 16-bit register that contains status and control bits for the synchronous serial port. SPC0 corresponds to synchronous serial port 0 and SPC1 corresponds to synchronous serial port 1.
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Glossary

SST: See saturation on store. ST0: A 16-bit register that contains 54x status and control bits. See also PMST; ST1. ST1: A16-bit register that contains 54x status and control bits. See also PMST, ST0. stack: A block of memory used for storing return addresses for subroutines and interrupt service routines and for storing data. stack pointer (SP): A register that always points to the last element pushed onto the stack. SXM: See sign-extension mode.

T
TADD: TDM address. A single, bidirectional address line that identifies which devices on the four-wire serial bus should read in the data on the TDM data (TDAT) line. TC: test/control flag. A bit in status register 0 (ST0) that is affected by test operations. TCLK: TDM clock. A single, bidirectional clock line for TDM operation. TCR: timer control register. A 16-bit memory-mapped register that contains status and control bits for the on-chip timer. TCSR: TDM channel select register. A 16-bit memory-mapped register that specifies in which of the eight time slots (channels) a device on the four-wire serial bus is to transmit. TDAT: TDM data. A single, bidirectional line from which all TDM data is carried. TDM receive interrupt (TRINT): A bit in the interrupt flag register (IFR) that indicates the TDM data receive shift register (TRSR) contents have been copied to the TDM data receive register (TRCV). TDM transmit interrupt (TXINT): A bit in the interrupt flag register (IFR) that indicates the TDM data transmit register (TDXR) contents have been copied to the data transmit shift register (XSR). TDXR: TDM data transmit register. A 16-bit register used to transmit data through the TDM serial port. See also XSR.
Glossary
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Glossary

temporary register (T): A 16-bit register that holds one of the operands for multiply and store instructions, the dynamic shift count for the add and subtract instructions, or the dynamic bit position for the bit test instructions. TIM:

timer counter register. A 16-bit memory-mapped register that specifies the current count for the on-chip timer.

time-division multiplexed (TDM): A bit in the TDM serial port control register (TSPC) that enables/disables the TDM serial port. time-division multiplexing: The process by which a single serial bus is shared by up to eight 54x devices with each device taking turns to communicate on the bus. There are a total of eight time slots (channels) available. During a time slot, a given device may talk to any combination of devices on the bus. timer divide-down register (TDDR): A 4-bit field in the timer control register (TCR) that specifies the timer divide-down ratio (period) for the on-chip timer. timer interrupt (TINT): A bit in the interrupt flag register (IFR) that indicates the timer counter register (TIM) has decremented past 0. timer prescaler counter (PSC): A 4-bit field in the timer control register (TCR) that specifies the count for the on-chip timer. timer reload (TRB): A bit in the timer control register (TCR) that resets the on-chip timer. timer stop status (TSS): A bit in the timer control register (TCR) that stops and restarts the on-chip timer. TINT: See timer interrupt. TRAD: TDM receive address register. A 16-bit memory-mapped register that contains information about the status of the TADD line in the TDM serial port. transition register (TRN): A 16-bit register that holds the transition decision for the path to new metrics to perform the Viterbi algorithm. transmit buffer half transmitted (XH): A bit in the BSP control extension register (BSPCE) that indicates which half of transmit buffer transmitted. transmit mode (TXM): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that specifies the source of the frame synchronization transmit (FSX) pulse.
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Glossary

transmit ready (XRDY): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that transitions from 0 to 1 to indicate the data transmit register (DXR) contents have been copied to the data transmit shift register (XSR) and that data is ready to be loaded with a new data word. transmit shift register empty (XSREMPTY): A bit in the serial port control register (SPC) and buffered serial port control register (BSPC) that indicates if the serial port transmitter has experienced underflow. transmitter reset (XRST): A bit in the serial port control register (SPC), buffered serial port control register (BSPC), and TDM serial port control register (TSPC) that resets the serial port transmitter. TRCV: TDM data receive register. A register used to receive data through the TDM serial port. TRINT: See TDM receive interrupt. TRN: See transition register. TRSR: TDM data receive shift register. A 16-bit register that holds serial data received from the TDM data (TDAT) line. See also TRCV. TRTA: TDM receive/transmit address register. The lower half of this register specifies the receive address of the device; the upper half of this register specifies the transmit address. TSPC: TDM serial port control register. A 16-bit memory-mapped register that contains status and control bits for the TDM serial port. TXINT: See TDM transmit interrupt.

TXM: See transmit mode.

W
wait state: A period of time that the CPU must wait for external program, data, or I/O memory to respond when reading from or writing to that external memory. The CPU waits one extra cycle (one CLKOUT1 cycle) for every wait state. warm boot: The process by which the processor transfers control to the entry address of a previously-loaded program.
Glossary
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Glossary

X
XF: A general purpose, software-controlled, external flag output pin that allows for signalling external devices. XF status flag: A bit in status register ST1 that indicates the status of the XF pin. XH: See transmit buffer half transmitted. XINT, XINT0, XINT1: See serial port transmit interrupt. XPC: See program counter extension. XRDY: See transmit ready. XRST: See transmitter reset. XSR: data transmit shift register. A 16-bit register that holds serial data to be transmitted from the DX pin (or TDX pin when TDM = 1). See also TDXR. XSREMPTY: See transmit shift register empty.

Z
ZA: zero detect A. A signal that indicates when accumulator A contains a 0. ZB: zero detect B. A signal that indicates when accumulator B contains a 0. zero detect: See ZA and ZB. zero fill: A method of filling the low- or high-order bits with zeros when loading a 16-bit number into a 32-bit field.

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Index

Index
*(lk) addressing 5-5 14-pin connector dimensions A-15 14-pin header header signals A-2 JTAG A-2 accumulator A high word (AH) definition E-2 accumulator A low word (AL) definition E-2 accumulator access no conflict 7-80 one-cycle latency 7-79 accumulator addressing 2-9, 5-1, 5-6 accumulator B 4-15 definition E-1 guard bits 3-27 high word 3-27 low word 3-27 accumulator B guard bits (BG) definition E-3 accumulator B high word (BH) definition E-3 accumulator B low word (BL) definition E-3 accumulator guard bits (AG) definition E-1 accumulator shift mode (ASM) 4-5 definition E-1 accumulator store with shift, example 4-16 accumulators 2-7, 4-15 to 4-17 application-specific instructions FIRS 4-17 LMS 4-17 SQDST 4-17 saturation 4-17 shift and rotate operations 4-16 rotate accumulator left 4-16 rotate accumulator left with TC 4-16 rotate accumulator right 4-16 shift arithmetically 4-16 shift conditionally 4-16 shift logically 4-16 storing contents 4-15

A
A/D converter definition E-2 absolute addressing 2-9, 5-1, 5-4 *(lk) 5-4 dmad 5-4 PA 5-4 pmad 5-4 ABU. See autobuffering unit ABU control register definition E-1 ABU receive address register (ARR) definition E-2 ABU receive buffer size register (BKR) definition E-3 ABU transmit address register (AXR) definition E-3 ABU transmit buffer size register (BKX) definition E-3 accessing DRAM blocks 7-28 accessing status registers latencies 7-60 accumulator definition E-1 accumulator A 4-15 definition E-1 guard bits 3-27 high word 3-27 low word 3-27

Index-1

Index

adder definition E-1 address definition E-1 address modification bit-reversed 5-18 circular 5-15 increment/decrement 5-14 indexed 5-15 offset 5-14 address visibility mode (AVIS) definition E-1 addresses buses addressing mode definition E-1 addressing modifications addressing program AG register AH register AL register 3-27 3-27 3-27 5-13, 5-19 3-18 to 3-20 2-3 4-7

ALU 2-7, 4-11 to 4-13 block diagram 4-11 carry bit (C) 4-13 input sources 4-11 X input source 4-11 Y input source 4-12 ALU input selection example ADD instruction, table 4-12 analog-to-digital converter definition E-2 application(s) automotive viii, xiii consumer viii, xiii development support viii, xiv general purpose viii medical viii, xiv speech/voice viii, x applications TMS320 family 1-3 4-17

application-specific instructions

AR0AR7 registers 3-27, 3-28 definition E-2 ARAU. See auxiliary register arithmetic unit ARAU and address-generation operation ARAUs definition E-2 Index-2 5-11

architectural overview 2-1 architecture 2-1 to 2-12 block diagram 2-2 bus structure 2-3 CPU 2-7 internal memory 2-5 arithmetic logic unit. See ALU arithmetic logic unit (ALU) carry bit (C) 4-13 definition E-2 X input source 4-11 Y input source 4-12 ARP See also auxiliary register pointer compatible mode 7-61 definition E-2 latencies 7-62 ARP load three-cycle latency 7-63 two-cycle latency 7-63 zero latency 7-63 ARR definition E-2 ARx updated with no latency example 7-48 ARx updated with one-cycle latency example 7-48 ARx updated with two-cycle latency example 7-49 ASM See also accumulator shift mode field definition E-1 ASM bit field latencies 7-70 ASM field shift operations 7-69 ASM update no latency 7-71 one-cycle latency 7-71 assistance B-4 autobuffering receiver enable (BRE) definition E-2 autobuffering receiver halt (HALTR) definition E-2 autobuffering transmitter enable (BXE) definition E-2 autobuffering transmitter halt (HALTX) definition E-2

Index

autobuffering unit (ABU) 9-40 block diagram 9-42 control register 9-43 definition E-2 process 9-45 circular addressing registers 9-47 automotive applications viii, xiii auxiliary register updating 7-38 auxiliary register file definition E-2 auxiliary register pointer (ARP) 4-2 definition E-2 auxiliary register-auxiliary register conflict example 7-40 auxiliary register-memory-mapped register conflict example 7-42 auxiliary registers 3-27, 5-18, 5-20 ARP indexes 5-23 definition E-3 AVIS See also address visibility mode definition E-1 AXR definition E-3

B
B. See accumulator B bank switching 2-12, 10-8 to 10-13 adding a cycle 10-13 BSCR 10-9 control register 10-9 field description 10-9 example 10-13 size 10-11 bank-switching control register (BSCR) BH bit 10-10 bit summary 10-9 BNKCMP bits 10-9 definition E-3 diagram 10-9 EXIO bit 10-10 PS-DS bit 10-9 barrel shifter E-3 See also shifter BDRR definition E-3

BDXR definition E-3 BG register 3-27 BH 10-10 BH register 3-27 BIO definition E-3 pin 8-20, E-9 bit-reversed addressing auxiliary register modifications 5-18 step/bit pattern relationship 5-19 BK 3-27, 3-28 See also circular buffer size register BKR definition E-3 BKX definition E-3 BL register 3-27 block diagrams 54x, internal architecture 2-2 arithmetic logic unit (ALU) 4-11 circular addressing 5-17 circular buffer implementation 5-17 compare select store unit (CSSU) 4-26 direct addressing 5-8 indirect addressing dual data-memory operands 5-21 single data-memory operand 5-12 memory-mapped register addressing 5-25 multiplier/adder 4-22 shifter 4-20 software wait-state generator 10-8 timer 8-23 block repeat counter register 3-27 end address register 3-27 start address register 3-27 block repeat operation looping 6-23 block-repeat active flag (BRAF) 4-4 definition E-4 block-repeat counter (BRC) 3-29, 6-23, 7-72 definition E-4 block-repeat end address (REA) 3-29, 6-23 definition E-4 block-repeat start address (RSA) 3-29, 6-23 definition E-4 BNKCMP 10-9

Index-3

Index

boot definition E-4 bootloader considerations when using 8-36 definition E-4 BRAF 7-74, E-4 definition E-4 BRAF deactivation example 7-75 branch control input (BIO) pin 8-20 branch instructions pipeline 7-6 branch instructions in the pipeline figure 7-6 branches 6-6 conditional 6-7 far 6-8 unconditional 6-6 BRC 3-27, 3-29 See also block-repeat counter BRE 9-44, E-4 definition E-2 BRINT E-4 definition E-4 BRSR definition E-4 BSCR E-4 definition E-3 BSP control extension register (BSPCE) bit summary 9-38, 9-44 BRE bit 9-44, E-2 BXE bit 9-45, E-2 CLKDV bits 9-39, E-11 CLKP bit 9-38, E-6 definition E-5 diagram 9-37, 9-43 FE bit 9-38, E-9 FIG bit 9-38, E-9 FSP bit 9-38, E-9 HALTR bit 9-44, E-2 HALTX bit 9-44, E-2 PCM bit 9-38, E-14 RH bit 9-44, E-14 XH bit 9-45, E-18 BSP data receive register (BDRR) definition E-3 BSP data receive shift register (BRSR) definition E-4 Index-4

BSP data transmit register (BDXR) definition E-3 BSP data transmit shift register (BXSR) definition E-5 BSP operation system considerations 9-49, 9-54 BSP receive interrupt (BRINT) definition E-4 BSP transmit interrupt (BXINT) definition E-4 BSPC definition E-4, E-5 BSPCE definition E-5 buffered serial port (BSP) 2-14, 9-33 autobuffering control register 9-43 autobuffering process 9-45 autobuffering unit (ABU) 9-40 buffer misalignment interrupt (BMINT) 9-54, E-5 definition E-4 enhanced features 9-37 power-down mode 9-55 registers 9-35 system considerations 9-49 buffered serial port control register (BSPC) definition E-4, E-5 DLB bit E-7 FO bit E-9 Free bit E-9 FSM bit E-9 IN0 bit E-10 IN1 bit E-10 MCM bit E-6 RRDY bit E-14 RRST bit E-14 RSRFULL bit E-14 Soft bit E-16 TXM bit E-18 XRDY bit E-19 XRST bit E-19 XSREMPTY bit E-19 buffered signals JTAG A-10 buffering A-10 burst mode (serial port) 9-18, E-5 bus devices A-4 bus protocol A-4 bus structure 2-3 bus usage 2-4

Index

bus usage table 2-4 butterfly definition E-5 BXE 9-45, E-5 definition E-2 BXINT definition E-4 BXSR definition E-5

C
C E-5 definition E-5 C address bus (CAB) definition E-5 C bus (CB) definition E-5 C compiler B-2 C16 definition E-5 C2x/C2xx/C5x compatibility (ARP) mode 5-23 C548 special instructions 3-21 cable target system to emulator A-1 to A-25 cable pod A-5, A-6 call instructions pipeline 7-8 calls 6-9 conditional 6-10 far 6-11 unconditional 6-9 carry bit (C) 4-3, 4-13 definition E-5 central processing unit (CPU) memory-mapped registers E-12 circular addressing circular buffer 5-17 diagram 5-17 rules for using 5-16 circular buffer size register (BK) 3-27, 3-28 definition E-5 CLKDV 9-39, E-5 definition E-11

CLKOFF definition E-5 CLKOUT off (CLKOFF) definition E-5 CLKP 9-38, E-5 definition E-6 clock changing the multiplier ratio 8-34 CLKMD 8-29 clock mode register (CLKMD) 8-29 considerations when using IDLE instruction 8-35 generator 2-13 modes 8-26 operation following reset 8-35 operation in IDLE modes 8-35 sources crystal resonator circuit 8-26 external clock 8-26 switching clock modes DIV to PLL 8-32 PLL to DIV 8-33 clock mode (MCM) definition E-6 clock mode register (CLKMD) bit summary 8-30 diagram 8-29 PLLCOUNT bits 8-30 PLLDIV bit 8-30 PLLMUL bits 8-30 PLLNDIV bit 8-30 PLLON/OFF bit 8-30 PLLSTATUS bit 8-30 clock modes mode configurations 8-27 settings at reset 5402 8-28 541B/545A/546A/548/549/5410 8-28 sources 8-26 clock polarity (CLKP) definition E-6 CLOCKOUT off (CLKOFF) 4-7 CMPT E-6 definition E-6 code definition E-6 code generation tools B-2 cold boot definition E-6

Index-5

Index

compare, select, and store unit (CSSU) 4-26 to 4-28 See also CSSU definition E-6 compatibility mode indirect addressing mode instruction format 5-24 instruction format 5-24 compatibility mode (CMPT) definition E-6 compiler B-2 compiler mode latencies for SP SP 7-50 7-51 4-4 4-5

compiler mode (CPL) definition E-6 condition groupings table 6-17 conditional branches delayed 6-7 instructions 6-8 nondelayed 6-7 conditional calls 6-10 delayed 6-10 instruction 6-11 nondelayed 6-10 conditional execute

6-7

6-17

conditional operations 6-16 to 6-19 branch 6-7 call 6-10 conditions 6-16 execute 6-17 return 6-13 store 6-18 XC instruction 6-17 conditional returns 6-13 delayed 6-14 instruction 6-14 nondelayed 6-14 conditional store 6-18 conditions for 6-19 instructions 6-18 configuration 3-16 multiprocessor A-13 Index-6

connector 14-pin header A-2 dimensions mechanical A-14 DuPont A-2 consumer applications viii, xiii continuous mode (serial port) 9-24, E-6 control applications viii, xi control registers external bus 10-5 counter down-time PLL multiplication factors 10-26 CPL E-6 definition E-6 latencies 7-66 CPU 2-7 to 2-9 accumulators 2-7, 4-15 ALU 2-7 See also ALU arithmetic logic unit 2-7 See also ALU compare, select, and store unit (CSSU) 4-26 components 4-1 CSSU 4-26 exponent encoder 4-29 introduction 4-1 to 4-18 multiplier/adder 2-8, 4-21 shifter 2-8, 4-19 CPU components 4-1 CPU registers 3-26 CSSU 2-9, E-6 diagram 4-26 functions 4-27 using CMPS instruction 4-28 Viterbi operator 4-27 with ALU operations 4-27

2-9,

D
D address bus (DAB) definition E-6 D bus (DB) definition E-7 DAB address register (DAR) definition E-6 DAGEN 7-38 DAGEN register address conflicts, rules 7-44

Index

DAR. See DAB address register DARAM blocks table 7-27 data address bus definition E-7 data address generation (DAGEN) instructions that access in read stage 7-38 data addressing five modes 2-9 introduction 5-1 data bus definition E-7 data buses 2-3 data memory 3-22 to 3-30 accumulators 3-27 auxiliary registers 3-28 block-repeat registers 3-29 circular buffer size register (BK) 3-28 configurability 3-22 CPU registers 3-26 definition E-7 interrupt registers 3-26 on-chip advantages 3-22 processor mode status register (PMST) 3-29 program counter extension (XPC) 3-29 stack pointer (SP) 3-28 status registers 3-26 table 2-5 temporary register (T) 3-28 transition register (TRN) 3-28 data memory page pointer (DP) 4-3 definition E-7 data receive register (DRR) 9-5 data receive shift register (RSR) 9-5 definition E-15 data ROM (DROM) 4-7 definition E-7 data security 3-30 data transmit register (DXR) 9-5 data transmit shift register (XSR) 9-5 definition E-20 data types 5-28 16-bit 5-28 32-bit 5-28 data-address generation logic (DAGEN) definition E-6, E-7 debug tools B-2

debugger. See emulation delayed branch instruction in the pipeline 7-7 development support applications viii, xiv development tools B-2, B-2 device nomenclature B-6 diagram B-7 prefixes B-5 diagnostic applications A-24 digital loopback mode definition E-7 digital loopback mode (DLB) bit definition E-7 dimensions 12-pin header A-20 14-pin header A-14 mechanical, 14-pin header A-14 direct addressing 2-9, 5-1, 5-7 diagram 5-8 DP-referenced 5-9 instruction format 5-8 instruction word fields dma 5-8 I 5-10, 5-24 opcode 5-8, 5-10, 5-24 SP-referenced 5-9 direct data-memory address bus definition E-7 direct data-memory address bus (DRB) definition E-8 direct memory address definition E-7 direct-addressing mode DP 7-63, 7-64 DLB 9-12 definition E-7 dma E-8 DMA sub-addressed registers 5420 8-18 dmad addressing 5-4 DP E-8 definition E-7 direct-addressing mode 7-63 latencies 7-64 DP load three-cycle latency 7-65 two-cycle latency 7-65 zero latency 7-65

Index-7

Index

DP-referenced direct addressing 5-9 diagram 5-9 DRAM blocks access 7-28 DROM E-8 definition E-7 DROM setup followed by a dual-read access 7-78 followed by a read access 7-78 DRR definition E-8 DSP articles viii, x, xii, xiii, xiv DSP interrupt (DSPINT) definition E-8 DSPINT definition E-8 DSPINT and HINT function operation 8-51 dual 16-bit mode 4-14 dual 16-bit/double-precision arithmetic mode (C16) 4-5 dual access memory 7-27 dual data-memory operand addressing auxiliary registers 5-20 diagram 5-21 indirect addressing mode diagram 5-21 instruction format 5-20 instruction format 5-20 types of 5-21 using Xmem 5-19 using Ymem 5-19 dual operands 5-19 circular 5-22 increment/decrement 5-22 indexed 5-22 single-operand instructions 5-22 dual-access RAM (DARAM) 2-6 definition E-7 DuPont connector A-2 DXR definition E-8

E
E address bus (EAB) definition E-8 Index-8

E bus (EB) definition E-8 EAB address register (EAR) definition E-8 EMU0/1 configuration A-21, A-23, A-24 emulation pins A-20 IN signals A-20 rising edge modification A-22 EMU0/1 signals A-2, A-3, A-6, A-7, A-13, A-18 emulation JTAG cable A-1 timing calculations A-7 to A-9, A-18 to A-26 emulator connection to target system JTAG mechanical dimensions A-14 to A-25 designing the JTAG cable A-1 emulation pins A-20 pod interface A-5 signal buffering A-10 to A-13 target cable header design A-2 to A-3 emulator pod timings A-6 enabling the timer 8-25 execute conditional 6-17 execute interrupt service routine (ISR) interrupt context save 6-34 interrupt latency 6-34 EXIO 10-10 EXP encoder definition E-8 exponent encoder 4-29 definition E-8 figure 4-29 extended program memory 3-20 paged 3-21 external bus hold mode 10-28 IDLE3 wake-up sequence 10-26 interface 10-2 interrupts 10-29 prioritization 10-4 reset 10-29 timing 10-14 I/O access 10-18 memory access 10-14 reset 10-24

Index

external bus control registers 10-5 external bus interface 2-16 external bus operation introduction 10-1 external flag output (XF) pin 8-20 external interface key signals, table 10-2

FSP 9-38, E-9 definition E-9

G
general-purpose applications viii generator clock 2-13 wait-state 2-11 graphics/imagery applications viii, x

F
far branches 6-8 instructions 6-8 unconditional 6-8 far calls 6-11 instructions 6-11 unconditional 6-11 far returns 6-14 instructions 6-15 unconditional 6-14 fast Fourier transform (FFT) E-8 fast return register (RTN) definition E-8 FE 9-38, E-9 definition E-9 FIG 9-38, E-9 definition E-9 FO 9-11, 9-13 definition E-9 format (FO) definition E-9 format extension (FE) definition E-9 fractional mode (FRCT) 4-5 definition E-9 frame ignore (FIG) definition E-9 frame synchronization mode (FSM) definition E-9 frame synchronization polarity (FSP) definition E-9 FRCT definition E-9 Free bit 8-22, 9-9, 9-17 definition E-9 FSM 9-11, 9-13, E-9 definition E-9

H
half-cycle accesses instruction performing dual-operand write 7-28, 7-29 instruction performing operand read/write 7-29 instruction performing single-operand read 7-28 instruction performing single-operand write 7-28 instruction word prefetch 7-28 half-cycle accesses to dual-access memory 7-28 HALTR 9-44, E-10 definition E-2 HALTX 9-44, E-10 definition E-2 hardware block diagram 2-2 timer 2-12 Harvard architecture 1-5 header 14-pin A-2 dimensions, 14-pin A-2 HINT definition E-10 HM E-10 definition E-10 HOLD and HOLDA minimum timing 10-30 hold mode 6-52, 10-28 hold mode (HM) 4-4 definition E-10 HOM host-only mode 8-47 host port interface 2-12, 8-37 to 8-54 block diagram 8-37 control register bit descriptions 8-44 definition E-10 details of operation 8-41

Index-9

Index

host port interface (continued) functional description 8-38 generic block diagram 8-39 host read/write access 8-46 input control signals 8-43 memory access during reset 8-54 memory access mode, SAM/HOM 8-52 operation during reset 8-54 register description 8-40 signal names and functions 8-41 timing diagram 8-48 host processor interrupt (HINT) definition E-10 host-only mode (HOM) 8-47, E-10 host-port interfaces table 2-12 HPI. See host port interface HPI address register (HPIA) E-10 HPI control register (HPIC) E-10 54x reads from HPIC 8-46 54x writes to HPIC 8-46 DSPINT bit E-8 HINT bit E-10 host reads from HPIC 8-45 host writes to HPIC 8-46 SMOD bit E-16 HPI modes host only (HOM) E-10 shared access (SAM) E-16

I
I/O access timing 10-18 pins 8-20 BIO pin 8-20 branch control input (BIO) pin 8-20 external flag output (XF) pin 8-20 XF pin 8-20 ports parallel 2-16 serial 2-14 I/O memory 3-30 I/O pins BIO 2-11 XF 2-11 IDLE1 mode 6-50 IDLE2 mode 6-51 Index-10

IDLE3 mode 6-51 IDLE3 wake-up sequence 10-26 IEEE 1149.1 specification bus slave device rules A-4 IEEE standard 1149.1 2-16 IFR 3-26, 3-27, E-10 definition E-11 immediate addressing 2-9, 5-1, 5-2 instructions, table 5-2 long 5-2 short 5-2 IMR 3-26, 3-27, E-10 definition E-11 IN0 9-10, 9-15 definition E-10 IN1 9-10, 9-15 definition E-10 indirect addressing 2-9, 5-1, 5-10 address modifications 5-13, 5-19 address-generation operation 5-11 ARAU 5-11 assembler syntax 5-23 diagram 5-12, 5-21 dual-operand addressing 5-19 instruction format compatibility mode 5-24 dual data-memory operands 5-20 single data-memory operand 5-10 instruction word fields ARF 5-11, 5-24 MOD 5-10, 5-24 opcode 5-20 Xar 5-20 Xmod 5-20 Yar 5-20 Ymod 5-20 single-operand addressing 5-10, 5-13 initialization timer 8-24 input 0 (IN0) definition E-10 input 1 (IN1) definition E-10 input sources ALU 4-11 multiplier 4-22 instruction fetch and operand read figure 7-30

Index

instruction register (IR) definition E-11 instructions multiconditional 6-17 internal memory on-chip dual-access RAM (DARAM) 2-6 ROM 2-5 security 2-6 single-access RAM (SARAM) 2-6 organization 2-5 internal transmit clock division factor (CLKDV) definition E-11 interrupt definition E-11 interrupt flag register (IFR) BRINT bit E-4 BXINT bit E-4 definition E-11 diagram 6-28 RINT bit E-15 TINT bit E-18 TRINT bit E-17 TXINT bit E-17 XINT bit E-16 interrupt locations 541 6-38 542 6-39 543 6-40 545 6-41 546 6-42 548 6-43 549 6-44 5402 6-45 5410 6-46 5420 6-48 interrupt mask register (IMR) definition E-11 diagram 6-29 interrupt mode (INTM) definition E-11 interrupt operation diagram 6-37 interrupt phases 4-4 3-26, 6-29 3-26, 6-27

interrupt tables

6-38

interrupt vector address generation diagram 6-36 interrupt vector pointer (IPTR) definition E-11 4-6

interrupts 6-26, 10-29 hardware E-10 interrupt flag register (IFR) 3-26 interrupt mask register (IMR) 3-26 latency time 6-34 maskable 6-26 nested E-12 NMI 6-27 nonmaskable 6-26, E-12 reset 6-25 RS interrupt 6-25 saving data 6-34 soft reset 6-27 user-maskable (external) E-8 interrupts phases acknowledge interrupt 6-32 execute interrupt service routine receive interrupt request 6-31 INTM definition E-11 introduction 1-1 to 1-8 features 1-6 TMS320 family overview 1-2 TMS320C54x overview 1-5 IPIRQ interprocessor interrupt request bit IPTR definition E-11 latencies, table 7-76 IPTR setup followed by a software trap IR definition E-11 7-77 10-9

6-33

J
JTAG A-16 JTAG emulator buffered signals A-10 connection to target system no signal buffering A-10

6-35 6-27

interrupt service routine definition E-11

A-1 to A-25

Index-11

Index

L
latencies accessing ARx 7-46 accessing BK 7-46 auxiliary register 7-44 BK 7-44 DROM bit, table 7-78 store instructions 7-39 latencies for SP compiler mode 7-51 non-compiler mode (CPL = 0) 7-55 latency definition E-11 explanation of 7-35 least significant bit (LSB) definition E-11 logic/arithmetic operations multiconditional instructions 6-17 long-immediate addressing RPT instruction 5-3

M
MAC and MAS saturation 4-25 maskable interrupt 6-26, 6-35 McBSPs 2-15 MCM 9-11, 9-14, E-11 definition E-6 medical applications viii, xiv memory data memory 3-22 data security 3-30 extended program memory 3-20 I/O access timing 10-19 introduction 3-1 memory access timing 10-14 memory space 3-2 to 3-14 program memory 3-15 extended program memory 3-20 word order 5-29 memory maps 541 3-3 542 3-4 543 3-4 545 3-5 546 3-5 548 3-6, 3-7 Index-12

memory maps (continued) 5402 3-9 5410 3-11 5420 3-13, 3-14 definition E-11 extended program 548 and 549 3-8 5402 3-10 5410 3-12 5420 3-14 memory security 2-6 memory space 3-2 to 3-14 memory-mapped registers conflict example 7-43 instructions for accessing 7-35 memory-mapped register addressing 2-9, 5-1, 5-25 diagram 5-25 instructions 5-26 LDM 5-26 MVDM 5-26 MVMD 5-26 MVMM 5-26 POPM 5-26 PSHM 5-26 STLM 5-26 STM 5-26 memory-mapped registers 2-6, 3-25 defined E-12 peripheral 8-2 micro stack definition E-12 microcomputer mode definition E-12 microprocessor mode definition E-12 microprocessor/microcomputer (MP/MC) 4-6 definition E-12 military applications viii, xii mode selection clock modes 8-27 most significant bit (MSB) definition E-12 MP/MC definition E-12 latencies, table 7-76 MP/MC setup followed by an unconditional delayed call 7-77

Index

multi-channel buffered serial port (McBSP) definition E-12 multi-channel buffered serial ports 2-15 multi-cycle instructions transformed to single-cycle 6-20 multimedia applications viii, xii multiplier definition E-12 multiplier/adder 2-8, 4-21 to 4-24 block diagram 4-22 input sources 4-22, 4-23 multiplier input selection, table 4-23 multiply/accumulate (MAC) instructions 4-24 multiply/subtract (MAS) instructions 4-21 square/add (SQRA) instructions 4-24 square/subtract (SQRS) instructions 4-24

N
nested interrupt E-12 nomenclature B-6 prefixes B-5 nonmaskable interrupt 6-26, 6-35 normalization of accumulator A example 4-29

O
on-chip dual-access RAM (DARAM) 2-6 peripherals 2-11 ROM 2-5 security 2-6 single-access RAM (SARAM) 2-6 on-chip DARAM 3-22 on-chip data memory available, table 3-22 on-chip memory 3-15 advantages 3-1 available, table 3-15 on-chip peripherals buffered serial port (BSP) 9-33 serial port interface 9-4 TDM serial port 9-56 on-chip RAM organization 3-23, 3-24, 3-25

on-chip ROM C-1 figure 3-17 organization 3-17 program memory map figure 3-19 on-chip ROM contents 3-18 operand write and operand read conflict figure 7-32 output modes external count A-20 signal event A-20 OVA definition E-12 OVB definition E-13 overflow definition E-13 overflow flag definition E-13 overflow flag A (OVA) 4-3 definition E-12 overflow flag B (OVB) 4-3 definition E-13 overflow handling 4-13 overflow mode (OVM) 4-5 definition E-13 overview architecture 2-1 TMS320 family 1-2 TMS320C54x 1-5 OVLY E-13 definition E-14 latencies, table 7-76 OVLY setup followed by a conditional branch 7-76 followed by a return 7-77 followed by an unconditional branch 7-76 OVM definition E-13

P
PA addressing 5-5 PAB E-13 definition E-13 PAGEN 2-10, 6-2 diagram 6-3 PAL A-21, A-22, A-24

Index-13

Index

parallel I/O ports 2-16 part numbers tools B-8 part-order information B-5 PB E-13 definition E-14 PC E-13 definition E-14 PCM 9-38, E-13 definition E-14 peripheral control 8-2 to 8-19 peripheral memory-mapped registers 541/541B 8-3 542 8-4 543 8-5 545/545A 8-6 546/546A 8-7 548 8-8 549 8-9 5402 8-11 5410 8-13 5420 8-15 peripherals 8-1 to 8-26 bank switching 2-12 buffered serial port (BSP) 9-33 clock generator 2-13 clock modes 8-26 control 8-2 general-purpose I/O pins 8-20 hardware timer 2-12 host port interface 2-12 host port interface (HPI) 8-37 I/O pins 8-20 list of 8-1 on-chip 8-1 parallel I/O ports 2-16 programmable bank switching 10-8 serial I/O ports 2-14 serial port interface 9-4 software-programmable wait-state generator 10-5 TDM serial port 9-56 timer 8-21 wait-state generator 2-11, 10-5 pins I/O 8-20 pipeline BC instruction 7-23 BCD instruction 7-24 Index-14

pipeline (continued) call instruction 7-8 call instructions 7-8 CC instruction 7-21 CCD instruction 7-22 conditional call/branch instructions 7-20 conditional-execute instructions 7-19 definition E-13 delayed call instruction 7-10 delayed return instruction 7-14 delayed return with interrupt enable instruction 7-16 delayed return-fast instruction 7-18 instructions 7-6 interrupt response 7-26 INTR instructions 7-11 introduction 7-1 latency in general 7-35 precautions 7-35 store instructions 7-39 types of 7-35 levels 2-10 operation 7-2 return instruction 7-12 return instructions 7-12 return with interrupt enable instruction 7-15 return-fast instruction 7-17 six-level structure 7-2 XC instruction 7-19 pipeline latencies 7-35 pipeline levels/functions 7-2 access 7-2 decode 7-2 execute/write 7-2 program fetch 7-2 program pre-fetch 7-2 read 7-2 pipeline operation pipeline stages figure 7-3 pipelined memory accesses 7-4 instruction performing dual-operand read 7-4 instruction performing dual-operand write 7-4 instruction performing operand read and write 7-4 instruction performing single-operand read 7-4 instruction performing single-operand write 7-4 instruction word fetch 7-4 2-10

Index

pipeline-protected instruction CPL = 0 7-54 update ARP 7-61 update DP 7-63 update T register 7-57 write to ASM 7-69 PLL changing the multiplier ratio 8-34 considerations when using IDLE instruction 8-35 hardware-configurable 8-26 operation following reset 8-35 operation in IDLE modes 8-35 programmable lock timer 8-31 programming considerations 8-31 software programmable 8-27 switching clock modes DIV to PLL 8-32 PLL to DIV 8-33 PLL lockup time versus CLKOUT frequency pmad definition E-13 pmad addressing 5-5 PMST 3-27, 3-29 See also processor mode status register (PMST) definition E-13 latencies 7-75 polarity bit clock 9-38 frame sync 9-38 pop definition E-13 power-down mode 6-50 to 6-52 disabling external interface internal clock Hold mode 6-52 IDLE 1 instruction 6-50 IDLE 2 instruction 6-51 IDLE 3 instruction 6-51 initiated using HOLD signal 6-52 invoking 6-50 other power-down capabilities 6-52 power-down modes operation during 6-50 PRD definition E-13 prioritization external bus 10-4 6-52 8-32

processor mode status register (PMST) 3-29, 4-6 AVIS bit 4-7, E-1 bit summary 4-6 CLKOFF bit 4-7, E-5 definition E-13 diagram 4-6 DROM bit 4-7, E-7 IPTR field 4-6, E-11 MP/MC bit 4-6, E-12 OVLY bit 4-6, E-14 SMUL bit 4-7, E-15 SST bit 4-8, E-15 program address bus (PAB) definition E-13 program address register (PAR) definition E-14 program addressing 2-10 introduction 6-1 program bus 2-3 program control block repeat operations 6-23 conditional operations 6-16 control registers 4-2 hardware stack 5-27 interrupts 6-26 to 6-49 power-down mode 6-50 program counter (PC) 6-4 repeat (single) operations 6-20 reset 6-25 status registers 4-2 program controller definition E-14 program counter (PC) 6-4 to 6-5 definition E-14 loading address 6-4 program counter extension (XPC) definition E-14 program data bus (PB) definition E-14 program memory 3-15 to 3-21 address map 3-18 configurability 3-16 definition E-14 mapping the C542 3-18 on-chip ROM code 3-18 program space 3-16 table 2-5

3-27,

3-27, 3-29

Index-15

Index

program memory address (pmad) definition E-13 program-address generation logic (PAGEN) 6-2 definition E-13 programmable bank switching 10-8 program-memory address generation 6-2 protocol bus A-4 PSC 8-22 definition E-18 PS-DS 10-9 pulse coded modulation mode (PCM) definition E-14 push definition E-14

2-10,

R
RAM 2-6 RAM overlay (OVLY) 4-6 definition E-14 RC E-14 definition E-15 RCCD instruction no latency 7-73 REA 3-27, 3-29, E-14 receive buffer half received (RH) definition E-14 receive interrupt request hardware interrupt request 6-31 interrupt flag register (IFR) 6-27 software interrupt request 6-31 receive ready (RRDY) definition E-14 receive shift register full (RSRFULL) definition E-14 receiver reset (RRST) definition E-14 regional technology centers B-4 register ABU address receive (ARR) E-2 ABU address transmit (AXR) E-3 ABU receive buffer size (BKR) E-3 ABU transmit buffer size (BKX) E-3 autobuffering control 9-43 bank-switching control (BSCR) E-3 Index-16

register (continued) BSP control extension (BSPCE) E-5 BSP data receive (BDRR) E-3 BSP data receive shift (BRSR) E-4 BSP data transmit (BDXR) E-3 BSP data transmit shift (BXSR) E-5 buffered serial port control (BSPC) E-4 data receive shift (RSR) E-15 data transmit shift (XSR) E-20 definition E-15 fast return (RTN) E-8 host port interface address (HPIA) E-10 host port interface control (HPIC) E-10 instruction (IR) E-11 interrupt flag (IFR) E-11 interrupt mask (IMR) E-11 processor mode status (PMST) 4-6, E-13 repeat counter (RC) E-15 serial port 9-5 serial port control (SPC) E-16 serial port data receive (DRR) E-8 serial port data transmit (DXR) E-8 status 4-2 status 0 (ST0) E-17 status 1 (ST1) E-17 TDM channel select (TCSR) E-17 TDM data receive (TRCV) E-19 TDM data receive shift (TRSR) E-19 TDM data transmit (TDXR) E-17 TDM receive address (TRAD) E-18 TDM receive/transmit address (TRTA) E-19 TDM serial port 9-56 TDM serial port control (TSPC) E-19 temporary (T) E-18 timer control (TCR) E-17 timer counter (TIM) E-18 timer period (PRD) E-13 transition (TRN) E-18 re-mapping interrupt vector addresses 6-36 repeat block loops 7-72 repeat counter (RC) definition E-15 repeat operation See also block repeat operation handling multicycle instructions 6-20 non-repeatable instructions 6-21 reset clock modes 8-28 definition E-15 RS interrupt 6-25

Index

reset (continued) sequence of events 6-25 setting status bits 6-25 reset sequence 10-24 resolved conflict instruction fetch and operand read 7-29 operand write and dual-operand read 7-30 operand write, operand write, and dual-operand read 7-31 return instruction in the pipeline 7-12 returns 6-12 conditional 6-13 far 6-14 unconditional 6-12 RH 9-44, E-15 definition E-14 RINT E-15 definition E-15 ROM 2-5 RPT instruction long-immediate addressing 5-3 short-immediate addressing 5-3 RPTB instruction 6-23 RPTBD instruction 6-23 RRDY 9-10, 9-15, E-15 definition E-14 RRST 9-10, 9-14, E-15 definition E-14 RSA 3-27, 3-29, E-15 RSR definition E-15 RSRFULL 9-9, 9-16, E-15 definition E-14 RTCs B-4 RTN E-15 definition E-8 run/stop operation A-10 RUNB debugger command A-20 to A-24 RUNB_ENABLE input A-22

S
SAM shared access mode 8-47

sample pipeline diagram figure 7-5 saturation on multiplication (SMUL) 4-7 definition E-15 example 4-9 saturation on store (SST) 4-8 definition E-15 example 4-10 scan path linkers A-16 secondary JTAG scan chain to an SPL A-17 suggested timings A-22 usage A-16 scan paths TBC emulation connections for JTAG scan paths A-25 scanning logic (IEEE standard) 2-16 security options 3-30 on-chip ROM 3-30 ROM/RAM 3-30 seminars B-4 serial I/O ports 2-14 serial port control register (SPC) 9-5 bit summary 9-9 definition E-16 diagram 9-8 DLB bit 9-12, 9-12, E-7 FO bit 9-11, 9-13, E-9 Free bit 9-9, 9-17, E-9 FSM bit 9-11, 9-13, E-9 IN0 bit 9-10, 9-15, E-10 IN1 bit 9-10, 9-15, E-10 MCM bit 9-11, 9-14, E-6 RRDY bit 9-10, 9-15, E-14 RRST bit 9-10, 9-14, E-14 RSRFULL bit 9-9, 9-16, E-14 Soft bit 9-9, 9-17, E-16 TXM bit 9-11, 9-14, E-18 XRDY bit 9-10, 9-15, E-19 XRST bit 9-10, 9-14, E-19 XSREMPTY bit 9-9, 9-16, E-19 serial port data receive register (DRR) definition E-8 serial port data transmit register (DXR) definition E-8 serial port interface 9-4, E-15 block diagram 9-8 configuring 9-8 error conditions 9-26 operation 9-6

Index-17

Index

serial port interface (continued) operation examples 9-31 pins 9-7 receive operation burst mode 9-18 continuous mode 9-24 registers 9-5 reserved bit 9-12 transmit operation burst mode 9-18 continuous mode 9-24 serial port interfaces three types 9-1 serial port receive interrupt (RINT) definition E-15 serial port transmit interrupt (XINT) definition E-16 serial ports 2-14 buffered serial port (BSP) 9-33 block diagram 9-34 operation in standard mode 9-35 initialization timing 9-50 introduction 9-2 on various 54x devices 9-2 serial port interface 9-4 table 2-14 three types 2-14 time-division multiplexed (TDM) 9-56 receive initialization routine 9-68 receive interrupt service routine 9-68 register contents 9-66 transmit initialization routine 9-67 transmit interrupt service routine 9-67 where to find information 9-3 shared access mode SAM 8-47 shared-access mode (SAM) shared-access mode (SMOD) definition E-16 shift and rotate operations 4-16 rotate accumulator left 4-16 rotate accumulator left with TC rotate accumulator right 4-16 shift arithmetically 4-16 shift conditionally 4-16 shift logically 4-16 shift operations ASM field 7-69 Index-18 E-16

4-16

shifter 2-8, 4-19 to 4-21 block diagram 4-20 connections 4-19 definition E-16 used for 4-19 short-immediate addressing RPT addressing 5-3 sign control logic definition E-16 sign extension definition E-16 sign extension mode (SXM) 4-5 signal descriptions 14-pin header A-3 signals buffered A-10 buffering for emulator connections A-10 to A-13 description, 14-pin header A-3 timing A-6 sign-extension mode (SXM) definition E-16 single data-memory operand addressing diagram 5-12 direct addressing mode, diagram 5-8 indirect addressing mode assembler syntax 5-23 diagram 5-12 instruction format 5-10 instruction format 5-10 types of 5-13 with 32-bit words 5-28 single operands 5-13 single-access RAM (SARAM) 2-6 definition E-15 single-operand addressing 5-10 SINT. See software interrupt slave devices A-4 SMOD definition E-16 SMUL E-16 definition E-15 example 4-9 Soft bit 8-22, 9-9, 9-17, E-16 software development tools assembler/linker B-2 C compiler B-2 general B-8 linker B-2 simulator B-2

Index

software interrupt (SINT) definition E-16 software programmable PLL 8-27 software wait-state control register (SWCR) 10-6 software wait-state generator block diagram 10-8 software wait-state register (SWWSR) 2-11 bit summary 10-6 definition E-16 diagram 10-5 software wait-state register (SWWSR) bit summary 548/549/5402/5410/5420 10-7 SP 3-27, 3-28, E-16 compiler mode 7-50 definition E-17 push, pop, return, MVMM, FRAME 7-54 SP load one-cycle latency 7-52, 7-56 three-cycle latency 7-53 two-cycle latency 7-53 zero latency 7-52, 7-56 SPC definition E-16 SP-referenced direct addressing 5-9 figure 5-9 SRCCD instruction three-cycle latency 7-74 SST E-17 definition E-15 example 4-10 ST0 3-26, 3-27 See also status register 0 (ST0) definition E-17 ST1 3-26, 3-27 See also status register 1 (ST1) definition E-17 stack definition E-17 stack addressing 2-9, 5-1, 5-27 pop instructions 5-27 push instructions 5-27 stack pointer (SP) 2-10, 3-27, 3-28 definition E-17 latencies 7-50 stack/stack pointer before and after push operation, figure 5-27 start-up access sequences 10-24

status and control registers 4-2 to 4-10 status register 0 (ST0) 4-2 ARP field 4-2, E-2 bit summary 4-2 C bit 4-3, E-5 definition E-17 diagram 4-2 DP field 4-3, E-7 OVA bit 4-3, E-12 OVB bit 4-3, E-13 TC bit 4-3, E-17 status register 1 (ST1) 4-2 ASM field 4-5, E-1 bit summary 4-4 BRAF bit 4-4, E-4 C16 bit 4-5 CMPT bit 4-5, E-6 CPL bit 4-4, E-6 definition E-17 diagram 4-4 FRCT bit 4-5, E-9 HM bit 4-4, E-10 INTM bit 4-4, E-11 OVM bit 4-5, E-13 SXM bit 4-5, E-16 XF bit 4-4, E-20 status register ST0, ST1 3-26 store conditional 6-18 straight unshrouded, 14-pin A-2 support tools development B-8 device B-8 support tools nomenclature prefixes B-5 SWCR, software wait-state control register SWWSR bit summary 10-6 SXM 7-67, E-17 definition E-16 latencies 7-68 SXM update no latency 7-67 one-cycle latency 7-67, 7-68 synchronous serial port interfaces three types 9-2 system stack 5-27 system-integration tools B-2

10-6

Index-19

Index

T
T definition E-18 T load one-cycle latency 7-59 zero latency 7-59 T register 3-27, 3-28 latencies 7-57 table 7-58 TADD 9-61 definition E-17 target cable A-14 A-1 to A-25 target system connection to emulator target-system clock TC definition E-17 TCK signal A-2, A-3, A-4, A-6, A-7, A-13, A-17, A-18, A-25 TCR definition E-17 TCSR definition E-17 TDDR 8-22 definition E-18 TDI signal A-2 to A-8, A-13, A-18 TDM definition E-18 TDM address (TADD) 9-59, E-17 9-57 TDM channel select register (TCSR) definition E-17 diagram 9-60 TDM clock (TCLK) TDM data (TDAT) E-17 E-17 9-57 9-58 A-12

TDM data receive register (TRCV)

TDM data receive shift register (TRSR) definition E-19 TDM data transmit register (TDXR) definition E-17

9-57 9-57

TDM receive address register (TRAD) diagram 9-60 TDM receive interrupt (TRINT) definition E-17 Index-20

TDM receive/transmit address register (TRTA) 9-57 definition E-19 diagram 9-60 TDM registers content 9-66 diagram 9-60 TDM serial port (TDM) 2-15 TDM serial port control register (TSPC) 9-57 definition E-19 diagram 9-60 DLB bit E-7 FO bit E-9 Free bit 9-9, 9-17, E-9 FSM bit E-9 IN0 bit 9-10, 9-15, E-10 IN1 bit 9-10, 9-15, E-10 MCM bit 9-11, 9-14, E-6 RRDY bit 9-10, 9-15, E-14 RRST bit 9-10, 9-14, E-14 Soft bit 9-9, 9-17, E-16 TDM bit E-18 TXM bit 9-11, 9-14, E-18 XRDY bit 9-10, 9-15, E-19 XRST bit 9-10, 9-14, E-19 TDM serial port data receive register (TRCV) definition E-19 TDM serial port interface 9-56 exception conditions 9-64 operation 9-58 operation examples 9-64 receive operation 9-62 registers 9-56 transmit operation 9-62 TDM serial port receive address register (TRAD) definition E-18 TDM transmit interrupt (TXINT) definition E-17 TDO output A-4 TDO signal A-4, A-5, A-8, A-19, A-25 TDXR definition E-17 telecommunications applications viii, xii temporary register (T) 3-27, 3-28 definition E-18 test bus controller A-22, A-24 test clock A-12 diagram A-12

Index

test/control (TC) 4-3 definition E-17 third-party support TIM definition E-18 time-division multiplexed (TDM) definition E-18 time-division multiplexing (TDM) basic operation 9-56 definition E-18 timer 2-12, 8-21 to 8-25 block diagram 8-23 operation 8-23 registers 8-21 timer control register (TCR) timer control register (TCR) bit summary 8-22 definition E-17 diagram 8-22 Free bit 8-22, E-9 PSC bits 8-22 PSC field E-18 Soft bit 8-22, E-16 TDDR bits 8-22 TDDR field E-18 TRB bit 8-22, E-18 TSS bit 8-22, E-18 timer counter register (TIM) definition E-18 timer divide-down register (TDDR) definition E-18 timer enabling 8-25 8-24 timer initialization B-3

8-22

8-21

timer interrupt (TINT) definition E-18 timer interrupt rate equation 8-24 timer operation 8-23 8-21 timer period register (PRD) definition E-13

timer stop status (TSS) definition E-18 timing XF 8-20 timing calculations A-7 to A-9, A-18 to A-26 timing diagrams external bus interface priority 10-4 external bus reset sequence 10-25 hold and reset interaction 10-31 to 10-35 IDLE3 wake-up sequence 10-27 memory interface 10-15 to 10-23 TINT E-18 definition E-18 TMS signal A-2 to A-8, A-13, A-17 to A-19, A-25 TMS/TDI inputs A-4 TMS320 DSPs applications, table 1-4 TMS320 family 1-2 to 1-6 advantages 1-2 applications 1-3 to 1-4 characteristics 1-2 development 1-2 evolution (figure) 1-3 history 1-2 overview 1-2 TMS320C54x 1-5 TMS320 ROM code submittal figure C-2 TMS320C54x 1-5 to 1-8 advantages 1-5 features 1-6 CPU 1-6 emulation 1-9 instruction set 1-7 memory 1-6 peripherals 1-7 ports 1-8
host port interfaces 2-12 serial port interfaces 2-14

timer prescaler counter (PSC) definition E-18 timer register (TIM) timer registers 8-21 timer reload (TRB) definition E-18 8-21

power 1-9 speed 1-8 internal block diagram 2-2 overview 1-5 tools part numbers B-8 tools nomenclature prefixes B-5 TRAD definition E-18

Index-21

Index

transition register (TRN) definition E-18

3-27, 3-28

transmit buffer half transmitted (XH) definition E-18 transmit mode (TXM) definition E-18 transmit ready (XRDY) definition E-19 transmit reset (XRST) definition E-19 transmit shift register empty (XSREMPTY) definition E-19 TRB 8-22 definition E-18 TRCV definition E-19 TRINT E-19 definition E-17 TRN 3-27, 3-28, E-19 definition E-18 TRSR definition E-19 TRST signal A-2, A-3, A-6, A-7, A-13, A-17, A-18, A-25 TRTA definition E-19 TSPC definition E-19 TSS 8-22 definition E-18 TXINT E-19 definition E-17 TXM 9-11, 9-14, E-19 definition E-18

unconditional operations branch 6-6 call 6-9 far branch 6-8 far call 6-11 far return 6-14 return 6-12 unconditional returns 6-12 delayed 6-12 instructions 6-13 nondelayed 6-12 updating accumulator no latency 7-82 one-cycle latency 7-81 updating ARx instructions 7-44 updating auxiliary registers 7-38 updating BK instructions 7-44

V
Viterbi operator 4-26

W
wait-state generation conditions 8-49 wait-state generator 2-11, 10-5 to 10-13 block diagram 10-8 software 10-5 software wait-state register format 10-5 wait-state register, SWWSR 10-5 warm boot definition E-19 workshops B-4

X U
unconditional branches delayed 6-6 instructions 6-7 nondelayed 6-6 unconditional calls 6-9 delayed 6-9 instructions 6-10 nondelayed 6-9 Index-22 6-6 XDS510 emulator JTAG cable. See emulation XF 4-4 definition E-20 pin 8-20, E-9 timing 8-20 XF status flag (XF) definition E-20 XH 9-45, E-20 definition E-18

Index

XINT E-20 definition E-16 XPC 3-29 See also program counter extension register loading addresses 6-5 XRDY 9-10, 9-15, E-20 definition E-19 XRST 9-10, 9-14, E-20 definition E-19 XSR definition E-20 XSREMPTY 9-9, 9-16, E-20 definition E-19

Z
ZA definition E-20 ZB definition E-20 zero detect. See ZA and ZB zero detect A (ZA) definition E-20 zero detect B (ZB) definition E-20 zero fill definition E-20

Index-23