VIDEO TECHNICAL GUIDE

DIGITAL VIDEO MOVIE

GR-DVF31U/DVL40EG
(1999 Fusion DVC Model)

NTSC/PAL

COPYRIGHT 1999 VICTOR COMPANY OF JAPAN, LTD.

Septmber 1999

INDEX
SECTION 1 OUTLINE OF THE PRODUCTS
1.1 COMPARISON TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.............1-1 1.1.1 Comparison table of DV models specification by products year .....................................1-1 1.1.2 DV model chart table of LCD type..................................................................................1-2

SECTION 2 EXPLANATION OF ELECTRICAL CIRCUT

2.1 CIRCUIT OUTLINE ..............................................................................................................2-1 2.1.1 Reference block diagram (GR-DVF31U)........................................................................2-1 2.1.2 Explanation of PLL operation .........................................................................................2-2 2.1.3 Explanation of PB equalizer and ATF operations ...........................................................2-3 2.1.4 Explanation of PC terminal and JLIP terminal ................................................................2-4 2.2 CPU FUNCTIONS................................................................................................................2-6 2.2.1 SYSCON CPU (IC1001) function ...................................................................................2-6 2.2.2 DECK CPU (IC1401) function ........................................................................................2-9 2.2.3 MDA IC (IC1601) function ..............................................................................................2-14 2.2.4 CDS AGC AD IC (IC5601) function................................................................................2-20 2.2.5 B/W LCD driver IC (IC7001) function (for GR-DVF11U) .................................................2-22

INDEX-1

SECTION 1 OUTLINE OF THE PRODUCTS

1.1 COMPARISON TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR
1.1.1 Comparison table of DV models specification by products year (1/2)
Model Function Battery 1998 Fusion DV Model BN-V11 Ni-Cd (6V, 1100 mAh) BN-V12 Ni-Cd (6V, 1200 mAh) BN-V20 Ni-MH (6V, 2000 mAh) Charging time: AA-V15 used 70 min. (BN-V11) 70 min. (BN-V12) 110 min. (BN-V20) No Yes Manual Shutter Color LCD 0.55" 113k pixels B/W CRT Non 2.5" 480 234 = 112k pixels 3" 480 234 = 112k pixels Horizontal resolution: 240 lines Amorphous silicon transistor 1/4" Total 766 596 = 460k pixels (*766 711 = 540k pixels) Effective aria 611 480 = 290k pixels (*601 576 = 350k pixels) 360 Lines No Yes lux 1999 Fusion DV Model BN-V207 Lithium-ion (7.2V, 700 mAh) BN-V214 Lithium-ion (7.2V, 1400 mAh)

Charging time: AA-V20 used 90 min. (BN-V207) 180 min. (BN-V214) Cap Color LCD 0.55" 113k pixels B/W LCD 2.5" 480 234 = 112k pixels 3" 480 234 = 112k pixels 3.5" 480 234 = 112k pixels Horizontal resolution: 240 lines Amorphous silicon transistor 998 677 = 680k pixels (*998 797 = 800k pixels) Effective aria 711 485 = 340k pixels (*702 575 = 400k pixels) 400 Lines 16 lux (*18 lux) 60 IRE Level Slow Shutter off F1.6 f = 3.9 to 62.4 mm Optical zoom: 16 Digital zoom: 4/10,25 or 28 Max. zoom: 160 ,400 or 450 1/4" Total

Charging of battery in the unit Lens cover Viewfinder LCD monitor

Image device

Horizontal resolution Progressive scanning Electric image stabilizer Sensitivity Lens specification Tele macro Zoom ratio

Snapshot

Playback snapshot Playback digital zoom Slow motion Auto flash Video auto light Audio Snapshot search Record end search Audio dubbing

F1.6 f = 3.9 to 62.4 mm Yes Optical zoom: 16 Digital zoom: 4/10 or 8/20 Max. zoom: 160 or 320 5 mode With frame Full Pin-up Pin-up 4-division Pin-up 9-division Yes Yes 10 RM-V712U Yes RM-V712U No Yes 2ch(48kHz) /4ch(32kHz) No No No (Yes:PAL model,32kHz only,RCU only)

Yes 4 RM-V711U (optional: GR-DVF11U) Yes (Frame Advance) RM-V711U (optional: GR-DVF11U) Yes ( /No) 2ch(48kHz) /4ch(32kHz) Yes (32kHz only,RCU only)

Table 1-1-1 Comparison table of DV models specification by products year (1/2)

1-1

 Comparison table of DV models specification by products year (2/2)

Model Function V.insert editing Time code Headphone terminal AV output terminal S output terminal JLIP terminal PC terminal Digital still image output terminal DV terminal JLIP related software 1998 Fusion DV Model No Yes No RCA (Video Audio L/R) Yes Yes No No No JLIP video capture box GV-CB3 (optional) JLIP video capture Ver.2.0 JLIP video producer Ver.1.13 06 Yes Yes: CR-2025 type Yes (No: GR-DVF11U) Yes (No: GR-DVF11U) Yes (EG/EK Model Output only) Provided CD-ROM or optional HS-V4KIT (/No: GR-DVF11U) JLIP video capture Ver.3.0 JLIP video producer Ver.1.16 Yes: CR-2032 type (built-in) 1999 Fusion DV Model

JLIP ID number Remote control sensor Button battery (only for clock backup)

Table 1-1-1 Comparison table of DV models specification by products year (2/2) 1.1.2 DV model chart table of LCD type
1998 Fusion DV Model LCD Monitor/ VF Non/ Color 2.5"/ BW CRT 2.5"/ Color 3.0"/ Color GR-DVF20U VICTOR JVC-NTSC GR-DVA1U GR-DVF10U GR-DVF10EG GR-DVF10EK GR-DVF7A GR-DVF10EA GR-DVF25SH GR-DVF1EG GR-DVF1EK JVC-PAL GR-DVF3A GR-DVF15SH

1999 Fusion DV Model LCD Monitor/VF VICTOR JVC-NTSC JVC-PAL GR-DVL20EA GR-DVL33SH GR-DVL38SH GR-DVL40EG GR-DVL40EK GR-DVL45A GR-DVL40EA GR-DVL48ED GR-DVL28ED

2.5"/ BW LCD GR-DVF1 3.0"/ BW LCD 3.0"/ Color 3.5"/ Color GR-DVA1

GR-DVF11U,21U GR-DVL20EG GR-DVL20EK GR-DVL25A GR-DVL30EG GR-DVL30EK GR-DVF31U

Table 1-1-2 DV model chart table of LCD type

1-2

SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT

2.1 CIRCUIT OUTLINE
The basic circuit of GR-DVF31U and GR-DVL40EG descriptions only a difference in this technical guide because it is the same as GR-DVM70U/DVX7E. Refer to technical guide of GR-DVM70U/DVX7E for the part which isn't descriptioned. 2.1.1 Basic block diagram (GR-DVF31U)
0 4 CCD 0 1 MAIN
IC5601

IC4301
TMY(8), TMC(4) FMY(8), FMC(4)

IC4302
FIELD MEMORY

IC3001
RD(16) RA(10)

IC3002
16M DRAM

OPTICAL BLOCK

CCD

CCD_OUT

CDS/AGC A/D

CAM_AD(10)

IC3101
1394PHY
TPA+,TPATPB+,TPBDV_JACK

CAMERA_DSP
DYO(4),DCO(4)

DECK_DSP

PD(4)

SSI

DYI(4),DCI(4)

VREF_Y,VREF_C,VREF_RB

ADDT(16)

DV_C, DV_Y

DV_R-Y, DV_B-Y

BUS(16)

IC5501
SUB H1, H2, RG V1,V2,V3,V4 XAVD, XAHD

IRIS PWM

PBDATA

DODAT

IC3201
PBO

IC3301
PB_ENV

AIDAT

HSE

DVEQ

ATFO

DVANA

TG V.DRV

CLK27,CLK18,CLK13 SSI

IC1003
54MHz X5501 X1002 32kHz E 2PROM

IC3503
H_GAIN,H_OFFSET YC_GCTL,ASPECT AFZ_DATA

AVCOC VCO,ATF_GAIN RECC_ADJ

EVR DAC

IC1004
RTC

IC4851
FOCUS (4)

ZOOM (4)

FOCUS DRIVER & ZOOM DRIVER

AFZ_DATA

IC1001
AD(16)

IC1401
ADDT(16)

IC4801,IC4802
DRIVE+,-

SYSCON CPU
IRIS_O/C

S_DT_OUT S_DT_IN

S_DT_OUT S_DT_IN SRV_RX

DECK CPU

ANA_DATA

IRIS DRIVER

RX

TX

OSD_DATA

H_GAIN,H_OFFSET TX

PC

DODAT

RX

SRV_TX

IRIS PWM

MDA_IN MDA_OUT

AIDAT

RX

IC3501
PB_ENV HSE

ANA_DATA

ADDT(16)

TX

TX

JLIP

RX

IC2101 IC3701
MIC_AU / R

AUDIO A/D, D/A

MIC_AU / L

REC AMP & PB AMP

1F 1S 2F 2S

VIDEO HEAD

PB_AU / R

S OUT

DV_C, DV_Y Y_OUT V_OUT

VIDEO DRIVER

IND

IND LCD_IND

IC1002
ON SCREEN

PB_AU / L

RECC_ADJ

SP

A/V OUT

Y_GCTL,C_GCTL,ASPECT A_OUT/ L A_OUT/ R

IC2201
AO_SIG / L AO_SIG / R

SPK+,SPKINT_MIC / L MIC UNIT INT_MIC / R

AUDIO AMP

1 0 VF
LCD PANEL

0 7 MONITOR
MON_R VF_R VF_G VF_B

IC7601 IC7604
SW
R G B LCD_Y

AFZ_DATA

IC1601
MDA_IN,MDA_OUT

C_COIL_U C_COIL_V C_COIL_W D_COIL_U D_COIL_V D_COIL_W LOAD_FWD LOAD_REV

CAPSTAN MOTOR

LCD PANEL

MON_G MON_B

LCD DRIVER

LCD_B-Y, LCD_R-Y LCD_IND

MDA

DRUM MOTOR

0 2 SECOND

LOADING MOTOR

3 JUNCTION

Fig. 2-1-1 Basic block diagram (GR-DVF31U)

2-1

2.1.2 Explanation of PLL operation

X5501

IC5501 TG V.DRV
CLK27 VCO405I

54MHz

81MHz A07 MAIN_VCO ADJ JIG CONN MAIN_VCO X3301

IC3001 FRP GEN

FRP FRP

DVDSP

IC3101 1394 PHY

PHYCLK

27MHz

81MHz

1394 LINK

IC3301

DVANA

REF

VCXO
PWM405 VCO405

FRP GEN

PC

VCO CLK OSC

X3001 REF 24.576MHz DOMCK MAIN CLK 40.5MHz REC CLK 41.85MHz
Not used

Serial I/F
12.288MHz 11.289MHz 8.192MHz PWMAUD

ANA_DATA From DECK_CPU VCOAUD

PC

VCO

A04 FS_PLLADJ VCOAUD

FS_PLL JIG CONN

A012 AVCOC

Fig. 2-1-2 PLL operation block diagram The main clock for the deck section operates at a frequency of 40.5 MHz, which is equivalent to 18 MHz for the previous models. Since two memories of the SHUFFLE memory and the ECC memory that are needed for the previous models are integrated into one DRAM, the clock frequency is raised in order to increase the processing speed. For setting the clock duty ratio exactly at 50 %, 40.5 MHz clock is produced from the 81 MHz clock. The PLL circuit of the main clock system produces 81 MHz clock by the X'TAL X301 and VCXO, and sends the 81 MHz clock to the IC3001 DV DSP. Using the frame pulse produced from the 81 MHz pulse as the comparison signal of the PLL, the frame pulse (29.97 Hz in NTSC or 25 Hz in PAL) is produced from the 27 MHz pulse output from the camera and this frame pulse is used as the reference signal of the PLL in the general recording and playback modes. However, the frame pulse produced by decoding the input DV signal is used as the PLL reference signal for phase comparison in the 1394 input mode. A phase error is output as the PWM405 signal, which passes through the filter circuit and controls the VCXO. For PLL adjustment, the filter output voltage is set nearly at the center (1.2 V 0.1 V) of the tolerance in the condition that the PLL is locked. There are three audio sampling frequencies (32 kHz, 44.1 kHz and 48 kHz) provided, therefore, master clocks (8.192 MHz, 11.289 MHz and 12.288 MHz) are produced by the VCO in the IC3301 for the respective sampling frequencies, and those master clocks are output to the IC3001 DV DSP. For adjusting the FS-PLL, the respective frequencies are adjusted in the free-run status.
2-2

2.1.3 Explanation of PB equalizer and ATF operations

IC3301
PB_ENV

DV_ANA
PBO

IC3201
AINAD1

DV_EQ AUTO EQ
PB_DATA

LPF

AGC

AD1

1+D

VITERBI
PB_CLK

PLLE REFV
+ -

VOA VOB

2CH DAC

PLL DET PWM

IC3203
PLLO

VCO

CLK

41.85MHz ADDT00:15 SERVO CPU

DTR SW CTL1 DISCR

CPU I/F DISCRI

41.85MHz

RECCTL JIG CONN PB_VCO REC:H

BPF

GCA

ATFO

AINAD2

AD2

ATF

A02 ATF_GAIN

RECCLK

Fig. 2-1-3 PB equalizer and ATF operation block diagram In the playback mode the PB ENV signal output from the PB amp. is branched into two in the IC3301 DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output through the LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal output through the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF. In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTO EQ), SI-NRZI channel decoding (1+D), and Viterbi-decoding (VITERBI). The resultant signal processed as mentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuit constructed in this circuitry controls phase correction in order to generate the PB clock synchronizing with the playback signal. The 41.85 MHz signal oscillated by the IC3203 VCO is output as the PB clock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switch is turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, in the Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator (DISCRI) compares the 41.85 MHz signal oscillated from the VCO with the other 41.85 MHz signal produced from the 81 MHz of the main clock in order to detect a difference between the two frequencies. In the general playback mode, the discriminator outputs a Low level signal when the frequency difference is +1 % or more or a High level signal when the difference is -1 % or more. In the other modes, a Low level signal is output when the frequency difference is +3 % or more or a High level signal is output when the difference is -3 % or more. When the frequency difference is within 1 % in the general playback mode or within 3 % in the other modes, the output signal has a high impedance. Therefore, a frequency difference, if there is, is roughly corrected. Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from the playback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201 DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detection result is transmitted to the servo CPU.
2-3

2.1.4 Explanation of PC terminal and JLIP terminal

IC1001 IC1401

SYSCON CPU
IC501 EDIT_CTL

DECK CPU

SRV_RX

J507

PC

TX RX

IC503 Q502 D1002

Q1008 EDIT J503 RX TX GND Q501 IC503 Q1001 IC1006

JLIP

Fig. 2-1-4 PC terminal and JLIP terminal block diagram

To: PC RS-232C

PC Cable

2.5 3-Pole Plug

Fig. 2-1-5 PC cable

N.C. N.C.
1

Remote Pause Jack GND

2 4

JLIP Jack EDIT RX TX GND

REMOTE

3.5 , 2-Pole Plug

4-2 Edit Cable

3.5 , 4-Pole Plug

Fig. 2-1-6 4-2 edit cable The PC jack (2.5 mm , 3 poles) and JLIP jack (3.5 mm , 4 poles) are provided as the JLIP terminals of this model. Since the IC501 of an RS-232C transceiver is built in the PC terminal, a straight type PC cable (without level converter) can be used for connecting this model with a personal computer. Therefore, a straight type PC cable is contained in the personal computer connecting kit supplied as an accessory or the HS-V4KIT to be supplied as an optional. Since the JLIP terminal is the same as usual, a personal computer can be connected with this model by use of the JLIP-PC cable (QAM0099-002) that internally incorporates a level converter. However, it is recommended to use the PC terminal for connecting a
2-4

SRV_TX

RXD

TXD

GND

MAX3221

IC502

personal computer and to use the JLIP terminals for connecting other JLIP apparatus such as a video deck, video printer and so on, because such the connection enables the user to perform program editing with the JLIP video producer. If this model is used for program editing with the JLIP video producer, only the video deck having the JLIP terminal can be connected with it as a recording unit because it has no remote output terminal (editing terminal). Accordingly, neither video deck having the remote pause terminal nor multibrand remote controller can be connected with this model. This problem can be solved by use of a special 4-pole-to-2pole remote cable while connecting the EDIT CTL with a dead pin of the JLIP terminal (except the US version). When trying to make this connection for program editing with the JLIP video producer, pay heed to the point that it is required to use a special 4-pole-to-2-pole remote cable. If a 2-pole-to-2-pole remote cable is used for connection or a 4-pole-to-2-pole remote cable is revsersely connected, communication with a personal computer and editing operation result in failure because the RX pole of the JLIP terminal is grounded. However, for utilizing the program editing function of this model without use of the JLIP video producer, in other words without connection of a personal computer, either a 4-pole-to-2-pole or a 2-pole-to-2-pole remote cable can be used for connecting a video deck having the remote pause terminal and multibrand remote controller. When a 4-pole plug is inserted into the JLIP jack, the remote pause signal is output from the EDIT CTL. On the other hand, when a 2-pole plug is inserted into the jack, the remote pause signal is output from the TXD because it is detected that the RX pole is grounded. This model is capable of transferring digital still pictures with the JLIP video capture used together. The previous models having the digital still picture output terminal (GR-DVL9000, GR-DVL9500) use the VRAM (field memory) as the capture memory and output digital video data from the TXD through the CAMERA DSP and SYSCON CPU, while the personal computer receives and saves digital data in the DVF format. Differently from this system currently in use, this model outputs DV playback data that is saved in the DRAM from the SRV-TX through the DECK DSP and DECK CPU. At that time, only the image data is extracted from the DV playback data not to be accompanied with the other data such as audio data, sub code, etc., and the image data is output as the DV stream data. Receiving the image data, the personal computer (JLIP Video Capture Ver.3.0) manages the whole image data of an album in one file (extension: **.vna). For saving an image data as an image file, open an album on the personal computer and select desirable data, which will be saved as a JPEG, BMP or DVF formatted file when "Save Image As ..." operation is executed.

2-5

2.2 CPU FUNCTIONS

2.2.1 SYSCON CPU (IC1001) function 1. SYSCON CPU (IC1001) pin functons (1/3)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Label AU_CMODE LAMP_ON BUS0 BUS1 BUS2 BUS3 VDD VSS BUS4 BUS5 BUS6 BUS7 BUS8 BUS9 BUS10 PWR_CTL SRV_RDY BUS11 BUS12 BUS13 BUS14 BUS15 MODE0 MODE1 MODE2 SRV_CS WB_IR_DET F/Z_CS VDD OSCI OSCO VSS MFLD NMI RST PHOTO_SW V_MUTE JLIP_INT VD OMT KASHA_CTL MENU_P_A CFRP In/Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out In In/Out In/Out In/Out In/Out In/Out In In In Out In Out In Out In In In In Out In In In In In In Description M clock select for audio AD/DA IC Video light ON/OFF

Address/Data MPX BUS 16bits CAMERA_DSP IC4301

Power supply GND GND

Address/Data MPX BUS 16bits CAMERA_DSP IC4301

Power control Ready signal from DECK_CPU IC1401

Address/data MPX BUS 16bits CAMERA_DSP IC4301

GND GND AL3V Chip select to DECK_CPU IC1401 Flicker detect Chip select to F/Z DRIVER IC4851 Power supply System clock (24MHz) System clock (24MHz) GND Field discrimination signal H: fixed Reset Snap shot switch input Video mute JLIP interrupt Vertical sync signal EIS data readout timing Not used Menu dial pulse Frame reference pulse

Table 2-2-1 SYSCON CPU (IC1001) pin functions (1/3)

2-6

 SYSCON CPU (IC1001) pin functions (2/3)

Pin No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Label RTC_INT AFBEND VF_MONI LCD_LOAD VF_CTL EEPROM_CS VDD TIMER_OUT TALLY MONI_CTL MONI_UD REMOTE S_DT_IN S_DT_OUT S_CLK AFZ_DATA AFZ_CLK RXD TXD AUDIO_CS LCD_SO LCD_SI LCD_CLK VDD VSS AVSS VRefL BATT_CHK KEY_A KEY_B ZOOM_SW IR_AD HALL_AD Z_PTR_AD F_PTR_AD TG_CS BATT_SW MONI_RVS VRefH In/Out In In Out Out Out Out Out Out Out Out In In In Out Out Out Out In Out In Out Out In In In In In In In In Out In In Description Clock 1 sec. Interrupt AF data readout timing VF/MONI select signal LCD data load pulse VF_REG4.8V ON/OFF control Chip select signal to EEPROM IC1003 Power supply Not used Tally lamp MONI_LCD back light control MONI_LCD L/R UP/DOWN reverse control Remote control input Serial data input from DECK_CPU EEPROM RTC Serial data output to DECK_CPU TG/VDRIV CDS/AGC/ADC EEPROM RTC Serial clock Not used Serial data output to AUDIO FZ_MDA DAC/EVR Serial data output to AUDIO FZ_MDA DAC/EVR RS232C data input RS232C data output Chip select signal to AUDIO IC2200 Serial data input from LCD EEPROM Serial data output to LCD EEPROM Serial clock output to LCD EEPROM Power supply GND GND Reference power supply Battery DC input Deck operation switch input Camera operation switch input Zoom switch input AWB IR sensor AD input Iris hall generator AS input ZOOM position sensor AD input FOCUS position sensor AD input Chip select signal to TG/V.DRV IC5501 Not used Not used Not used DC pulg installation detect LCD reverse switch input ADC power supply (REG3V)

Table 2-2-1 SYSCON CPU (IC1001) pin functions (2/3)

2-7

 SYSCON CPU (IC1001) pin functions (3/3)

Pin No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Label AVDD SRV_RST OEM_REG5_CTL MENU_SET_SW RTC_CS DAC_CS CLWE CHWE CRE CALE VDD VSS SEL_SW TRIG_SW DIAL_MANU DIAL_AUTO DIAL_OFF DIAL_PLAY EJECT_SW CAS_SW MONITOR_SW MENU_P_B LCD_CS1 RESERVE F/Z_RST K_CTL KRST/CLR VDD(VPP) IRIS_O/C CDS_CS TG_RST S_MUTE WEN STIL_PLS FADE_H AFADER A_MUTE In/Out Out Out In Out Out Out Out In Out In In In In In In In In In In Out Out Out Out Out Out Out Out In In Out Out Out Description Power supply Not used Reset signal to DECK_CPU IC1401 Not used Menu set switch input Chip select signal to RTC IC1004 Chip select signal to DAC/EVR IC3503 Write enable Write enable Read enable Address latch enable Power supply GND Snap shot mode switch Trigger switch Dial MANUAL Dial AUTO Dial OFF Dial PLAY EJECT switch detect Cassette switch detect Monitor OPEN/CLOSE switch detect Not used Menu dial pulse Chip select signal to LCD EEPROM IC7603 L: fixed Not used Reset signal to F/Z DRIVER IC4851 Shutter sound oscillator control Not used Shutter sound reset/clear signal to CAMERA_DSP IC4301 Not used Power supply Iris OPEN/CLOSE Chip select signal to CDS/AGC/AD IC5601 Reset signal to TG/V.DRV IC5501 Shutter sound mute Memory write timing at slow shutter Odd/Even field discrimination signal at slow playback (FRAME ADVANCE) Fade in/out pulse (Fade last high) Fade in/out pulse (Fade execution: high) Audio mute

Table 2-2-1 SYSCON CPU (IC1001) pin functions (3/3)

2-8

2.2.2 DECK CPU (IC1401) function 1. DECK CPU (IC1401) pin functions (1/5)
Pin No. 1 27 14 28 2 29 3 61 15 45 16 46 4 30 31 62 5 47 17 63 49 32 18 79 6 48 64 7 65 19 33 20 82 50 66 8 67 51 34 9 35 21 52 10 36 22 23 Label CAP_BRK LD_ON ANA_CS OSD_CS VSS MIC_CTL PHY_PD PHY_RST PHY_CNA ANA_PD VMUTE_IN VDDH REWSEL AS VSS DSYSCLK DRWSEL DAS VDDB ADM15 ADM14 ADM13 ADM12 ADM11 ADM10 ADM9 ADM8 VSS ADM7 ADM6 ADM5 ADM4 ADM3 ADM2 ADM1 ADM0 In/Out Out Out Out Out Out Out Out In Out In Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Description Capstan motor brake control Loading motor ON/OFF control Chip select signal to DV_ANA IC3301 Chip select signal to OSD IC1002 GND Power supply control to MIC Power down control to PHY IC3101 Reset output to PHY IC3101 IEEE1394 connection detect (Connect: L) Power down control to DV_ANA IC3301 Video mute input Not used Not used Power supply (REG_3V) Not used Not used Read/write select signal of Bus Address strobe signal of Bus Not used Not used Not used GND Not used Not used Not used Not used Not used Not used Not used Power supply (REG_3V)

Address/Data MPX BUS 16bits DECK_DSP IC3001 DVEQ IC3201

GND

Address/Data MPX BUS 16bits DECK_DSP IC3001 DVEQ IC3201

Table 2-2-2 DECK CPU (IC1401) pin functions (1/5)

2-9

 DECK CPU (IC1401) pin functions (2/5)

Pin No. 11 37 24 38 12 40 53 56 54 55 70 71 69 68 72 88 86 87 85 104 102 103 101 100 84 99 83 120 118 119 116 117 134 135 133 136 132 148 149 152 150 151 147 Label VDDB DK RE WE1 WE0 PVDD PVSS MMOD1 MMOD0 RESET FRQS VSS EXMOD1 EXMOD0 OSCI OSC0 VDDH SYSCLK EQ_CS DV_CS CS1 CS0 VDD STIL_PLS V_PB_L DV_RST EQ_TRST EQ_RST VSS HID3 REC_I PBH REEL_LED REC_SAFE VDDH CAM2 CAM1 CAM0 AVSS In/Out In Out Out In In Out Out Out Out Out Out Out Out Out Out Out In In In In Description Power supply (REG_3V) Servo CPU ready signal (Low: Deck mode) Read enable signal Not used Write enable signal Power supply (REG_3V) GND Control port for FLASH CPU Reset input from SYSCON CPU IC1001 L: fixed GND H: fixed H: fixed 27MHz clock input form TG/V.DRV IC5501 Not used Power supply (REG_3V) Not used Chip select signal to DV_EQ IC3201 Chip select signal to DECK_DSP IC3001 Not used Not used Power supply (REG_3V) Odd/Even field discrimination signal at slow playback (FRAME ADVANCE) Video track area recording off signal Reset signal output to DECK_DSP IC3001 Reset signal output to DV_EQ IC3201 (for Boundly scan) Reset signal output to DV_EQ IC3201 GND Head switch pulse (control of recording current measure circuit) ON/OFF control for recording circuit to PRE/REC IC ON/OFF control for playback circuit to PRE/REC IC Reel sensor LED control REC safty switch Power supply (REG_3V) Mechanism position detect from rotary encoder GND Not used Not used Not used Not used

Table 2-2-2 DECK CPU (IC1401) pin functions (2/5)

2-10

 DECK CPU (IC1401) pin functions (3/5)

Pin No. 164 166 167 163 168 165 183 181 184 200 182 199 198 216 214 239 213 240 197 227 212 226 196 238 180 225 195 237 179 211 210 236 194 224 209 235 178 223 193 208 Label BCID3 BCID2 BCID1 DEW_SENS E_SENS S_SENS VREFH AVDD ADTRG NMI VSS DV_INT DRAM_PG DRAM_FG MSELECT VDD MDA_CS SRV_RDY AGC_RST TRIG_OUT ADC_PWD1 ADC_PWD0 VSS ADC_DEM1 ADC_DEM0 In/Out In In In In In In In In In In In In Out Out Out Out Out Out Out Out Description Not used Not used Not used Not used Not used Not used Cassette tape ID board information Dew sensor detect End sensor detect Start sensor detect Reference voltage Power supply (REG_3V) H: fixed H: fixed GND Not used Not used Not used Not used DV_DSP interrupt signal Drum PG Drum FG DECK_CPU chip select input form SYSCON CPU IC1001 Power supply (REG_3V) Chip select signal to MDA IC1601 DECK_CPU ready signal output to SYSCON CPU IC1001 Video output clamp control to A/V OUT SECTION Remote pause output Not used Not used D/A power control to AUDIO AD/DA IC2101 (power down: L ) A/D power control to AUDIO AD/DA IC2101 (power down: L) GND Sampling frequency select to AUDIO AD/DA IC2101 (ADC_DEM0/ADC_DEM1:frequency L/L:44.1k, L/H:48k, H/L:OFF, H/H:32k) Not used Not used Not used

Table 2-2-2 DECK CPU (IC1401) pin functions (3/5)

2-11

 DECK CPU (IC1401) pin functions (4/5)

Pin No. 162 222 177 234 192 207 176 233 191 221 175 232 159 220 206 231 190 204 174 219 205 230 189 218 173 229 203 201 187 185 188 186 171 169 172 170 158 154 156 153 157 155 Label VDDH HID A_PLL V_PLL DRUM_REF CAP_REF VSS TR FR DV_INT SPA HID_IN VDD S_REEL T_REEL TR CAP_FG DRUM_FG DRUM_FG TAPE_LED VSS VD VDD VSS In/Out Out Out Out In In In In In In In In In In In Out In Description Not used Not used Not used Not used Power supply (REG_3V) Head switch pulse output Not used Not used Drum offset voltage output to MDA IC1601 Capstan offset voltage output to MDA IC1601 Not used Not used Not used Not used GND HID reference (Drum 150Hz reference) Frame pulse from DECK_DSP IC3001 DV_DSP interrupt signal Pulse for ATF sample Head switch pulse input Power supply (REG_3V) SUP reel pulse TU reel pulse HID reference (Drum 150Hz reference) Capstan FG Drum FG Not used Drum FG Tape sensor LED control GND Vertical reference pulse form CAMERA_DSP IC4301 Not used Not used Not used Not used Power supply (REG_3V) Not used Not used Not used Not used Not used GND

Table 2-2-2 DECK CPU (IC1401) pin functions (4/5)

2-12

 DECK CPU (IC1401) pin functions (5/5)

Pin No. 140 138 142 139 141 137 124 122 123 121 125 106 107 105 109 108 93 91 94 90 92 89 78 74 76 73 77 59 75 58 60 57 43 42 44 41 Label VDDH EEP_CLK EEP_OUT EEP_IN EEP_CS VPP BR VSS ANA_CLK ANA_IN ANA_OUT MDA_CLK MDA_IN VDD MDA_OUT SYS_CLK SYS_IN SYS_OUT VSS TXD RXD OSD_CLK OSD_DATA MIC_SCL VDDH MIC_SDA In/Out Out Out In Out Out In In Out In Out In Out Out Out In Description Not used Not used Not used Not used Not used Not used Power supply (REG_3V) Not used Not used Not used Not used Power supply (REG_3V) H: fixed GND Serial clock to DV_ANA IC3301 Serial data bus output to DV_ANA IC3301 Serial data bus input from DV_ANA IC3301 Serial clock from MDA IC1601 Serial bus data output from MDA IC1601 Power supply (REG_3V) Serial bus data input from MDA IC1601 Serial clock from SYSCON CPU IC1001 Serial bus data output to SYSCON CPU IC1001 Serial bus data input from SYSCON CPU IC1001 Not used GND RS232C output RS232C input Serial clock to OSD IC1002 Serial bus data to OSD IC1002 Not used Serial clock for MIC Power supply (REG_3V) Serial data fro MIC Not used Not used

Table 2-2-2 DECK CPU (IC1401) pin functions (5/5)

2-13

2.2.3 MDA IC (IC1601) function 1. MDA IC (IC1601) pin locations

TEST2 TEST1 D.DETECT D.OSC D.PCV D.PCI D.CL D.ECR D.EC GND2 VREG DIN CS CLK C.COM C.BU C.BRK C.RCC C.CL C.EC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

D.PGSOUT D.PGOUT D.PGD.FGPG+ D.FGD.FGOUT D.FGSOUT D.VS GND1 D.UIN D.VIN D.WIN D.COM D.SL D.ISET L.REF D.UNREG D.VM NC NC

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

C.ECR C.PCI C.PCV C.VS C.SD C.VCC C.FG+ C.FGC.FGOUT C.FGSOUT C.HU+ C.HUC.HV+ C.HVC.HW+ C.HWC.UNREG C.VM NC NC

10 11 12 13 14 15 16 17 18 19 20

FGND1 D.U D.v NC D.W NC D.GND NC L.FWD FGND2 L.GND L.REV C.GND L.UNREG NC C.U NC C.V NC C.W

Fig. 2-2-3 MDA IC (IC1601) pin locations

2-14

2. MDA IC (IC1601) capstan servo section block diagram

VCC REG_4.8V C.UNREG

35

24
C.VM

C.F/R

DIRECTION

23

HALL

30 29

C.HU+ C.HU-

HALL

28 27

C.HV+ C.HV-

UPPER/LOWER DIVISION

DRIVE SIGNAL MIXING

16

C.U

HALL

26 25

C.HW+ C.HW-

18

C.V

CAP.M 20 43
C.RCC C.W

RIPPLE CANCEL

CAP.M TSD
C.U C.V C.W

13
L.SATURATION PREVENT C.U C.V C.W U.SATURATION PREVENT

C.GND

CAP_REF REG_4.8V

41 40

C.EC C.ECR TORQUE CTL C.MODE

42

C.CL

CURRENT LIMIT BRAKE

C.U C.V C.W SHORT CIRCUIT DETECT

DC-DC

44 33 34

C.BRK

39 38
C.U C.V C.W C.EC PW.SAVE

C.PCI C.PCV

C . F G C . F G+

37
C.VM C.MODE

C.VS

32
CAP_FG

C.FGOUT

C.FGSOUT

31

POWER SAVE

69
GND

Fig. 2-2-4 MDA IC (IC1601) capstan servo section block diagram

2-15

3. MDA IC (IC1601) drum servo section block diagram

VCC

D.UNREG D.SL D.ISET

35

74 75

77
D.VM

78

SLOPE 70
D.UIN D.U

D.VIN

71

UPPER/LOWER DIVISION

SELECT LOGIC

DRIVE SIGNAL LOGIC

D.WIN D.COM

D.V

72 73

START
D.DETECT

D.W

58

DETECT 7
D.U D.V D.W L.SATURATION PREVENT D.U D.V D.W U.SATURATION PREVENT

DRUM.M
D.GND

D.OSC

57

OSC

D.BRK DRUM_REF D.EC D.ECR TORQUE CTL

BRAKE TSD

55

D.PCI

DC-DC 56
D.PCV

52
REG_4.8V

53

D.U D.V D.W

CURRENT FEED BACK D.VM ERROR AMP D.PG.SM

68

D.VS

54

D.CL

CURRENT LIMIT

PW.SAVE D.PGSOUT

D.FGSOUT

D.PGOUT

D.FGOUT

D.FGPG+

65 64

66

67

D.PG

D.FG

POWER SAVE

VREG

63

62

61

69
GND

50

DRUM_FG

DRUM_PG

Fig. 2-2-5 MDA IC (IC1601) drum servo section block diagram

2-16

4. MDA IC (IC1601) interface section block diagram

L.UNREG TEST1 TEST2 VCC

14
L.REF

59

60

35

76

CONTROL LOGIC

L.FWD

L.FIN

L.RIN

L.REV

12

LOADING MOTOR TSD

L.GND

11 SHIFT REGISTER
D0 D1 D2 D3 D4 D5 D6 D7 PW_SAVE D.PG.SM D.BRK L.FIN

DATA-LATCH

C.F/R C.MODE

47
CLK

49
DIN

48
CS

69
GND

Fig. 2-2-6 MDA IC (IC1601) interface section block diagram

2-17

5. MDA IC (IC1601) pin functions (1/2)

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D.U D.V NC D.W NC D.GND NC L.FWD FGND2 L.GND L.REV C.GND L.UNREG NC C.U NC C.V NC C.W NC NC C.VM C.UNREG C.HWC.HW+ C.HVC.HV+ C.HUC.HU+ C.FGSOUT C.FGOUT C.FGC.FG+ C.VCC C.SD C.VS C.PCV C.PCI C.ECR Label FGND1 In/Out Out In Out Out Out Out Out In In In In In In In Out Out In In Out In In In In Output of FG schmitt for Capstan Motor section Output of FG amp. for Capstan Motor section FG input of Capstan Motor section VCC of BIP control section Short detect output of Capstan Motor section Motor power supply control of Capstan Motor section Output of saturation prevent phase compensation for Capstan section (upper side) Output of saturation prevent phase compensation for Capstan section (lower side) Input of reference torque control for Capstan Motor section Hall input of Capstan Motor section Sub ground of IC Output of motor drive for Drum Motor section Output of motor drive for Drum Motor section Not used Output of motor drive for Drum Motor section Not used Ground for the Drum Motor section (Current detect register) Not used Output of motor drive for Loading Motor section Sub ground of IC Ground for the Loading Motor section Output of motor drive for Loading Motor section Ground for the Capstan Motor section (Current detect register) Power supply for Loading Motor section (UNREG) Not used Output of motor drive for Capstan Motor section Not used Output of motor drive for Capstan Motor section Not used Output of motor drive for Capstan Motor section Not used Not used VM of Capstan Motor section Power supply for Capstan Motor section (UNREG) Description

Table 2-2-3 MDA IC (IC1601) pin functions (1/2)

2-18

 MDA IC (IC1601) pin functions (2/2)

Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C.EC C.CL C.RCC C.BRK C.BU C.COM CLK CS DIN V.REG GND2 D.EC D.ECR D.CL D.PCI D.PCV D.OSC D.DETECT TEST1 TEST2 D.PGSOUT D.PGOUT D.PGD.FGPG+ D.FGD.FGOUT D.FGSOUT D.VS GND1 D.UIN D.VIN D.WIN D.COM D.SL D.ISET L.REF D.UNREG D.VM NC NC Label In/Out In In In In In In In Out In In In In In In In Out Out In In In Out Out Out In In In Out Middle point of motor for Drum Motor section Shape of slope waveform for Drum Motor section Current control of SL terminal for Drum Motor section (Resister connect) Setting of output voltage for Loading Motor section Power supply for the Drum Motor section (UNREG) VM of Drum Motor section Not used Not used Input of BEMF comparator for Drum Motor section Description Input of torque command control for Capstan Motor section Input of current limmit for Capstan Motor section Ripple cancel variable terminal for Capstan Motor section (Register connect) Brake input of Capstan Motor section (H: Brake) Not used Not used Clock signal input Chip select signal input Serial data input Internal reference voltage output Ground for logic system Input of torque command control for Drum Motor section Input of reference torque control for Drum Motor section Input of current limmit for Drum Motor section Output of saturation prevent phase compensation for Drum section (upper side) Output of saturation prevent phase compensation for Drum section (lower side) Starting signal oscillation for Drum Motor section Detect mode time setting for Drum Motor section Not used Not used Output of PG schumitt for Drum Motor section Output of PG amp. for Drum Motor section Input of PG for Drum Motor section Input of FG/PG common for Drum Motor section Input of FG for Drum Motor section Output of FG amp. for Drum Motor section Output of FG schumitt for Drum Motor section Control of motor power supply for Drum Motor section Ground for BIP control section

Table 2-2-3 MDA IC (IC1601) pin functions (2/2)

2-19

2.2.4 CDS AGC AD IC (IC5601) function 1. CDS AGC AD IC (IC5601) pin locations and block diagram
ADCLK SPBLK SPSIG

DVDD

AVDD

VRM2

DVSS 14

AVSS

OBP

CLP

24

23

22

21

20

19

18

17

16

15

13

AVSS AVDD CDSIN TESTY TESTC AVSS AVDD VRB VRM VRT BIAS NC

25 26 27 28 29 30 31 32 33 34 35 36 BIAS Serial I/F Gain Select Output Latch 10bit A/D CDS AGC

OE

NC

12 11 10 9 8 7 6 5 4 3 2 1

NC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PBLK

Clamp

37

38

39

40

41

42

43

44

45

46

47

48

AVSS

AVSS

SDATA

DVSS

AVDD

AVDD

Fig. 2-2-7 CDS AGC AD IC (IC5601) pin locations and block diagram

2-20

DVDD

DVSS

SCK

NC

NC

CS

2. CDS AGC AD IC (IC5601) pin function

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Label PBLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 NC OE DVSS DVDD ADCLK OBP SPBLK SPSIG AVSS AVDD NC CLP VRM2 AVSS AVDD CDSIN TESTY TESTC AVSS AVDD VRB VRM VRT BIAS NC AVSS AVDD NC NC AVDD AVSS CS SCK SDATA DVDD DVSS DVSS In/Out In Out Out Out Out Out Out Out Out Out Out In In In In In Out In In In In In In Description Pre-blanking pulse input (LSB)

Digital output

(MSB) Not used Digital output enable control Ground for the digital system Power supply for the digital system A/D converter clock input Optical balck clamp pulse input Pre-charge level sample and hold pulse for CDS Level sample and hold pulse for CDS Ground for the analog system Power supply for the analog system Not used Clamp voltage Reference voltage Ground for the analog system Power supply for the analog system CDS input Test signal input - Y Test signal input - C Ground for the analog system Power supply for the analog system Reference voltage Reference voltage Reference voltage Internal bias Not used Ground for the analog system Power supply for the analog system Not used Not used Power supply for the analog system Ground for the analog system Serial interface chip select input Serial clock input Serial data input Power supply for the digital system Ground for the digital system Ground for the digital system

Table 2-2-4 CDS AGC AD (IC5601) pin function

2-21

2.2.5 B/W LCD driver IC (IC7001) function (for GR-DVF11U) 1. B/W LCD DRIVE IC (IC7001) pin locations and block diagram
BRIGHTNESS

BL_GND

GAMMA

VIDCH

VIDLC

MVDD

RENO 26

36

35

34

33

32

31

30

29

28

27

25

H_SKIPPING SSTART SMCOMP VDDH SMGND SMOUT VBAT BLACK_LEVEL H_SYNC V_SYNC VHIO_SEL REF_GND

37 38 39 40 41 42 43 44 45 46 47 48

Backlight Current Control

Band Gap Reference

RENE

VIDL

VBG

OK

BL

Video Amp

24 23

HCK HPL V_REF VSS VDD VEE V_COM HODL VPL VCK VIDH PDR

32fh Ramp DC-DC Convertoer 416fh 32fh 1/13 Hsync Timing Generator Vsync PLL DC Restore OSD Level Detect Blkg White Video Adjust Video Amp Sync Separator

22 21 20 19 18 17 16 15 14 13

10

11

12

PLL_FILTER

HODL_SEL

VIDEO_IN

OSD_IN

525/625

SLEEP

SFLTR

A_GND

CLAMP

Fig. 2-2-8 B/W LCD DRIVE IC (IC7001) pin locations and block diagram

2-22

D_GND

A_GND

GAIN

2. B/W LCD driver IC (IC7001) pin function

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Label SLEEP OSC_CTL OSD_IN A_GND VIDEO_IN CLAMP PLL_FILTER GAIN SYFILTER 525/625 D_GND A_GND PDR VIDH VCK VPL HODL V_COM VEE VDD VSS V_REF HPL HCK RENE RENO VIDL VIDLC VIDHC BACK_LEVEL BL_GND BL VBG BRIGHTNESS OK NC SMPFILTER SSTART SMCOMP VDDH SMGND SMOUT VBAT ANALOG_VBAT H_SYNC V_SYNC VHIO_SEL REF_GND In/Out In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In Out Description Logic level input. A logic low sets the IC into the sleep mode Not used (L: fixed) Not used (L: fixed) Ground for the analog sections and signals Input for standard level monochrome video, 525 or 625 lines Clamp capacitor, to ground, for the video black level clamp Filter pin for the internal horizontal PLL DC control for the gain of the video signal path Filter pin for the sync separator Video system select (L: 525 line, H: 625 line) Ground for the digital sections and signals Ground for the analog sections and signals Power down reset output to the LCD panel (Active Low) Upper video drive signal to the LCD panel Vertical clock output to the LCD panel Vertical start pulse output to the LCD panel Column inversion control output to the LCD panel Internally generated supply for the LCD panel (5.8V) Internally generated supply for the LCD panel (2.0V) Internally generated supply for the LCD panel (9.0V) Reference ground for the LCD panel Internally generated supply for the LCD panel (VBat/2V) Horizontal start pulse output to the LCD panel Horizontal clock output to the LCD panel Even Row enable output to the LCD panel Odd Row enable output to the LCD panel Lower video drive signal to the LCD panel Connect to VIDHC through a compensation capacitor Connect to VIDLC through a compensation capacitor DC control to adjust the video output black level Ground pin for the backlight LED current Current sink for the backlight LED current Output of the bandgap reference DC control for the brightness of the backlight LED Not used Not used Not used Not used Not used (H: fixed) Internally generated supply voltage (11.0V) Ground pin for the DC/DC converter Not used Power supply input (VF_4.8V) Power supply Not used Not used 45, 46 pins I/O control (L: OUT, H: INPUT) Ground for the DC/DC converter

Table 2-2-5 B/W LCD driver IC (IC7001) pin function

2-23

VICTOR COMPANY OF JAPAN, LIMITED

Printed in Japan 9909 (TM1)