Laboratory 2: Amplitude Modulation (AM) Implementation

I. Introduction In the present project, students are required to implement and simulate a simple amplitude modulated (AM) circuit in the Simulink environment (DSPBuilder), using two methodologies to build the cos() function: a hard-coded look-up table and the NumericalControlled Oscillator (NCO) Altera IP core. The design has to be downloaded to the FPGA device on the Stratix EP1S25 DSP development board to perform hardware simulation and verification. II. Theory Amplitude Modulation or AM involves the encoding of a carrier signal by variation of its amplitude in accordance with an input signal. In Amplitude Modulation (AM) the carrier signal cos(c n) modulates a signal x( n) , which typically has at least 10 times lower frequency than the carrier, as follows:

y ( n) = cos(c n) x( n)
Where is the carrier angular frequency with 0 c . c

(1)

However it is not always possible in real-time to call the function cos() numerous times (many computations required). Three more efficient approaches are: To use a hard-coded look-up table for the cos() function, where the index of the table is the input of the function and the values inside the table are the possible outputs To use an oscillator To use a recursive approach for the computation of the cos() function

In the present project, we will use the first two approaches to implement the cosine function. For the second method, the NCO IP core from Altera will be used to generated the required carrier signal. III. Background about DSP Builder and the Altera EP1S25 DSP development board Capabilities of DSP Builder and Simulink were introduced with an example design in the Tutorial: A/D and D/A Conversion on Altera Stratix EP1S25 Development Board using Simulink and DSP Builder [1], which contain a design targeting the 12-bit 125MHz A/D

and 14-bit 165 MHz D/A converters onboard. For further information about the Stratix EP1S25 DSP development board, the student is referred to [2] and [3]. IP cores are megafunctions that are already tested and optimized for specific platforms, in this case, Altera FPGAs. They avoid building functions from scratch, reducing design and test time. In the laboratory, we have several evaluation-version IP cores. They can be parameterized, simulated and downloaded to hardware; although this last feature is restricted to the time in which the design is being tested in hardware (once the connection between the PC and the board is terminated, the program running the IP core is deleted from the FPGA). For more information about Altera IP cores, the student is referred to [5]. In the present lab, students will implement the required cos() function using the Numerically Controlled Oscillator (NCO) IP core v6.1. NOTE: previous IP core versions are not guaranteed to work with the installed Matlab and Quartus II versions. IV. Requirements For this laboratory, students are required to accomplish the next requirements: Implement an AM circuit by applying Equation (1) from Section II. The cosine function must be implemented using a hard-coded look-up table, where the index of the table is the input of the function and the values inside the table are the possible outputs. The signal to be modulated must be acquired through the A/D converter onboard, and then multiplied with the generated cosine function. The resultant signal must be converted back to analog through the D/A converter. You can use the design given in the Tutorial [1] as a template. Place SignalTap II nodes at the output of the AM modulator and at the output of the cosine function to acquire the modulated and carrier signals, respectively (see Figure 1, Tutorial [1]). To implement the cosine function use Counter, ROM EAB and Pattern blocks from the DSPBuilder library, following the same approach given in [SineWave_Generator, 6] to design the look-up table approach. The ROM EAB block points to the hex file containing the points of the desired cosine function. The student must determine the values and required number of points for the cosine function, and implement the hex file. Follow the next specifications: Look-up table cosine function: Precision: 16 bits Cosine frequency: 600kHz Sample frequency: 80MHz

Max. number of points in the look-up table:

20

NOTE: it must be chosen the optimal number of points that minimizes quantization errors and maximizes the approximation to the required cosine frequency. Once, the points have been determined, implement the hex file. You can use Quartus II to do so. However, it is necessary that the points have the appropriate format. Hex files built by using Quartus II require numbers in unsigned decimal format. Thus, first convert the points to integer numbers by using the next Matlab command: values = round(x*2^Var-1); Var must contain the necessary value to have the bitlength of the points at 16 bits maximum, as required from the specifications. Then, convert values to unsigned fixed-point, as follows: q = quantizer('fixed',[16 0]); LUT = num2hex(q,values); hex2dec(LUT) These commands first create a quantizer for fixed-point numbers, fixing the number of bits at 16. Then, the values are converted to hexadecimal, and finally to the required unsigned decimal format. Afterwards, you can create the hex file in Quartus II with the obtained points. Open Quartus II, File > New and select Other Files in the pop-up window. Select Hexadecimal (Intel-format) File from the list, and click OK. A new window opens and asks for number of words and word size. Type 16 in the Word size field (following the look-up table specifications), and type the determined number of points from your previous analysis in the Number of words field. A table is created. Now fill the table with the point values for the cosine function. Save the file in the same directory where your Simulink design is located, and close Quartus II. Finally, specify the recently created hex file in the ROM EAB Block in your design in Simulink. Double click in the ROM EAB icon, and fill the Input Hex File field with the name of the hex file. Simulate your circuit in Simulink to modulate different sinusoidal signals up to 5MHz, observing the modulation behavior. What happens if the input signal frequency is closed to the carrier frequency?

The second part of the project involves the implementation of the cosine function but this time using the NCO IP core. Add to your AM circuit an additional cosine function. This new cosine function must be implemented using the NCO Altera IP core. From the Megacore Functions in the Altera DSPBuilder library, drag and place into your design the nco_v6_1 block. Double click the block to visualize the NCO Compiler v6.1. A menu with several options is available. If you click on Documentation, a pop-up window will appear with information concerning to the IP core. The student is encouraged to review the NCO User Guide v6.1. To parameterize the IP core, click on the Step1: Parameterize button in the NCO Compiler window. The student will select the required options to achieve the next specifications: Architecture: Accumulator precision: Angular precision: Cosine magnitude: Cosine frequency: Sampling frequency: multiplier-based using the multipliers embedded in the FPGA. 32 bits 13 bits 16 bits 600kHz 80MHz

Apply Phase Dithering to have a minimum attenuation of 90dB. What is the required dither level to achieve so? How many FPGA resources are estimated to be consumed by the NCO? Once parameterized, click on Finish, and click the Step2: Generate button in the NCO Compiler to compile and generate the IP core. Once done, the NCO block updates automatically, and is ready to interconnect to your circuit. Place a SignalTap II node at the output of the NCO to acquire the carrier signal during hardware tests later. Simulate your circuit in Simulink using the NCO as cosine generator to modulate different sinusoidal signals up to 5MHz, observing the modulation behavior. You final design must permit the user to select in real-time which cosine generator is going to use at a time: the look-up table based or the NCO-based method. To do so, use one of the push-buttons provided onboard. Download your design to the Stratix EP1S25 DSP development board and test it by using a signal generator and oscilloscope. Observe the effect of the modulation

with sine waves from 20kHz to 5MHz. What range of frequencies works appropriately with the AM circuit? NOTE: because of the IP core, the Signal Compiler will call the Quartus II Programmer during programming. The next message will appear, specifying that once the programmer is disconnected the FPGA will be erased:

Click OK, and then program the device through the next screen:

Check the box below the column Program/Configure, and click the Start button on the left to download the program to the FPGA. The next window will appear:

Your program will run onboard until you click on Cancel and close the Quartus II Programmer window.

While the program is running onboard, capture and analyze the data using SignalTap II Analysis. Also, using the data acquired through SignalTap II, show the frequency response using fft command for several input signals in the range from 20kHz to 5MHz. NOTE: you can use similar commands to those given in the Tutorial [1], Importing the data acquired from the board in Matlab workspace, step2. What differences can be found between the approach using NCO with multipliers and the look-up table? Make a list with at least 3 reasons to justify why one of the approaches is superior to the other in your design.

V. Submission You must submit: The Simulink model (.mdl) developed using DSP Builder blocks with two approaches to implement the cosine function: hard-coded look-up table and multiplier-based NCO. A report describing the general procedure to accomplish the project requirements, and answering questions regarding modulation techniques. The report must contain graphs showing the modulated and carrier signals, and frequency response using fft command for different inputs. VI. References [1] Tutorial: A/D and D/A Conversion on Altera Stratix EP1S25 Development Board using Simulink and DSP Builder. [2] DSP Builder User Guide, ver. 5.1.0, c:\altera\61\DSPBuilder\Doc\ug_dspbuilder.pdf Altera, 2005. Local copy at:

[3] Stratix EP1S25 DSP Development Board Data Sheet, ver. 1.6, Altera, 2004. Available online at: http://www.altera.com/literature/ds/ds_stratix_dsp-board-starter.pdf or local copy at: c:\altera\61\kits\stratix_dsp_kit-v1.3.0\Docs\ds_stratix_dsp_bd.pdf [4] DSP Development Kit Stratix & Stratix Professional Edition (Getting Started User Guide), ver. 1.3.0 rev. 1, Altera, 2004. Available online at: http://www.altera.com/literature/ug/ug_stratix_dsp_kit.pdf or local copy at: c:\altera\61\kits\stratix_dsp_kit-v1.3.0\Docs\ug_stratix_dsp_kit.pdf [5] IP MegaStore, Altera. Available online at: http://www.altera.com/products/ip/ipmindex.html

[6] Reference Design, Altera, 2004. Local copy at: C:\altera\61\DSPBuilder\DesignExamples\Demos\Filters\FilteringLab\Stap\stfilteringlab. mdl