FPGA Lab

Objective

M.Tech(I Year)

Now a days, FPGAs are becoming alternatives to ASICs. Most of the digital system designers opt, FPGAs for their low cost, reprogram ability, less time to market features. In this lab, Basic designs which are very regular in complex designs are considered for FPGA implementations. These designs are designed and verified using testbenches written using VHDL. Nexys2 board is chosen for implementation. It consists of Spartan3E FPGA in which all designs are indented to be implemented.

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FPGA Lab

M.Tech(I Year)

Implementation Flow In this lab, digital logic designs will be implemented using Xilinx Spartan 3E FPGA. Nexyxs2 board is used for these FPGAs. Xilinx ISE is used for designing digital logic, synthesizing, implementing and generating bit - stream files. Adept software is used for downloading this bitstream files to Spartan 3E FPGA of Nexys2 board. The fallowing diagram shows the basic FPGA implementation flow.

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FPGA Lab

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List of Experiments

Cycle -1 (combinational designs) 1. 2. 3. 4. 5. 2 bit comparator 3 to 8 decoder Priority encoder Generic adder 8-bit Barrel shifter

Cycle -2 (Sequential Designs) 6. 7. 8. 9. 10. Parameterized register Universal shift register Universal binary counter Mod-m counter FIFO buffer

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FPGA Lab

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1. Comparator -_2bit

Source code : Library ieee; use ieee.std_logic_1164.all ; entity eq2 is port ( a, b : in std_logic_vector( 1 downto 0 ) ; aeqb : out std_logic ); end eq2;

architecture sop_arch of eq2 is signal p0, pl, p2, p3 : std_logic ; begin -- product terms aeqb <= P0 or pl or p2 or p3 ; -- sum of product terms P0 <= ((not a(1)) and (not b(1))) and ((not a(0)) and ( not b(0))); p3 <= (a(1) and b(1)) and ( a(0) and b(0)) ; pl <= ((not a(1)) and (not b(1))) and (a(0) and b(0)) ; p2 <= (a(1) and b(1)) and ((not a(0)) and ( not b(0))) ; end sop_arch ;

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Testbench library ieee; use ieee.std_logic_1164.all; entity eq2_testbench is end eq2_testbench; architecture tb_arch of eq2_testbench is signal test_in0, test_in1 : std_logic_vector(1 downto 0) ; signal test_out : std_logic; component eq2 is port ( a, b : in std_logic_vector( 1 downto 0 ) ;

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aeqb : out std_logic ); end component; begin --instantiate the circuit under test uut : eq2 port map( a b => test_in0, => test_in1,

aeqb => test_out ); -- testvector generator process begin --test vector 1 test_in0 <= "00"; test_in1 <= "00";

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wait for 200 ns ; -- test vector 2 test_in0 <= "01";

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test_in1 <= "00"; wait for 200 ns; --testvector 3 test_in0 <= "01"; test_in1 <= "11"; wait for 200 ns; --test vector 4 test_in0 <= "10";

test_in1 <= "10"; wait for 200 ns; --test vector 5 test_in0 <= "10"; test_in1 <= "00"; wait for 200 ns; -- test vector 6 test_in0 <= "11";

test_in1 <= "11"; wait for 200 ns; -- test vector 7 test_in0 <= "11"; test_in1 <= "01"; wait for 200 ns; end process; end tb_arch;

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FPGA Lab

M.Tech(I Year)

User Constraint File # Leds For Outputs NET "aeqb" LOC = "J14";

# Switches For Inputs NET "a<0>" LOC = "G18"; NET "a<1>" LOC = "H18"; NET "b<2>" LOC = "K18"; NET "b<3>" LOC = "K17";

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FPGA Lab

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2. Decoder_3to8 Source code: library ieee; use ieee.std_logic_1164.all; entity dec3_8 is port ( a : in in std_logic_vector (2 downto 0 ) ; std_logic;

en : y ); end dec3_8; :

out std_logic_vector (7 downto 0 )

architecture cond_arch of dec3_8 is begin

y <=

"00000000" "00000001" "00000010" "00000100" "00001000" "00010000" "00100000" "01000000" "10000000" ;

when when when when when when when when

(en = '0') (a = "000") (a = "001")

else else else

(a = "010") else (a = "011") else (a = "100") else (a = "101") else (a = "110") else

end cond_arch;

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Testbench Library ieee; use entity end ieee.std_logic_1164.all; dec3_8 testbench dec3_8testbench; tb_arch of dec3_8testbench is : std_logic_vector(2 downto 0) ; std_logic; std_logic_vector(7 downto 0); is is

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architecture signal test_in

signal test_en : signal test_out : component

dec3_8

port ( a en y ); End component; begin --instantiate the circuit under test uut : dec3_8 port map( a en y ); => => => test_in, test_en, test_out : in : in : std_logic_vector (2 downto 0 ) ; std_logic;

out std_logic_vector (7 downto 0 )

-- testvector generator process begin

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test_en

<=

'0';

wait for 200 ns; test_en --test vector 1 test_in <= "000"; <= '1';

wait for 200 ns ; -- test vector 2 test_in <= "001";

wait for 200 ns; --testvector 3 test_in <= "010";

wait for 200 ns; --test vector 4 test_in <= "011";

wait for 200 ns; --test vector 5 test_in <= "100";

wait for 200 ns; -- test vector 6 test_in <= "101";

wait for 200 ns; -- test vector 7

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test_in <= "110";

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wait for 200 ns; -- test vector 8 test_in wait; end process; end tb_arch; <= "111";

User Constraint File # Leds For Outputs NET "y<0>" LOC = "J14"; NET "y<1>" LOC = "J15"; NET "y<2>" LOC = "K15"; NET "y<3>" LOC = "K14"; NET "y<4>" LOC = "E17"; NET "y<5>" LOC = "P15"; NET "y<6>" LOC = "F4"; NET "y<7>" LOC = "R4";

# Switches For Inputs NET "en" LOC = "G18"; NET "a<0>" LOC = "H18"; NET "a<1>" LOC = "K18"; NET "a<2>" LOC = "K17";

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FPGA Lab

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3. Priority encoder Source code : Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Entity prio_encoder is port ( r pcode ); end prio_encoder ; : in : out std_logic_vector (4 downto 1) ; std_logic_vector (2 downto 0)

architecture cond_arch of prio_encoder is begin pcode <= "100" "011" "010" "001" "000"; end cond_arch; Testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; when (r(4) = '1' ) when (r(3) = '1') when (r(2) = '1') when (r(1) = '1') else else else else

entity end

prio_encoder_testbench is prio_encoder_testbench;

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architecture Behavioral of prio_encoder_testbench is

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signal test_in signal test_out

: :

std_logic_vector(4 downto 1); std_logic_vector(2 downto 0);

component prio_encoder is port ( r pcode ); End component; : in std_logic_vector (4 downto 1) ;

: out std_logic_vector (2 downto 0)

begin

--instantiate the circuit under test uut : prio_encoder port map( r pcode ); => => test_in, test_out

-- testvector generator process begin

--test vector 1 test_in <= "0000";

wait for 200 ns ;

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-- test vector 2 test_in <= "0001";

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wait for 200 ns; --testvector 3 test_in <= "0010";

wait for 200 ns; --test vector 4 test_in <= "0011";

wait for 200 ns; --test vector 5 test_in <= "0100";

wait for 200 ns; -- test vector 6 test_in <= "0101";

wait for 200 ns; -- test vector 7 test_in <= "0110";

wait for 200 ns; -- test vector 8 test_in <= "0111";

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wait for 200 ns; -- test vector 9 test_in <= "1000";

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wait for 200 ns; -- test vector 10 test_in <= "1001";

wait for 200 ns; -- test vector 11 test_in <= "1010";

wait for 200 ns; -- test vector 12 test_in <= "1011";

wait for 200 ns; -- test vector 13 test_in <= "1100";

wait for 200 ns; -- test vector 14 test_in <= "1101";

wait for 200 ns; -- test vector 15 test_in <= "1110";

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FPGA Lab

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wait for 200 ns; -- test vector 16 test_in wait; end process; end behavioral; <= "1111";

User Constraint File # Leds NET "pcode<0>" LOC = "J14"; NET "pcode<1>" LOC = "J15"; NET "pcode<2>" LOC = "K15";

# Switches For Inputs NET "r<1>" LOC = "G18"; NET "r<2>" LOC = "H18"; NET "r<3>" LOC = "K18"; NET "r<4>" LOC = "K17";

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FPGA Lab

M.Tech(I Year)

4. Generic Adder Source code : Library ieee; Use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gen_add_w_carry is generic (N : integer := 4); port ( a,b : cout sum ); end gen_add_w_carry ; architecture signal begin a_ext b_ext sum_ext sum cout end arch; Testbench Library ieee; Use ieee.std_logic_1164.all; use ieee.numeric_std.all; <= <= <= <= <= unsigned('0' & a); unsigned('0' & b); a_ext + b_ext; std_logic_vector (sum_ext (N-1 downto 0)); sum_ext(N); arch of gen_add_w_carry : is : : in std_logic_vector(N-1 downto 0);

out std_logic; out std_logic_vector (N-1 downto 0)

a_ext,

b_ext, sum_ext

unsigned(N downto 0 );

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entity gen_add_w_carry_testbench is end gen_add_w_carry_testbench; architecture signal signal signal signal Behavioral of : : gen_add_w_carry_testbench std_logic_vector( 3 downto 0); std_logic_vector( 7 downto 0); std_logic_vector(15 downto 0); std_logic; is

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a4, b4, sum4 a8, b8, sum8

a16, b16, sum16 : c4, c8, c16 :

component gen_add_w_carry generic (N : integer := 4); port ( a, b cout sum ); end component; begin --instantiate the circuit under test --------------------------------instantiate 8 - bit adder adder_8_unit : gen_add_w_carry : : : in std_logic_vector(N-1 downto 0);

out std_logic; out std_logic_vector (N-1 downto 0)

generic map ( N => 8) port map( a b cout sum ); => a8, => b8, => c8, => sum8

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-- instantiate 16-bit adder adder_16_unit : gen_add_w_carry generic map ( N => 16) port map ( a => a16, b => b16, cout => c16, sum => sum16 );

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-- instantiate 4 - bit adder -- (generic mapping omitted, default value 4 used)

adder_4_unit : gen_add_w_carry port map( a => a4, b => b4, cout => c4, sum => sum4 );

process begin a4 b4 a8 <= "1011"; <= "1100"; <= "00011110";

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b8 a16 b16 wait ; end process; end behavioral; <= "00111001"; <= "0011010110101101"; <= "1011011001100111";

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User Constraints File # Leds NET "sum<0>" LOC = "J14"; NET "sum<1>" LOC = "J15"; NET "sum<2>" LOC = "K15"; NET "sum<3>" LOC = "K14"; NET "sum<4>" LOC = "E17"; NET "cout" LOC = "P15";

# Switches NET "a<0>" LOC = "G18"; NET "a<1>" LOC = "H18"; NET "a<2>" LOC = "K18"; NET "a<3>" LOC = "K17"; NET "b<4>" LOC = "L14"; NET "b<5>" LOC = "L13"; NET "b<6>" LOC = "N17"; NET "b<7>" LOC = "R17";

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FPGA Lab

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5. Barrel shifter Source code : library ieee; use ieee.std_logic_1164.all; entity barrel_shifter is port ( a amt y ); End barrel_shifter ; architecture sel_arch of barrel_shifter is begin with amt select y <= a a(0) & a(3 downto 1) a(1 downto 0) & a(3 downto 2) a(2 downto 0) & a( 3) end sel_arch; when "00", when "01", when "10", when others; -- 11 : : : in in std_logic_vector (3downto 0) ; std_logic_vector (1 downto 0) ;

out std_logic_vector (3downto 0)

Testbench Library IEEE; Use Entity End IEEE.STD_LOGIC_1164.ALL; barrel_shift_testbench is barrel_shift_testbench; Behavioral of barrel_shift_testbench is

architecture

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component port ( a amt y ); End component; Signal signal signal begin uut : barrel_shifter ( a amt y => test_a, => test_amt, => test_y port map test_a test_amt test_y : : : std_logic_vector(3 downto 0); std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); : : : in in out std_logic_vector (3 downto 0) ; std_logic_vector (1 downto 0) ; std_logic_vector (3 downto 0) barrel_shifter

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); process begin test_a <= "0110";

test_amt

<=

"00";

wait for 200 ns;

test_amt

<=

"01";

wait for 200 ns;

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test_amt <= "10";

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wait for 200 ns;

test_amt wait; end process;

<=

"11";

end Behavioral;

User Constraints File # Leds NET "y<0>" LOC = "J14"; NET "y<1>" LOC = "J15"; NET "y<2>" LOC = "K15"; NET "y<3>" LOC = "K14";

# Switches NET "a<0>" LOC = "G18"; NET "a<1>" LOC = "H18"; NET "a<2>" LOC = "K18"; NET "a<3>" LOC = "K17"; NET "amt<0>" LOC = "L14";

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FPGA Lab

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6. Parameterized Register File Source code : Library ieee;

Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; Entity reg_file is generic ( B : integer integer := 2; -- number of bits := 2 -- number of address bits

W : );

port ( clk, reset wr_en w_addr, w_data r_data ); end reg_file; r_addr : : : : : in in in in std_logic; std_logic; std_logic_vector (W - 1 downto 0); std_logic_vector (B - 1 downto 0);

out std_logic_vector (B - 1 downto 0)

architecture type

arch of reg_file is is array (2**W-1 downto 0) of std_logic_vector (B - 1 downto 0);

reg_file_type

signal begin

array_reg :

reg_file_type;

process (clk, reset)

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begin if (reset = '1') then array_reg <= (others => (others => '0'));

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elsif (clk'event and clk = '1') then if (wr_en = '1') then array_reg(to_integer(unsigned(w_addr))) end if; end if; end process; -- read port r_data end arch; Testbench library IEEE; use entity end IEEE.STD_LOGIC_1164.ALL; reg_file_testbench is reg_file_testbench; <= array_reg(to_integer(unsigned(r_addr))); <= w_data;

architecture component generic (

Behavioral of reg_file_testbench is reg_file is

B W ); port (

: :

integer integer

:= :=

2; -- number of bits 2 -- number of address bits

clk, reset wr_en

: :

in in

std_logic; std_logic;

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w_addr, r_addr : w_data r_data ); end component; signal signal signal signal clk reset, test_wr_en : : : : std_logic std_logic := := '1'; '1'; : : in in

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std_logic_vector (W - 1 downto 0); std_logic_vector (B - 1 downto 0);

out std_logic_vector (B - 1 downto 0)

test_w2_addr, test_r2_addr test_w2_data, test_r2_data

std_logic_vector( 1 downto 0); std_logic_vector( 1 downto 0);

begin uut2 : reg_file port map( clk reset wr_en w_addr r_addr w_data r_data ); => => => => => => => clk, reset, test_wr_en, test_w2_addr, test_r2_addr, test_w2_data, test_r2_data

Clk Reset

<= <=

not clk after 20 ns; '1', '0' after 10 ns;

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process begin test_wr_en test_w2_addr test_w2_data <= '1';

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<= "00"; <= "00";

wait until rising_edge(clk); test_w2_addr test_w2_data <= <= "01"; "01";

wait until rising_edge(clk); test_w2_addr test_w2_data <= "10"; <= "10";

wait until rising_edge(clk); test_w2_addr test_w2_data <= <= "11"; "11";

wait until rising_edge(clk); test_wr_en test_r2_addr <= '0';

<= "00";

wait until rising_edge(clk);

test_r2_addr

<=

"01";

wait until rising_edge(clk);

test_r2_addr

<= "10";

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FPGA Lab
wait until rising_edge(clk); test_r2_addr wait; end process; end Behavioral; User Constraints File # clock pin for Nexys 2 Board NET "clk" LOC = "B8"; # Leds for Outputs NET "r_data<0>" LOC = "J14"; NET "r_data<1>" LOC = "J15"; <= "11";

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# Switches for Inputs NET "reset" LOC = "G18"; NET "wr_en" LOC = "H18"; NET "w_addr<0>" LOC = "K18"; NET "w_addr<1>" LOC = "K17"; NET "r_addr<0>" LOC = "L14"; NET "r_addr<1>" LOC = "L13"; NET "w_data<0>" LOC = "N17"; NET "w_data<1>" LOC = "R17";

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FPGA Lab

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7. Universal Shift register Source code : library ieee; use ieee.std_logic_1164.all; entity univ_shift_reg is generic ( N : integer := 5) ; port ( clk, reset ctrl d q ); End univ_shift_reg; : in : : : in in std_logic; std_logic_vector (1 downto 0 ) ; std_logic_vector ( N - 1 downto 0 ) ;

out std_logic_vector ( N - 1 downto 0)

architecture arch of univ_shift_reg is signal r_reg : std_logic_vector ( N - 1 downto 0) ;

signal r_next : std_logic_vector ( N - 1 downto 0 ) ; begin -- r e g i s t e r process (clk, reset) begin if (reset = '1') then r_reg <= ( others => '0' ); r_reg <= r_next;

elsif (clk'event and clk = '1') then end if;

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end process; -- next-state logic

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with ctrl select r_next <= d r_reg (2 downto 0) & d(0) d(N-1) & r_reg(N-1 downto 1) r_reg -- output q <= r_reg; when "00", -- no OP when "01", -- shift left : when "10", -- shift right; when others; -- load

end arch; Testbench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY univ_reg_testbench IS END univ_reg_testbench; ARCHITECTURE behavior OF univ_reg_testbench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT univ_shift_reg PORT( clk reset ctrl d q ); END COMPONENT; : IN : IN : IN : IN std_logic; std_logic; std_logic_vector(1 downto 0); std_logic_vector(7 downto 0);

: OUT std_logic_vector(7 downto 0)

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--Inputs Signal signal signal signal clk reset ctrl d : : std_logic := '0'; : std_logic := '0'; : std_logic_vector(1 downto 0) := (others => '0'); std_logic_vector(4 downto 0) := (others => '0');

--Outputs Signal q : std_logic_vector(4 downto 0);

-- Clock period definitions Constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT) Uut : univ_shift_reg PORT MAP ( Clk reset ctrl d q ); => => => => => clk, reset, ctrl, d, q

-- Clock process definitions clk_process : process

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begin clk <= '0';

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wait for clk_period/2; clk <= '1';

wait for clk_period/2; end process;

-- Stimulus process stim_proc begin -- hold reset state for 100 ns. reset <= '1'; : process

wait for 100 ns; -- insert stimulus here

reset ctrl d

<= <= <=

'0'; "11"; "00111";

wait until rising_edge(clk); ctrl <= "00";

wait until rising_edge(clk); wait until rising_edge(clk); ctrl <= "01";

wait until rising_edge(clk); ctrl <= "10";

wait until rising_edge(clk); wait;

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end process; END behavior;

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User Constraints File

# clock pin for Nexys 2 Board NET "clk" LOC = "B8"; # Leds NET "q<0>" LOC = "J14"; NET "q<1>" LOC = "J15"; NET "q<2>" LOC = "K15"; NET "q<3>" LOC = "K14"; NET "q<4>" LOC = "E17";

# Switches NET "reset" LOC = "G18"; NET "ctrl<0>" LOC = "H18"; NET "ctrl<1>" LOC = "K18"; NET "d<0>" LOC = "K17"; NET "d<1>" LOC = "L14"; NET "d<2>" LOC = "L13"; NET "d<3>" LOC = "N17"; NET "d<4>" LOC = "R17";

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FPGA Lab

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8. Universal binary counter Source code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity univ_bin_counter is

generic ( N : integer := 3 ); port ( clk, reset syn_clr, load, en, up d q max_tick, min_tick ); end univ_bin_counter; : in : in : in std_logic; std_logic; std_logic_vector ( N - 1 downto 0);

: out std_logic_vector( N - 1 downto 0); : out std_logic

architecture arch of univ_bin_counter is signal r_reg : unsigned ( N - 1 downto 0) ; unsigned ( N - 1 downto 0) ;

signal r_next : -- register begin

process (clk, reset) begin if (reset = '1') then r_reg <= ( others => '0' );

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elsif (clk'event and clk = '1') then r_reg end if; end process; <= r_next;

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--next - state logic r_next <= (others => '0' ) unsigned (d) r_reg + 1 r_reg - 1 r_reg; -- output logic max_tick min_tick q end arch; <= '1' <= '1' <= when when r_reg = (2**N - 1) else '0'; r_reg = 0 else '0'; when when when when syn_clr = '1' load = '1 ' en = '1' and up = '1' en = '1' and up = '0' else else else else

std_logic_vector(r_reg);

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Testbench library ieee; use ieee.std_logic_1164.all; entity bin_counter_tb is end bin_counter_tb;

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architecture arch of bin_counter_tb is

constant constant signal signal signal signal signal

THREE T clk, reset syn_clr, load, en, up

: : : : : min_tick : :

integer := 3 ; time := 20 ns; -- clk period std_logic; std_logic; std_logic_vector (THREE-1 downto 0); std_logic; std_logic_vector (THREE-1 downto 0);

d max_tick, q

component univ_bin_counter is

generic ( N : integer := 3 ); port ( clk, reset syn_clr, load, en, up d q max_tick, min_tick ); end component; : : : : : in in in out out std_logic; std_logic; std_logic_vector ( N - 1 downto 0); std_logic_vector( N - 1 downto 0); std_logic

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begin counter_unit : univ_bin_counter

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generic map ( N => THREE ) port map( clk reset syn_clr load en up d max_tick min_tick q => q ); -- clock -- 20 ns clock running forever process begin clk <= '0'; wait for T / 2 ; clk <= '1'; wait for T / 2 ; end process; -- reset asserted for T / 2 Reset <= '1', '0' after (T/2); -- other stimulus => => => => => => => => => clk, reset, syn_clr, load, en, up, d, max_tick, min_tick,

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process begin

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-- initial input syn_clr load up d <= <= <= <= '0'; '0'; '1'; -- count up

(others => '0');

wait until falling_edge(clk); wait until falling_edge(clk);

--test load load d <= <= '1'; "011";

wait until falling_edge(clk); load <= '0';

-- pause 2 clocks wait until falling_edge(clk); wait until falling_edge(clk); -- test syn_clear syn_clr <= '1'; -- c l e a r

wait until falling_edge(clk); syn_clr <= '0';

-- test up counter and pause En Up <= <= '1'; '1'; -- count 10 clocks -- count

for i in 1 to 10 loop

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end en loop; <= '0';

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wait until falling_edge(clk); wait until falling_edge(clk); en <= '1';

wait until falling_edge(clk); wait until falling_edge(clk); wait until falling_edge(clk); -- test down counter Up For <= i in '0'; 1 to 10 loop -- run 10 clocks

end loop; -- other wait conditions -- continue until wait until q=2

q = "010";

wait until falling_edge(clk); up <= '1';

-- continue until min_tick changes value Wait on min_tick; wait until falling_edge(clk); up <= '0';

wait for 4*T; -- wait for 12s en <= '0';

wait for 4*T; -- terminate simulation Assert false report "Simulation Completed"

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severity failure; end process; end arch;

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User Constraints File # clock pin for Nexys 2 Board NET "clk" LOC = "B8";

# Leds for Outputs NET "q<0>" LOC = "J14"; NET "q<1>" LOC = "J15"; NET "q<2>" LOC = "K15"; NET "min_tick" LOC = "F4"; NET "Max_tick" LOC = "R4";

# Switches for Inputs NET "reset" LOC = "G18"; NET "sync_clr" LOC = "H18"; NET "load" LOC = "K18"; NET "en" LOC = "K17"; NET "up" LOC = "L14"; NET "d<0>" LOC = "L13"; NET "d<1>" LOC = "N17"; NET "d<2>" LOC = "R17";

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9. Mod - m counter Source code : library ieee; use ieee.std_logic_1164.all; use ieee . numeric_std.all; entity mod_m_counter is generic ( N : integer := 4; -- number of bits -- mod 4

M : integer );

:= 10

port ( clk, reset max_tick q ); end mod_m_counter ; : : : in out out std_logic; std_logic; std_logic_vector (N-1 downto 0)

architecture arch of mod_m_counter is signal signal begin -- register process (clk, reset) begin if (reset='1') then r_reg r_next : unsigned ( N - 1 downto 0 ) ; : unsigned ( N - 1 downto 0 ) ;

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r_reg elsif (clk'event and r_reg end if; end process; --next - state r_next <= logic ( others => '0' ) when r_reg = (M - 1) else <= clk='1') then <= r_next; (others => '0');

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r_reg + 1;

-- output logic Q max_tick <= <= std_logic_vector(r_reg); '1' '0'; end arch; Testbench LIBRARY ieee; USE ieee.std_logic_1164.ALL; when r_reg = (M - 1) else

ENTITY mod_m_counter_testbench IS END mod_m_counter_testbench; ARCHITECTURE behavior OF mod_m_counter_testbench IS -- -- Component Declaration for the Unit Under Test (UUT) component mod_m_counter is generic ( N M ); port ( clk, reset : in std_logic; : : integer integer := 4; -- number of bits -- mod 4

:= 10

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max_tick q ); end component ; --Inputs Signal signal --Outputs Signal Signal max_tick q : std_logic; : std_logic_vector(3 downto 0); clk reset : std_logic := '0'; := '0'; : out std_logic; : out std_logic_vector (N-1 downto 0)

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: std_logic

-- Clock period definitions Constant clk_period : time := 10 ns;

BEGIN -- Instantiate the Unit Under Test (UUT) uut : mod_m_counter PORT MAP ( clk reset max_tick q ); -- Clock process definitions clk_process : process begin clk <= '1'; => clk, => reset, => max_tick, => q

wait for clk_period/2; clk <= '0';

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wait for clk_period/2; end process; -- Stimulus process stim_proc : process begin -- hold reset state for 100 ns. Reset <= '1';

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Wait for 100 ns; reset wait for -- insert stimulus here wait; end process; END; <= '0'; clk_period*10;

User Constraints File # clock pin for Nexys 2 Board NET "clk" LOC = "B8";

# Leds for Outputs NET "q<0>" LOC = "J14"; NET "q<1>" LOC = "J15"; NET "q<2>" LOC = "K15"; NET "q<3>" LOC = "K14";

# Switches for Inputs NET "reset" LOC = "G18";

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10. FIFO Buffer library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity fifo is generic( B : natural := 5; -- number of bits -- number of address bits

W : natural := 4 );

port ( clk, reset rd, wr w_data empty, full r_data ); end fifo; : : : : : in in in std_logic; std_logic; std_logic_vector( B-1 downto 0) ;

out std_logic; out std_logic_vector( B-1 downto 0)

architecture type signal signal signal signal signal

arch of fifo is

reg_file_type is array (2**W-1 downto 0) of std_logic_vector ( B - 1 downto 0); array_reg w_ptr_reg, w_ptr_next, w_ptr_succ r_ptr_reg, wr_en full_reg, empty_reg, full_next, empty_next r_ptr_next, r_ptr_succ : : : : : reg_file_type; std_logic_vector(W-1 downto 0); std_logic_vector(W-1 downto 0); std_logic; std_logic;

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signal wr_op :

M.Tech(I Year)
std_logic_vector (1 downto 0 );

begin -- register file process (clk, reset) begin if (reset = '1') then array_reg <= (others => (others => '0'));

elsif (clk'event and clk = '1') then if (wr_en = '1') then array_reg(to_integer(unsigned(w_ptr_reg))) end if; end if; end process; <= w_data;

-- read port r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));

--write enabled only when FIFO is not full wr_en <= wr and ( not full_reg);

================================================================================== --fifo control logic -================================================================================== --register for read and write pointers process (clk, reset) begin if(reset = '1') then w_ptr_reg <= ( others => '0');

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r_ptr_reg full_reg empty_reg elsif (clk'event and <= <= <= ( others => '0'); '0'; '1';

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clk = '1') then <= <= <= <= w_ptr_next; r_ptr_next; full_next; empty_next ;

w_ptr_reg r_ptr_reg full_reg empty_reg end if ; end process;

-- successive pointer values w_ptr_succ r_ptr_succ <= <= std_logic_vector(unsigned(w_ptr_reg)+1); std_logic_vector(unsigned(r_ptr_reg)+1);

-- next-state logic for read and write pointers wr_op <= wr & rd;

process (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg) begin w_ptr_next r_ptr_next full_next empty_next <= <= <= <= w_ptr_reg; r_ptr_reg; full_reg; empty_reg ;

case wr_op is when when "00" "01" => => -- no operation -- read if (empty_reg /= '1') then -- not empty

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r_ptr_next full_next <= <= r_ptr_succ; '0';

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if (r_ptr_succ = w_ptr_reg) then empty_next end if; end if; <= '1';

when

"10"

=>

-- write if (full_reg /= '1') then w_ptr_next empty_next <= <= -- not full w_ptr_succ; '0';

if (w_ptr_succ = r_ptr_reg) then full_next end if; end if; <= '1';

when others

=>

-- write / read; w_ptr_next r_ptr_next <= <= w_ptr_succ; r_ptr_succ;

end case; end process; -- output full empty end arch; <= <= full_reg; empty_reg;

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Test bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity fif_testbench is end fif_testbench; architecture Behavioral of fif_testbench is

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component fifo is generic( B : natural := 5; -- number of bits

W : natural := 4 -- number of address bits );

port ( clk, reset rd, wr w_data : in : in : in std_logic; std_logic; std_logic_vector( B-1 downto 0) ;

empty, full : out std_logic; r_data ); end component; : out std_logic_vector( B-1 downto 0)

signal signal begin uut

clk, reset, rd, wr, empty, full w_data, r_data

: :

std_logic; std_logic_vector( 4 downto 0);

: fifo port map( clk => clk,

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reset rd wr w_data empty full r_data ); => => => reset, rd, wr,

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=> w_data, => empty, => => full, r_data

Clk reset

<= '1', not clk after 20 ns; <= '1', '0' after 20 ns;

process begin wait for 100 ns; wr <= '1';

w_data <= "01011"; wait until rising_edge(clk);

w_data

<=

"01101";

wait until rising_edge(clk);

w_data

<=

"11010";

wait until rising_edge(clk);

w_data

<= "01010";

wait until rising_edge(clk);

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w_data

<=

"11001";

wait until rising_edge(clk); wr rd <= <= '0'; '1';

wait until rising_edge(clk); rd <= '1';

wait until rising_edge(clk); end process; end Behavioral;

User Constraints File

# clock pin for Nexys 2 Board NET "clk" LOC = "B8";

# Leds For Outputs NET "r_data<0>" LOC = "J14"; NET "r_data<1>" LOC = "J15"; NET "r_data<2>" LOC = "K15"; NET "r_data<3>" LOC = "K14"; NET "r_data<4>" LOC = "E17"; NET "empty" LOC = "F4"; NET "full" LOC = "R4";

# Switches For Inputs NET "reset" LOC = "G18";

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NET "rd" LOC = "H18"; NET "wr" LOC = "K18"; NET "w_data<0>" LOC = "K17"; NET "w_data<1>" LOC = "L14"; NET "w_data<2>" LOC = "L13"; NET "w_data<3>" LOC = "N17"; NET "w_data<4>" LOC = "R17";

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Appendix A

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Providing 1 Hz frequency signal to sequential designs

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All the sequential designs implemented in this lab are working at 50MHz frequency, because Nexys2 board consists of 50MHz clock signal source only. The outputs of these designs cant be observable with normal eyes when implemented on nexys2 board. So in order to observe these circuits output clearly, a 1Hz frequency clock signal is required. This can be done by placing a 50MHz to 1Hz frequency converter. In all designs, give clock source in nexys2 board to clk_50Hz in the fallowing code and the output signal clk_1Hz to clk signal declared in all designs. Simply instantiate this frequency converter component in every sequential design for clock signal and do corresponding port mapping. The source code for this converter is as fallows

library ieee; use ieee.std_logic_1164.all; use ieee . numeric_std.all; entity freqconv50_1Hz is generic ( N : integer := 26; -- number of bits -- mod 4

M : integer );

:= 50000000

port ( clk_50Hz, reset clk_1Hz ); end freqconv50_1Hz ; : : in out std_logic; std_logic;

architecture arch of freqconv50_1Hz is signal signal r_reg r_next : unsigned ( N - 1 downto 0 ) ; : unsigned ( N - 1 downto 0 ) ; Page 54

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begin -- register process (clk, reset) begin if (reset='1') then r_reg elsif (clk'event and r_reg end if; end process; --next - state r_next <= logic ( others => '0' ) when r_reg = (M - 1) else <= clk='1') then <= r_next; (others => '0');

M.Tech(I Year)

r_reg + 1;

-- output logic Q max_tick <= <= std_logic_vector(r_reg); '1' '0'; end arch; when r_reg = (M - 1) else

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Appendix - B

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