L3: Introduction to L3: Introduction to VeriIog VeriIog

(CombinationaI Logic) (CombinationaI Logic)

Courtesy of Rex Min. Used with permission.
VeriIog References:
Samir PaInitkar, VeriIog HDL, Pearson Education (2nd edition).
DonaId Thomas, PhiIip Moorby, The VeriIog Hardware Description Language, Fifth
Edition, KIuwer Academic PubIishers.
J. Bhasker, VeriIog HDL Synthesis (A PracticaI Primer), Star GaIaxy PubIishing
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 1
Synthesis and Synthesis and HDLs HDLs
! Hardware description Ianguage (HDL) is a convenient, device-
independent representation of digitaI Iogic
VeriIog
input a,b;
output sum;
assign sum <= {1b'0, a} + {1b'0, b};
FPGA PAL
ASIC
(Custom ICs)
NetIist
g1 "and" n1 n2 n5
g2 "and" n3 n4 n6
g3 "or" n5 n6 n7
! HDL description is compiIed
into a netIist
! Synthesis optimizes the Iogic
! Mapping targets a specific
hardware pIatform
Compilation and
Synthesis
Mapping
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 2
VeriIog VeriIog: The ModuIe : The ModuIe
! VeriIog designs consist of
interconnected moduIes.
! A moduIe can be an eIement or
coIIection of Iower IeveI design bIocks.
! A simpIe moduIe with combinationaI
Iogic might Iook Iike this:
!"#$%$&'($! )$*$&'($! +$
1
0
sel
out
outbar
a
b
2-to-1 multiplexer with inverted output
module mux_2_to_1(a, b, out,
DecIare and name a moduIe; Iist its
outbar, sel);
ports. Don't forget that semicoIon.
// This is 2:1 multiplexor
input a, b, sel;
output out, outbar;
Comment starts with //
VeriIog skips from // to end of the Iine
Specify each port as input, output,
or inout
Express the moduIe's behavior.
assign out = sel ? a : b;
Each statement executes in
assign outbar = ~out; paraIIeI; order does not matter.
endmodule ConcIude the moduIe code.
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 5
Continuous (DatafIow) Assignment Continuous (DatafIow) Assignment
module mux_2_to_1(a, b, out,
outbar, sel);
a
input a, b, sel;
1
0
out
output out, outbar;
b
outbar
assign out = sel ? a : b;
assign outbar = ~out;
sel
endmodule
! Continuous assignments use the assign keyword
! A simpIe and naturaI way to represent combinationaI Iogic
! ConceptuaIIy, the right-hand expression is continuousIy evaIuated as a function of
arbitrariIy-changing inputs.just Iike datafIow
! The target of a continuous assignment is a net driven by combinationaI Iogic
! Left side of the assignment must be a scaIar or vector net or a concatenation of scaIar
and vector nets. It can't be a scaIar or vector register (discussed later). Right side can be
register or nets
! DatafIow operators are fairIy Iow-IeveI:
" ConditionaI assignment: (conditionaI_expression) ? (vaIue-if-true) : (vaIue-if-faIse);
" BooIean Iogic: ~, &, |
" Arithmetic: +, -, *
! Nested conditionaI operator (4:1 mux)
" assign out = s1 ? (s0 ? i3 : i2) : (s0? i1 : i0);
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 6
Gate LeveI Description Gate LeveI Description
module muxgate (a, b, out,
outbar, sel);
input a, b, sel;
output out, outbar;
wire out1, out2, selb;
and a1 (out1, a, sel);
not i1 (selb, sel);
out
sel
a
b
out1
out2
selb
outbar
and a2 (out2, b , selb);
or o1 (out, out1, out2);
assign outbar = ~out;
endmodule
! VeriIog supports basic Iogic gates as primitives
" and, nand, or, nor, xor, xnor, not, buf
" can be extended to muItipIe inputs: e.g., nand nand3in (out, in1, in2,in3);
" bufif1 and bufif0 are tri-state buffers
! Net represents connections between hardware eIements. Nets are
decIared with the keyword wire.
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 8
ProceduraI Assignment with ProceduraI Assignment with always always
! ProceduraI assignment aIIows an aIternative, often higher-IeveI, behavioraI
description of combinationaI Iogic
! Two structured procedure statements: initial and always
! Supports richer, C-Iike controI structures such as if, for, while,case
module mux_2_to_1(a, b, out,
outbar, sel);
ExactIy the same as before.
input a, b, sel;
output out, outbar;
Anything assigned in an always
reg out, outbar;
bIock must also be decIared as
type reg (next slide)
always @ (a or b or sel)
begin
if (sel) out = a;
else out = b;
outbar = ~out;
end
endmodule
ConceptuaIIy, the always bIock
runs once whenever a signaI in the
sensitivity Iist changes vaIue
Statements within the always
bIock are executed sequentiaIIy.
Order matters!
Surround muItipIe statements in a
singIe always bIock with begin/end.
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 9
VeriIog VeriIog Registers Registers
! In digitaI design, registers represent memory eIements (we
wiII study these in the next few Iectures)
! DigitaI registers need a cIock to operate and update their
state on certain phase or edge
! Registers in VeriIog shouId not be confused with hardware
registers
! In VeriIog, the term register (reg) simpIy means a variabIe
that can hoId a vaIue
! VeriIog registers don't need a cIock and don't need to be
driven Iike a net. VaIues of registers can be changed
anytime in a simuIation by assuming a new vaIue to the
register
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 10
Mix Mix- -and and- -Match Assignments Match Assignments
! ProceduraI and continuous assignments can (and often do) co-exist
within a moduIe
! ProceduraI assignments update the vaIue of reg. The vaIue wiII remain
unchanged tiII another proceduraI assignment updates the variabIe.
This is the main difference with continuous assignments in which the
right hand expression is constantIy pIaced on the Ieft-side
module mux_2_to_1(a, b, out,
outbar, sel);
input a, b, sel;
output out, outbar;
reg out;
always @ (a or b or sel)
begin
if (sel) out = a;
else out = b;
end
assign outbar = ~out;
procedural
description
continuous
description
1
0
sel
out
a
b
outbar
endmodule
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 11
The The case case Statement Statement
! case and if may be used interchangeabIy to impIement
conditionaI execution within always bIocks
! case is easier to read than a Iong string of if...else statements
module mux_2_to_1(a, b, out,
outbar, sel);
input a, b, sel;
output out, outbar;
reg out;
module mux_2_to_1(a, b, out,
outbar, sel);
input a, b, sel;
output out, outbar;
reg out;
always @ (a or b or sel) always @ (a or b or sel)
begin begin
if (sel) out = a; case (sel)
else out = b; 1b1: out = a;
end 1b0: out = b;
endcase
assign outbar = ~out; end
endmodule assign outbar = ~out;
endmodule
Note: Number specification notation: <size>'<base><number>
(4'b1010 if a 4-bit binary value, 16'h6cda is a 16 bit hex number, and 8'd40 is an 8-bit decimal value)
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 12
The Power of The Power of VeriIog VeriIog: : n n- -bit SignaIs bit SignaIs
! MuIti-bit signaIs and buses are easy in VeriIog.
! 2-to-1 muItipIexer with 8-bit operands:
module mux_2_to_1(a, b, out,
outbar, sel);
input[7:0] a, b;
1
0
8
input sel;
output[7:0] out, outbar;
a
8
reg[7:0] out; out
always @ (a or b or sel) b
outbar
begin
8
8
if (sel) out = a;
sel
else out = b;
end
assign outbar = ~out;
endmodule
assign {b[7:0],b[15:8]} = {a[15:8],a[7:0]};
effects a byte swap
Concatenate signaIs using the { } operator
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 13
The Power of The Power of VeriIog VeriIog: Integer Arithmetic : Integer Arithmetic
! VeriIog's buiIt-in arithmetic makes a 32-bit adder easy:
module add32(a, b, sum);
input[31:0] a,b;
output[31:0] sum;
assign sum = a + b;
endmodule
! A 32-bit adder with carry-in and carry-out:
module add32_carry(a, b, cin, sum, cout);
input[31:0] a,b;
input cin;
output[31:0] sum;
output cout;
assign {cout, sum} = a + b + cin;
endmodule
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 14
Dangers of Dangers of VeriIog VeriIog: IncompIete Specification : IncompIete Specification
GoaI: Proposed VeriIog Code:
00
sel
out
01
10
a
b
c
2
3-to-1 MUX
('11' input is a don't-care)
module maybe_mux_3to1(a, b, c,
sel, out);
input [1:0] sel;
input a,b,c;
output out;
reg out;
always @(a or b or c or sel)
begin
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
endcase
end
endmodule
Is this a 3-to-1 multiplexer?
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 15
IncompIete Specification Infers Latches IncompIete Specification Infers Latches
module maybe_mux_3to1(a, b, c,
Synthesized ResuIt:
sel, out);
input [1:0] sel;
input a,b,c;
output out;
a
reg out;
b
00
sel
01
10
2
D Q
G
sel[1]
sel[0]
out
always @(a or b or c or sel)
begin
c
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
endcase
end
endmodule
if out is not assigned
during any pass through
the aIways bIock, then the
previous vaIue must be
retained!
! Latch memory "Iatches"
oId data when G=0 (we
wiII discuss Iatches Iater)
! In practice, we aImost
never intend this
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 16
Avoiding IncompIete Specification Avoiding IncompIete Specification
! Precede aII conditionaIs
with a defauIt assignment
for aII signaIs assigned
within them.
always @(a or b or c or sel)
begin
out = 1bx;
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
endcase
end
endmodule
always @(a or b or c or sel)
begin
! .or, fuIIy specify aII
case (sel)
branches of conditionaIs and
2'b00: out = a;
assign aII signaIs from aII
2'b01: out = b;
2'b10: out = c; branches
default: out = 1bx;
" For each if, incIude else
endcase
end
" For each case, incIude default
endmodule
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 17
Dangers of Dangers of VeriIog VeriIog: Priority Logic : Priority Logic
GoaI: Proposed VeriIog Code:

0
4-to-2 Binary Encoder
E
1
E
0
1
0
0
1
0
0

0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
all others
E
1
E
0
0 0
0 1
1 0
1 1
X X
module binary_encoder(i, e);
input [3:0] i;
output [1:0] e;
reg e;
always @(i)
begin
if (i[0]) e = 2b00;
else if (i[1]) e = 2b01;
else if (i[2]) e = 2b10;
else if (i[3]) e = 2b11;
else e = 2bxx;
end
endmodule
What is the resulting circuit?
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 18
Priority Logic Priority Logic
Intent: if more than one input is
1, the resuIt is a don't-care.

0
E
1
E
0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
all others X X
Code: if i[0] is 1, the resuIt is 00
regardIess of the other inputs.
i[0] takes the highest priority.
if (i[0]) e = 2b00;
else if (i[1]) e = 2b01;
else if (i[2]) e = 2b10;
else if (i[3]) e = 2b11;
else e = 2bxx;
end
1
i[0]
0
2'b00
1
i[1]
0
2'b01
1
i[2]
0
2'b10
1
i[3]
0
2'b11
2'bxx
e[1:0]
Inferred
Result:
! if-else and case statements are interpreted very IiteraIIy!
Beware of unintended priority Iogic.
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 19
Avoiding (Unintended) Priority Logic Avoiding (Unintended) Priority Logic
! Make sure that if-else and case statements are parallel
" If mutuaIIy excIusive conditions are chosen for each branch...
" ...then synthesis tooI can generate a simpIer circuit that evaIuates
the branches in paraIIeI
ParaIIeI Code: Minimized ResuIt:
module binary_encoder(i, e);
input [3:0] i;
output [1:0] e;
reg e;
always @(i)
begin
if (i == 4b0001) e = 2b00;
else if (i == 4b0010) e = 2b01;
else if (i == 4b0100) e = 2b10;
else if (i == 4b1000) e = 2b11;
else e = 2bxx;
I
3
I
1
I
0
E
0
E
1
end
endmodule
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 20
Interconnecting ModuIes Interconnecting ModuIes
! ModuIarity is essentiaI to the success of Iarge designs
! A VeriIog module may contain submoduIes that are "wired together"
! High-IeveI primitives enabIe direct synthesis of behavioraI descriptions (functions such
as additions, subtractions, shifts (<< and >>), etc.
ExampIe: A 32-bit ALU Function TabIe
A[31:0] B[31:0]
+ - *
0 1 0 1
32'd1 32'd1
00 01 10
F[0]
F[2:1]
F2 F1 F0
0 0 0
0 0 1
0 1 0
F[2:0]
0 1 1
1 0 X
Function
A + B
A + 1
A - B
A - 1
A * B
R[31:0]
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 21
ModuIe Definitions ModuIe Definitions
2-to-1 MUX 3-to-1 MUX
module mux32two(i0,i1,sel,out);
module mux32three(i0,i1,i2,sel,out);
input [31:0] i0,i1,i2;
input [31:0] i0,i1;
input [1:0] sel;
input sel;
output [31:0] out;
output [31:0] out;
reg [31:0] out;
assign out = sel ? i1 : i0;
always @ (i0 or i1 or i2 or sel)
begin
endmodule
case (sel)
2b00: out = i0;
2b01: out = i1;
2b10: out = i2;
default: out = 32bx;
endcase
end
endmodule
32-bit Adder 32-bit Subtracter 16-bit MuItipIier
module mul16(i0,i1,prod);
module add32(i0,i1,sum); module sub32(i0,i1,diff);
input [15:0] i0,i1;
input [31:0] i0,i1; input [31:0] i0,i1;
output [31:0] prod;
output [31:0] sum; output [31:0] diff;
// this is a magnitude multiplier
assign sum = i0 + i1; assign diff = i0 - i1;
// signed arithmetic later
assign prod = i0 * i1;
endmodule endmodule
endmodule
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 22
Top Top- -LeveI ALU DecIaration LeveI ALU DecIaration
A[31:0] B[31:0]
! Given submoduIes:
alu
module mux32two(i0,i1,sel,out);
module mux32three(i0,i1,i2,sel,out);
module add32(i0,i1,sum);
module sub32(i0,i1,diff);
module mul16(i0,i1,prod);
+ - *
0 1 0 1
32'd1 32'd1
00 01 10
F[0]
F[2:1]
F[2:0]
! DecIaration of the ALU ModuIe:
module alu(a, b, f, r);
input [31:0] a, b;
input [2:0] f;
output [31:0] r;
R[31:0]
wire [31:0] addmux_out, submux_out;
wire [31:0] add_out, sub_out, mul_out;
mux32two adder_mux(b, 32'd1, f[0], addmux_out);
mux32two sub_mux(b, 32'd1, f[0], submux_out);
add32 our_adder(a, addmux_out, add_out);
sub32 our_subtracter(a, submux_out, sub_out);
mul16 our_multiplier(a[15:0], b[15:0], mul_out);
mux32three output_mux(add_out, sub_out, mul_out, f[2:1], r);
endmodule
moduIe
names
(unique)
instance
names
corresponding
wires/regs in
moduIe alu
intermediate output nodes
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 23
SimuIation SimuIation
addition subtraction muItipIier
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 24
More on ModuIe Interconnection More on ModuIe Interconnection
! ExpIicit port naming aIIows port mappings in arbitrary
order: better scaIing for Iarge, evoIving designs
Given Submodule Declaration:
module mux32three(i0,i1,i2,sel,out);
Module nstantiation with Ordered Ports:
mux32three output_mux(add_out, sub_out, mul_out, f[2:1], r);
Module nstantiation with Named Ports:
mux32three output_mux(.sel(f[2:1]), .out(r), .i0(add_out),
.i1(sub_out), .i2(mul_out));
submoduIe's
port name
corresponding
wire/reg in
outer moduIe
! BuiIt-in VeriIog gate primitives may be instantiated as weII
" Instantiations may omit instance name and must be ordered:
buf(out1,out2,...,outN, in); and(in1,in2,...inN,out);
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 25
UsefuI BooIean Operators UsefuI BooIean Operators
! Bitwise operators perform bit-sIiced operations on vectors
" ~(4'b0101) = {~0,~1,~0,~1} = 4'b1010
" 4'b0101 & 4'b0011 = 4'b0001
! LogicaI operators return one-bit (true/faIse) resuIts
" !(4'b0101) = ~1 = 1'b0
! Reduction operators act on each bit of a singIe input vector
" &(4'b0101) = 0 & 1 & 0 & 1 = 1'b0
! Comparison operators perform a BooIean test on two arguments
Bitwise LogicaI Reduction Comparison
~a NOT
a & b AND
a | b OR
a ^ b XOR
a ~^ b XNOR
!a NOT
a && b AND
a || b OR
&a AND
~& NAND
| OR
~| NOR
^ XOR
a < b
a > b
a <= b
Relational
a >= b
a == b
a != b
[in]equality
returns x when x
or z in bits. Else
returns 0 or 1
a === b case
a !== b [in]equality
returns 0 or 1
based on bit by bit
comparison
Note distinction between ~a and !a
L3: 6.111 Spring 2004 Introductory DigitaI Systems Laboratory 26
Combinational Logic Review Combinational Logic Review
Combinational
Circuit
in
0
in
1
in
N-1
in
0
in
1
in
M-1
Combinational logic circuits are memoryless
No feedback in combinational logic circuits
Output assumes the function implemented by the
logic network, assuming that the switching
transients have settled
Outputs can have multiple logical transitions
before settling to the correct value
L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2
A Sequential System A Sequential System
Sequential circuits have memory (i.e., remember the past)
The current state is held in memory and the next state is
computed based the current state and the current inputs
In a synchronous systems, the clock signal orchestrates the
sequence of events
L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3
A Simple Example A Simple Example
Adding N inputs (N-1 Adders)
in
0
in
1
in
2
in
N-1
Using a sequential (serial) approach
in
D Q
reset
clk
Current_Sum
L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4
L5: 6.111 Spring 2004 4 Introductory Digital Systems Laboratory
The Sequential The Sequential always always Block Block
Edge-triggered circuits are described using a sequential
always block
Combinational Sequential
module combinational(a, b, sel,
out);
input a, b;
input sel;
output out;
reg out;
always @ (a or b or sel)
begin
if (sel) out = a;
else out = b;
end
endmodule
module sequential(a, b, sel,
clk, out);
input a, b;
input sel, clk;
output out;
reg out;
always @ (posedge clk)
begin
if (sel) out <= a;
else out <= b;
end
endmodule
1
0
sel
1
0
sel
out
a
D Q
a
out
b b
clk
L5: 6.111 Spring 2004 5 Introductory Digital Systems Laboratory
Importance of the Sensitivity List Importance of the Sensitivity List
The use of posedge and negedge makes an always block sequential
(edge-triggered)
Unlike a combinational always block, the sensitivity list does
determine behavior for synthesis!
D Flip-flop with synchronous clear D Flip-flop with asynchronous clear
module dff_sync_clear(d, clearb,
clock, q);
input d, clearb, clock;
output q;
reg q;
always @ (posedge clock)
begin
if (!clearb) q <= 1'b0;
else q <= d;
end
endmodule
module dff_async_clear(d, clearb, clock, q);
input d, clearb, clock;
output q;
reg q;
always @ (negedge clearb or posedge clock)
begin
if (!clearb) q <= 1b0;
else q <= d;
end
endmodule
always block entered only at
each positive clock edge
always block entered immediately
when (active-low) clearb is asserted
Note: The following is incorrect syntax: always @ (clear or negedge clock)
If one signal in the sensitivity list uses posedge/negedge, then all signals must.
Assign any signal or variable from only one always block, Be
wary of race conditions: always blocks execute in parallel
L5: 6.111 Spring 2004 6 Introductory Digital Systems Laboratory
Simulation Simulation
DFF with Synchronous Clear
t
c-q
Clear on Clock Edge
DFF with Asynchronous Clear
Clear happens on falling edge of clearb
L5: 6.111 Spring 2004 7 Introductory Digital Systems Laboratory
Blocking vs. Blocking vs. Nonblocking Nonblocking Assignments Assignments
1. Evaluate a | b but defer assignment of x
2. Evaluate a^b^c but defer assignment of y
3. Evaluate b&(~c) but defer assignment of z
1. Evaluate a | b, assign result to x
2. Evaluate a^b^c, assign result to y
3. Evaluate b&(~c), assign result to z
always @ (a or b or c)
begin
x = a | b;
y = a ^ b ^ c;
z = b & ~c;
end
always @ (a or b or c)
begin
x <= a | b;
y <= a ^ b ^ c;
z <= b & ~c;
end
Verilog supports two types of assignments within always blocks, with
subtly different behaviors.
Blocking assignment: evaluation and assignment are immediate
Nonblocking assignment: all assignments deferred until all right-hand
sides have been evaluated (end of simulation timestep)
Sometimes, as above, both produce the same result. Sometimes, not!
4. Assign x, y, and z with their new values
L5: 6.111 Spring 2004 8 Introductory Digital Systems Laboratory
Assignment Styles for Sequential Logic Assignment Styles for Sequential Logic
D Q D Q D Q in out
q1 q2
clk
Flip-Flop Based
Digital Delay
Line
Will nonblocking and blocking assignments both produce
the desired result?
module nonblocking(in, clk, out);
input in, clk;
output out;
reg q1, q2, out;
always @ (posedge clk)
begin
q1 <= in;
q2 <= q1;
out <= q2;
end
endmodule
module blocking(in, clk, out);
input in, clk;
output out;
reg q1, q2, out;
always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end
endmodule
L5: 6.111 Spring 2004 9 Introductory Digital Systems Laboratory
Use Use Nonblocking Nonblocking for Sequential Logic for Sequential Logic
always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end
always @ (posedge clk)
begin
q1 <= in;
q2 <= q1;
out <= q2;
end
At each rising clock edge, q1 = in.
After that, q2 = q1 = in.
After that, out = q2 = q1 = in.
Therefore out = in.
At each rising clock edge, q1, q2, and out
simultaneously receive the old values of in,
q1, and q2.
D Q D Q D Q
D Q
q1 q2
q1 q2
in in out out
clk clk
Blocking assignments do not reflect the intrinsic behavior of multi-stage
sequential logic
Guideline: use nonblocking assignments for sequential
always blocks
L5: 6.111 Spring 2004 10 Introductory Digital Systems Laboratory
Simulation Simulation
Non-blocking Simulation
Blocking Simulation
L5: 6.111 Spring 2004 11 Introductory Digital Systems Laboratory
Use Blocking for Combinational Logic Use Blocking for Combinational Logic
x <= a & b;
Assignment completion
(Given) Initial Condition
a changes;
always block triggered
a b c x y Deferred
1 1 0 1 1
0 1 0 1 1
0 1 0 1 1 x<=0
0 1 0 1 1 x<=0, y<=1
0 1 0 0 1
y <= x | c;
Nonblocking Behavior
x = a & b;
(Given) Initial Condition
a changes;
always block triggered
y = x | c;
Blocking Behavior a b c x y
1 1 0 1 1
0 1 0 1 1
0 1 0 0 1
0 1 0 0 0
module blocking(a,b,c,x,y);
input a,b,c;
output x,y;
reg x,y;
always @ (a or b or c)
begin
x = a & b;
y = x | c;
end
endmodule
a
b
c
x
y
module nonblocking(a,b,c,x,y);
input a,b,c;
output x,y;
reg x,y;
always @ (a or b or c)
begin
x <= a & b;
y <= x | c;
end
endmodule
Nonblocking and blocking assignments will synthesize correctly. Will both
styles simulate correctly?
Nonblocking assignments do not reflect the intrinsic behavior of multi-stage
combinational logic
While nonblocking assignments can be hacked to simulate correctly (expand
the sensitivity list), its not elegant
Guideline: use blocking assignments for combinational always blocks
L5: 6.111 Spring 2004 12 Introductory Digital Systems Laboratory
The Asynchronous Ripple Counter The Asynchronous Ripple Counter
Clock
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Count[0]
Count [3:0]
A simple counter architecture
uses only registers
(e.g., 74HC393 uses T-register and
negative edge-clocking)
Toggle rate fastest for the LSB
but ripple architecture leads to
large skew between outputs
Clock
Count [3]
Count [2]
Count [1]
Count [0]
Skew
Count[1] Count[2] Count[3]
D register set up to
always toggle: i.e., T
Register with T=1
L5: 6.111 Spring 2004 13 Introductory Digital Systems Laboratory
The Ripple Counter in The Ripple Counter in Verilog Verilog
module dreg_async_reset (clk, clear, d, q, qbar);
input d, clk, clear;
output q, qbar;
reg q;
always @ (posedge clk or negedge clear)
begin
if (!clear)
q <= 1'b0;
else q <= d;
end
assign qbar = ~q;
endmodule
Clock
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Count[0]
Count [3:0]
Count[1] Count[2] Count[3]
Single D Register with Asynchronous Clear:
Structural Description of Four-bit Ripple Counter:
Countbar[0] Countbar[1] Countbar[2]
Countbar[3]
module ripple_counter (clk, count, clear);
input clk, clear;
output [3:0] count;
wire [3:0] count, countbar;
dreg_async_reset bit0(.clk(clk), .clear(clear), .d(countbar[0]),
.q(count[0]), .qbar(countbar[0]));
dreg_async_reset bit1(.clk(countbar[0]), .clear(clear), .d(countbar[1]),
.q(count[1]), .qbar(countbar[1]));
dreg_async_reset bit2(.clk(countbar[1]), .clear(clear), .d(countbar[2]),
.q(count[2]), .qbar(countbar[2]));
dreg_async_reset bit3(.clk(countbar[2]), .clear(clear), .d(countbar[3]),
.q(count[3]), .qbar(countbar[3]));
endmodule
L5: 6.111 Spring 2004 14 Introductory Digital Systems Laboratory
Simulation of Ripple Effect Simulation of Ripple Effect