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Semiconductor Division
RC2211
FSK Demodulator/Tone Decoder
Features
Wide frequency range 0.01 Hz to 300 kHz Wide supply voltage range 4.5V to 20V DTL/TTL/ECL logic compatibility FSK demodulation with carrier-detector Wide dynamic range 2 mV to 3 VRMS Adjustable tracking range 1% to 80% Excellent temperature stability 20 ppm/C typical
Applications
FSK demodulation Data synchronization Tone decoding FM detection Carrier detection
Description
The RC2211 is a monolithic phase-locked loop (PLL) system especially designed for data communications. It is particularly well-suited for FSK modem applications, and operates over a wide frequency range of 0.01 Hz to 300 kHz. It can accommodate analog signals between 2 mV and 3V, and can interface with conventional DTL, TTL and ECL logic families. The circuit consists of a basic PLL for tracking an input signal frequency within the passband, a quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation. External components are used to independently set carrier frequency, bandwidth and output delay.
Block Diagram
Loop Filter f-Detector FSK Comparator VCO f Preamp Lock Detector Outputs Lock Detector Filter Lock Detector Comparator
65-2211-01
f FSK Input
f-Detector
Rev. 1.0.1
PRODUCT SPECIFICATION
RC2211
RB 510K (11) C1 Input Preamp (2) VCO 0.1 F Input Signal Quad f-Detector (3) RD 100K to 470K Lock Detector Comparator f (14) C0 (13) R0 0.1 F f (12) (10) Internal Reference RF 100K (8)
RL
Loop f-Detector
R1
CF
FSK Comparator
FSK Output
CD
65-2211-02
RC2211
PRODUCT SPECIFICATION
2.
3.
4.
5.
FLL
F1
F0
F2
FLH
65-2211-03
6.
7.
Loop Phase Detector Conversion Gain, Kf (Kf is the differential DC voltage across pins 10 and 11, per unit of phase error at phase-detector input): ( 2) ( VR) kf ( in volts per radian ) = --------------------------p
VCO Conversion Gain, K0 is the amount of change in VCO frequency per unit of DC voltage change at pin 11: 1 K0 ( in Hertz per volt ) = -------------------C0 R1 VR
9.
Total Loop Gain, KT: KT (in radians per second per volt)= 2 pKfK0 = 4 -----------C0 R1
Design Equations
See Figure 1 for Denitions of Components. 1. VCO Center Frequency, F0: 1 F 0 ( Hz ) = -----------R0 C0
PRODUCT SPECIFICATION
RC2211
Pin Assignments
+VS Input Lock Detector Filter GND Q Q FSK Data Output 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Timing Capacitor Timing Capacitor Timing Resistor Loop f-Detector Reference Voltage Output Reference Bypass FSK Comparator Input
65-2211-04
Thermal Characteristics
Parameter Therm. Res qJC Therm. Res. qJA For TA > 50C Derate at 14 Lead Plastic DIP 160C/W 6.5 mW/C 14 Lead Ceramic DIP 60C/W 120C/W 8.33 mW/C
RC2211
PRODUCT SPECIFICATION
Electrical Characteristics
(Test Conditions +VS = +12V, TA +25C, R0 = 30 kW, C0 = 0.033 mF. See Figure 1 for component designations.) RV/RM2211 Parameters General Supply Voltage2 Supply Current Oscillator Frequency Accuracy Frequency Stability
1
RC2211 Min 4.5 5.0 1.0 20 0.05 0.2 300 Typ Max 20 11 Units V mA % ppm/C %/V %/V kHz Hz
Test Conditlons
Min 4.5
Typ
Max 20
R0 10 kW Deviation from f0 = 1/R0C0 R1 = +VS = 12 1V +VS = 5 0.5V R0 = 8.2 kW, C0 = 400 pF R0 = 2 MW, C0 = 50 mF 100
Temperature Coefficient Power Supply Rejection Upper Frequency Limit Lowest Practical Operating Frequency1 Timing Resistor, R0 Operating Range Recommended Range Loop Phase Detector Peak Output Current Output Offset Current Output Impedance Maximum Swing Quadrature Phase Detector Peak Output Current3 Output Impedance Maximum Swing Input Preamp Input Impedance Input Signal Voltage Required to Cause Limiting3 Voltage Comparator Input Impedance Input Bias Current Voltage Gain1 Output Voltage Low Output Leakage Current Internal Reference Voltage Level Output Impedance
0.01
0.01
2000 100
5.0 15
2000 100
kW kW mA mA MW V mA MW VP-P kW mVRMS
4.0 100
Measured at pin 2
20 2.0 10
2.0
MW nA dB mV mA V W
Notes: 1. Guaranteed by design. 2. Individual applications may need special circuitry to function at <12V. 3. Sample tested.
PRODUCT SPECIFICATION
RC2211
Applications
FSK Decoding
Figure 2 shows the basic circuit connection for FSK decoding. With reference to Figures 1 and 2, the functions of external components are dened as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth, and C1 sets the loop lter time constant and the loop damping factor. CF and RF form a one pole post-detection lter for the FSK data output. The resistor RB (510 kW) from pin 7 to pin 8 introduces positive feedback across FSK comparator to facilitate rapid transition between output logic states. Recommended component values for some of the most commonly used FSK bauds are given in Table 1.
+VS 0.1 F C0 FSK Input 0.1 F 1 2 3 RL 5.1K 4 5 6 7 14 13 12 R0 R1 C1 RF 100K
65-2211-05
1.
2.
Choose a value of timing resistor R0 to be in the range of 10 kW to 100 kW. This choice is arbitrary. The recommended value is R0 = 20 kW. The nal value of R0 ios normally netuned with the series potentiometer, RX. Calculate value of C0 from Design Equation No. 1 or from Typical Performance Characteristics: C0 = 1/R0F0
3.
4.
5.
VCO Fine Tune
Calculate C1 to set loop damping. (See Design Equation No. 4) Normally, z 1/2 is recommended Then: C1 = C0/4 for z = 1/2
RC2211
11 0.1 F 9 8
RX 5K
10
6.
Calculate Data Filter Capacitance, CF: For RF = 100 kW, RB = 510 kW, the recommended value of CF is: 3 C F ( in mF ) = -----------------------Baud Rate
RB 510K
CF
Table 1. Recommended Component Values for Commonly Used FSK Bands (see Circuit of Figure 2)
FSK Band 300 Baud F1 = 1070 Hz F2 = 1270 Hz 300 Baud F1 = 2025 Hz F2 = 2225 Hz 1200 Baud F1 = 1200 Hz F2 = 2200 Hz Component Values C0 = 0.039 mF, CF = 0.005 mF C1 = 0.01 mF, R0 = 18 kW R1 = 100 kW C0 = 0.022 mF, CF = 0.005 mF C1 = 0.0047 mF, R0 = 18 kW R1 = 200 kW C0 = 0.027 mF, CF = 0.0022 mF C1 = 0.01 mF, R0 = 18 kW R1 = 30 kW
Note: All calculated component values except RO can be rounded off to the nearest standard value, and R0 can be varied to fine-tune center frequency through a series potentiometer, RX (see Figure 2).
Design Example
75 Baud FSK demodulator with mark space frequencies of 1110/1170 Hz: Step 1: Calculate F0: F0=(1110+1170)(1/2)= 1140Hz Step 2: Choose R0 = 20 kW (18 kW xed resistor in series with 5 kW potentiometer) Step 3: Calculate C0 from VCO Frequency vs. Timing Capacitor: C9 = 0.044mF Step 4: Calculate R1: R1 = R0 (1140/60) = 380 kW Step 5: Calculate C1: C1 = C0/4 = 0.011 mF
Design Instructions
The circuit of Figure 2 can be tailored for any FSK decoding application by the choice of ve key circuit components: R0, R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, F1 and F2, these parameters can be calculated as follows:
Note: All values except R0 can be rounded off to nearest standard value.
RC2211
PRODUCT SPECIFICATION
+VS 0.1 F C0 FSK Inputs CO 0.1 F 1 2 3 470K 4 5 6 RL1 Logic Output 7 14 13 12 R0 0.1 F R1 C1 +VS RL2 Q Q Logic Outputs
65-2211-07
RC2211
11
RX 5K
10 9 8
+VS
RC2211
11 0.1 F 9 8
RX 5K
10
Both logic outputs at pins 5 and 6 are open-collector type stages, and require external pull-up resistors RL1 and RL2 as shown in Figure 4. With reference to Figures 1 and 4, the function of the external circuit components can be explained as follows: R0 and C0 set VCO center frequency, R1 sets the detection bandwidth, C1 sets the lowpass-loop lter time constant and the loop dampening factor, and RL1 and RL2 are the respective pull-up resistors for the Q and Q logic outputs.
+VS
Figure 3. External Connections for FSK Demodulation with Carrier Detector Capability
The minimum value of the lock detector lter capacitance CD is inversely proportional to the capture range, DfC. This is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is further limited by C1. For most applications, DFC< DF/2. For RD = 470 kW, the approximate minimum value of CD can be determined by: CD(mF) 16/capture range in Hz With values of CD that are too small, chatter can be observed on the lock detector output as an incoming signal frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of the lock detector output.
Design Instructions
The circuit of Figure 4 can be optimized for any tone-detection application by the choice of ve key circuit components: R0, R1, C0, C1 and CD. For a given input tone frequency, FS, these parameters are calculated as follows: 1. 2. 3. Choose R0 to be in the range of 15 kW to 100 kW. This choice is arbitrary. Calculate C0 to set center frequency, f0 equal to FS: C0 = 1/R0FS. Calculate R1 to set bandwidth DF (see Design Equation No. 5): R1 = R0(F0/DF). Note: The total detection bandwidth covers the frequency range of F0 DF. Calculate value of C1 for a given loop damping factor: C1 =C0/16z2 Normally z = 1/2 is optimum for most tone detector applications, giving C1 = 0.25 C0. Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time. 5. Calculate value of lter capacitor CD. To avoid chatter at the logic output, with RD = 470W, CD must be: CD(mF) (16/capture range in Hz) Increasing CD slows the logic output response time.
4.
Tone Detection
Figure 4 shows the generalized circuit connection for tone detection. The logic outputs, Q and Q at pins 5 and 6 are normally at high and low logic states, respectively. When a tone is present within the detection band of the PLL, the logic state at these outputs becomes reversed to the duration of the input tone. Each logic output can sink 5 mA of load current.
PRODUCT SPECIFICATION
RC2211
Design Examples
Tone detector with a detection band of 1 kHz 20 Hz: Step 1: Choose R0 = 20 kW (18 kW in series with 5 kW potentiometer) . Step 2: Choose C0 for F0 = 1 kHz: C0 = 0.05 mF. Step 3: Calculate R1: R1 = (R0) (1000/20) = 1 MW. Step 4: Calculate C1: for z = 1/2, C1 = 0.25 mF, C0 = 0.013 mF. Step 5: Calculate CD: CD = 16/38 = 0.42 mF. Step 6: Fine tune the center frequency with the 5 kW potentiometer. RX.
Linear FM Detection
The RC2211 can be used as a linear FM detector for a wide range of analog communications and telemetry applications. The recommended circuit connection for the application is shown in Figure 5. The demodulated output is taken from the loop phase detector output (pin 11), through a post detection lter made up of RF and CF, and an external buffer amplier. This buffer amplier is necessary because of the high impedance output at pin 11. Normally, a non-inverting unity gain op amp can be used as a buffer amplier, as shown in Figure 5. The FM detector gain, i.e., the output voltage change per unit of FM deviation, can be given as: VOUT = R1 VR/100 R0 Volts/% deviation where VR is the internal reference voltage. For the choice of external components R1, R0, C0, C1 and CF, see the section on Design Instructions.
0.1 F (2) (13) CO CK (14) (12) R0 RF 100K CF +VS (11) (1) (10) 0.1 F +VS
(8)
FM Input
RC2211
(4)
0.1 F
R1 C1
Demodulated Ouput
65-2211-08
RC2211
PRODUCT SPECIFICATION
R0 = 5 kW R0 = 10 kW R0 = 20 kW R0 = 40 kW R0 = 80 kW R0 = 160 kW
10
12 14 16 +VS (V)
18
20 22
24
0.1 100 1K FO (Hz) Figure 7. Timing Resistor with Timing Capacitor vs. VCO Frequency
10K
Figure 6. Supply Current vs. Supply Voltage (Logic Outputs Open Circuited)
1K
1.0
100
65-2211-11
10 0 1 FO (Hz) 10
-1.0 -50
-25
+25
+50
+75
+100
+125
Temperature (C)
Curve 1 2 3 4 5 FO = 1 kHz R 10 R0 4 6 8 10 12 14 -VS (V) Figure 10. VCO Frequency vs. Supply Voltage 16 18 20 22
0.98 0.97
24
65-2211-12
0.5
R0 = 10 kW R0 = 50 kW
1 MW
R0 (kW)
500 kW
0
50 kW
-0.5
R0 = 1 MW R = 500 kW 0
10 kW
65-2211-10
R0 > 100 kW
65-2211-09
10
Q4 B Q17 Q18 R12 18K R11 18K B Q79 D56 D57 D87 Q80 Q88 From VCO Q83 Q84 Q42 Q38 Q47 Q48 Q81 Q82 Q83 Q84 Reference Voltage Input (2) Output D85 Q85 Lock Detector Q86 Filter (3) D86 (5) Lock Detector Outputs (6) Input Pramplifier and Limitter Quadature Phase Detector Lock Detector Comparator D96 D108 D111 D72 D73 A A From VCO A Q60 Q61 Q68 Q62 Q65 Q64 Q71 Q74 (11) Loop f-Detector Output Q97 Q109 A Q95 C0 Timing Capacitor (13) B Q92 D89 D101 D67 Q68 D24 (12) R0 R37 Timing Resistor 8K Voltage Controlled Oscillator Q25 R19 2K (8) Q20 (7) Q23 FSK Comparator Input (14) B Q103 Q27 FSK Data Output Loop Phase Detector FSK Comparator
65-2211-14
PRODUCT SPECIFICATION
Schematic Diagram
+VS (1)
R2 20K
R3 20K
R18 2K
(4) GND
RC2211
RC2211
PRODUCT SPECIFICATION
Notes:
11
PRODUCT SPECIFICATION
RC2211
Notes:
12
RC2211
PRODUCT SPECIFICATION
Notes:
13
PRODUCT SPECIFICATION
RC2211
Mechanical Dimensions
14-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 7, 8 and 14 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 14. 6. Applies to all four corners (leads number 1, 7, 8, and 14). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twelve spaces. D
7 1
Symbol
.200 .014 .023 .045 .065 .008 .015 .785 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 90 105
5.08 .36 .58 1.14 1.65 .20 .38 19.94 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 90 105
NOTE 1
14
s1 eA
A Q L b2 b1 a c1
14
RC2211
PRODUCT SPECIFICATION
Symbol
.210 .015 .115 .195 .014 .022 .045 .070 .008 .015 .725 .795 .005 .300 .325 .240 .280 .100 BSC .430 .115 .200 14
5.33 .38 2.93 4.95 .36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 7.62 8.26 6.10 7.11 2.54 BSC 10.92 2.92 5.08 14
D 7 1
E1
D1
14
E e A A1 L B1 B eB C
15
PRODUCT SPECIFICATION
RC2211
Ordering Information
Part Number RC2211N RV2211N RM2211D RM2211D/883B Package N N D D Operating Temperature Range 0C to +70C -25C to +85C -55C to +125C -55C to +125C
Notes: /883B suffix denotes MIL-STD-883, Par 1.2.1 Compliant Devices N = 14-Lead Plastic DIP D = 14-Lead Ceramic DIP
The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the terms and conditions of any subsequent sale. Raytheons liability shall be determined solely by its standard terms and conditions of sale. No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied. Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors.