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INDEX
Technical Specifications Project Abstract Project Block Diagram CHAPTER 1: INTRODUCTION 1.1Introduction CHAPTER 2: BLOCK DESCRIPTION 2.1 Power Supply 2.1.1 Transformer 2.1.2 Rectifier 2.1.3 Filter 2.1.4 Voltage Regulator CHAPTER 3: AT89S52 Microcontroller 3.1 Features of AT89S52 Microcontroller 3.2 Description 3.3 Pin Description 3.4 Machine Cycle 3.5 ALE/PROG 3.6 PSEN 3.7 EA 3.8 Ports 3.9 Data Memory 3.10 EEPROM CHAPTER 4: IMPORTANT TERMINOLOGY TO MEMORIES 4.1 Memory Capacity 4.2 Memory Organization 4.3 Speed 4.4 EEPROM 4.5 Features Of EEPROM 4.6 Description 4.7 Signal Description 4.8 Device Operation 32 32 32 33 33 35 37 38 4 6 8 11 11 14 15 15 16 16 16 17 19 19 22 25 26 26 26 27 29 31
4.9 Minimizing Delays 4.10 Read Operations 4.11 Programming The Flash EEPROM 4.12 Data Polling 4.13 Ready/Busy 4.14 Program Verify 4.15 Chip Erase 4.16 Serial Downloading 4.17 Machine Cycle For 8052 4.18 Relays 4.19 Operation 4.20 Transistor Driver Circuit 4.21 RELAY INTERFACING WITH Uc CHAPTER 5: LIQUID CRYSTAL DISPLAY 5.1 Pin Function 5.2 Lcd Screen 5.3 Lcd Basic Commands 5.4 Lcd Initialisation 5.5 Lcd Interfacing With The Uc 5.6 Code(Command) 5.7 Code(Data) 5.8 Switch Interfacing With The uC 5.9 Trigger Card 5.10 Slots For Recharge 5.11 Load Banks 5.12 Energy Meter 5.13 ADE7757 5.14 Design Calculations CHAPTER 6: POWER SUPPLY 6.1 Transformer 6.2 Rectifier 6.3 Filter 6.4 Voltage Regulator
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43 46 48 49 50 50 50 51 52 52 53 54 56 59 60 61 62 63 65 66 67 68 68 68 68 69 70
73 73 76 76
CHAPTER 7: SOFTWARE TOOLS 7.1 Keil Software 7.2 Steps To Write Programming 7.3 Proload 7.4 Advantages 7.5 Applications RESULT CONCLUSION REFERENCES APPENDIX 79 79 81 82 82 85 87 89 90
DESCRIPTION
Block Diagram Recharging Unit Power Supply Section Pin Diagram Architechture
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PAGE NO.
10 11 15 20 21
3.3. 3.3.4 4.1.1 4.1.2 4.5 4.7 4.8 4.8.1 4.9.1 4.9.2 4.10 4.18 4.20 4.21 4.22 5.2 5.4 5.8 5.13 6.0 6.1 6.2 6.3
Oscillator Connection DIP Pin Connection SO Pin Connection Logic Diagram Memory Protection I2C Protocol Ac Wave Form Write Cycle Polling Using ACK Write Mode Sequence Read Mode Sequence Circuit Symbol Of Relay Transistor Driver Circuit Relay Interface Lcd Screen Procedure For 8 Bit Initialization Switch Interfacing Energy Meter Power Supply Transformer Rectifier Expected Wave Form
22 34 34 35 37 39 41 44 45 47 53 55 56 60 63 67 69 72 73 73 75
DESCRIPTION
PAGE NO.
25 28 29 31 34 36 36 60
3.9 Mcon Register Functions 4.1 Signal Names 4.6.1 Device Select Modes 4.6.2 Operating Modes 5.1 Pin Functions
TECHNICAL SPECIFICATIONS
Title of the project Domain Software Microcontroller Power Supply Display Crystal Applications
: : : : : : : :
EMBEDDED PREPAID ENERGY METER Energy calculation, Embedded Design, Energy System Embedded C, Keil, Proload AT89S52 +5V, 750mA Regulated Power Supply 16 X 2 Alphanumeric LCD 11.0592MHz Emergency lighting, water heaters, Industrial applications
ABSTRACT
BLOCK DIAGRAM
Block Diagram
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Load Bank
EEPROM
RELAY
8 9 s 5 2 16 X 2 LCD
Energy Meter
Trigger card
Bridge Rectifier
Filter Circuit
RECHARGING UNIT:
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O/P 5V
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INTRODUCTION
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CHAPTER 1 INTRODUCTION
An embedded system is a combination of software and hardware to perform a dedicated task. Some of the main devices used in embedded products are Microprocessors and Microcontrollers. Microprocessors are commonly referred to as general purpose processors as they simply accept the inputs, process it and give the output. In contrast, a microcontroller not only accepts the data as inputs but also manipulates it, interfaces the data with various devices, controls the data and thus finally gives the result. As everyone in this competitive world prefers to make the things easy and simple to handle, this project sets an example to some extent. This project enables the user to consume the electricity based on the prepaid recharge card he gets from the electrical department. The information such as the total number of units available in the card will be displayed on the LCD. Thus accordingly, the user has to consume the power and if the units are totally completed, he has to go for another recharge card.
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2.1 POWER SUPPLY: The input to the circuit is applied from the regulated power supply. The a.c. input i.e., 230V from the mains supply is step down by the transformer to 12V and is fed to a rectifier. The output obtained from the rectifier is a pulsating d.c voltage. So in order to get a pure d.c voltage, the output voltage from the rectifier is fed to a filter to remove any a.c components present even after rectification. Now, this voltage is given to a voltage regulator to obtain a pure constant dc voltage.
230V AC 50Hz
D.C Output
Bridge Rectifier
Filter
Regulator
Fig: 2.1 Power supply 2.1.1 Transformer: Usually, DC voltages are required to operate various electronic equipment and these voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus the a.c input available at the mains supply i.e., 230V is to be brought down to the required voltage level. This is done by a transformer. Thus, a step down transformer is employed to decrease the voltage to a required level.
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2.1.2 Rectifier: The output from the transformer is fed to the rectifier. It converts A.C. into pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a bridge rectifier is used because of its merits like good stability and full wave rectification. 2.1.3 Filter: Capacitive filter is used in this project. It removes the ripples from the output of rectifier and smoothens the D.C. Output received from this filter is constant until the mains voltage and load is maintained constant. However, if either of the two is varied, D.C. voltage received at this point changes. Therefore a regulator is applied at the output stage. 2.1.4 Voltage regulator: As the name itself implies, it regulates the input applied to it. A voltage regulator is an electrical regulator designed to automatically maintain a constant voltage level. In this project, power supply of 5V and 12V are required. In order to obtain these voltage levels, 7805 and 7812 voltage regulators are to be used. The first number 78 represents positive supply and the numbers 05, 12 represent the required output voltage levels.
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AT89S52 MICROCONTROLLER
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CHAPTER 3 MICROCONTROLLERS
Microprocessors and microcontrollers are widely used in embedded systems products. Microcontroller is a programmable device. A microcontroller has a CPU in addition to a fixed amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed amount of on-chip ROM, RAM and number of I/O ports in microcontrollers makes them ideal for many applications in which cost and space are critical. The Intel 8052 is Harvard architecture, single chip microcontroller (C) which was developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s and early 1990s, but today it has largely been superseded by a vast range of enhanced devices with 8052-compatible processor cores that are manufactured by more than 20 independent manufacturers including Atmel, Infineon Technologies and Maxim Integrated Products. 8052 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. 8052 is available in different memory types such as UVEPROM, Flash and NV-RAM. The present project is implemented on Keil Uvision. In order to program the device, proload tool has been used to burn the program onto the microcontroller. The features, pin description of the microcontroller and the software tools used are discussed in the following sections.
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3.2 Description:
The AT89S52 is a low-voltage, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcomputer, which provides a highly flexible and cost-effective solution to many embedded control applications. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
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Fig: diagram
3.2.Pin
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Pin 40 provides supply voltage to the chip. The voltage source is +5V. 3.3.2 GND: Pin 20 is the ground. 3.3.3 XTAL1 and XTAL2: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in the below figure. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Fig: 3.3.3 Oscillator Connections C1, C2 = 30 pF 10 pF for Crystals = 40 pF 10 pF for Ceramic Resonators
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3.3.4 RESET: Pin9 is the reset pin. It is an input and is active high. Upon applying a high pulse to this pin, the microcontroller will reset and terminate all the activities. This is often referred to as a power-on reset.
3.3.5 EA (External access): Pin 31 is EA. It is an active low signal. It is an input pin and must be connected to either Vcc or GND but it cannot be left unconnected. The 8052 family members all come with on-chip ROM to store programs. In such cases, the EA pin is connected to Vcc. If the code is stored on an external ROM, the EA pin must be connected to GND to indicate that the code is stored externally.
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3.3.6 PSEN (Program store enable): This is an output pin. 3.3.7 ALE (Address latch enable): This is an output pin and is active high. 3.3.8 Ports 0, 1, 2 and 3: The four ports P0, P1, P2 and P3 each use 8 pins, making them 8-bit ports. All the ports upon RESET are configured as input, since P0-P3 have value FFH on them. Port 0(P0): Port 0 is also designated as AD0-AD7, allowing it to be used for both address and data. ALE indicates if P0 has address or data. When ALE=0, it provides data D0D7, but when ALE=1, it has address A0-A7. Therefore, ALE is used for demultiplexing address and data with the help of an internal latch. When there is no external memory connection, the pins of P0 must be connected to a 10K-ohm pull-up resistor. This is due to the fact that P0 is an open drain. With external pull-up resistors connected to P0, it can be used as a simple I/O, just like P1 and P2. But the ports P1, P2 and P3 do not need any pull-up resistors since they already have pull-up resistors internally. Upon reset, ports P1, P2 and P3 are configured as input ports.
Port 1 and Port 2: With no external memory connection, both P1 and P2 are used as simple I/O. With external memory connections, port 2 must be used along with P0 to provide the 16-bit address for the external memory. Port 2 is designated as A8-A15 indicating its dual function. While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of the address.
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Port 3: Port 3 occupies a total of 8 pins, pins 10 through 17. It can be used as input or output. P3 does not need any pull-up resistors, the same as port 1 and port 2. Port 3 has an additional function of providing some extremely important signals such as interrupts.
Table: 3.3 Port 3 Alternate Functions 3.4 Machine cycle for the 8052: The CPU takes a certain number of clock cycles to execute an instruction. In the 8052 family, these clock cycles are referred to as machine cycles. The length of the machine cycle depends on the frequency of the crystal oscillator. The crystal oscillator, along with on-chip circuitry, provides the clock source for the 8052 CPU. The frequency can vary from 4 MHz to 30 MHz, depending upon the chip rating and manufacturer. But the exact frequency of 11.0592 MHz crystal oscillator is used to make the 8052 based system compatible with the serial port of the IBM PC. In the original version of 8052, one machine cycle lasts 12 oscillator periods. Therefore, to calculate the machine cycle for the 8052, the calculation is made as 1/12 of the crystal frequency and its inverse is taken. The assembly language program is written and this program has to be dumped into the microcontroller for the hardware kit to function according to the software. The program dumped in the microcontroller is stored in the Flash memory in the
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microcontroller. Before that, this Flash memory has to be programmed and is discussed in the next section. 3.5 ALE/PROG: Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. 3.6 PSEN (Program Store Enable): It is the read strobe to external program memory. When the AT89S8252 is executing code from external program memory, PSEN is acti-vated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. 3.7 EA/VPP (External Access Enable): EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected.
but when ALE=1, it has address A0-A7. Therefore, ALE is used for demultiplexing address and data with the help of an internal latch. When there is no external memory connection, the pins of P0 must be connected to a 10K-ohm pull-up resistor. This is due to the fact that P0 is an open drain. With external pull-up resistors connected to P0, it can be used as a simple I/O, just like P1 and P2. But the ports P1, P2 and P3 do not need any pull-up resistors since they already have pull-up resistors internally. Upon reset, ports P1, P2 and P3 are configured as input ports. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pull-ups. Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively. Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins. Port 1 also receives the low-order address bytes during Flash programming and verification.
A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/0 pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). Port 2: With no external memory connection, P2 are used as simple I/O. With external memory connections, port 2 must be used along with P0 to provide the 16-bit address for the external memory. Port 2 is designated as A8-A15 indicating its dual function. While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of the address. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S8252, as shown in the following table.
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3.9 Data Memory EEPROM and RAM: The AT89S8252 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers i.e., the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data It should be noted that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. The on-chip EEPROM data memory is selected by setting the EEMEN bit in the WMCON register at SFR address location 96H. The EEPROM address range is from 000H to 7FFH. The MOVX instructions are used to access the EEPROM. To access off-chip data memory with the MOVX instructions, the EEMEN bit needs to be set to 0.
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The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM, and to enable byte-write. The DPS bit selects one of two DPTR registers available. Symbol PS2 PS1 PS0 EEMWE Function Prescaler Bits. When all three bits are set to 0, the timer has a nominal period of 16 ms. When all three bits are set to 1; the nominal period is 2048 ms. These bits are used for watchdog timer. EEPROM Data Memory Write Enable Bit. Set this bit to 1 before initiating byte write to on-chip EEPROM with the MOVX instruction. User software should set this bit to 0 after EEPROM write is EEMEN completed. Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external DPS RDY/BSY data memory. Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the second bank, DP1 RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed, the RDY/BSY bit equals 0 and is automatically reset to 1 when programming is WDTEN completed. Used for Watchdog timer Table: 3.9 MCON Register functions
3.10 EEPROM: In the design of all microprocessors-based systems, semiconductor memories are used as primary storage for code and data. Semiconductor memories are
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connected directly to the CPU and they are the memory that the CPU first asks for information (code and data). For this reason, semiconductor memories are sometimes referred to as primary memory.
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memory chip can store is equal to the number of locations times the number of data bits per location.
4.3 Speed:
One of the most important characteristics of a memory chip is the speed at which its data can be accessed. The speed of the memory chip is commonly referred to as its access time. The access time of memory chip varies from a few nanoseconds to hundreds of nanoseconds, depending on the IC technology used in the design and fabrication process. The different types of memories are RAM, ROM, EPROM and EEPROM. RAM and ROM are inbuilt in the microprocessor. This project requires the data such as the total number of available units and the pulse count to be stored permanently and this data modifies upon the power consumption. Thus this data has to be stored in such a location where it cannot be erased when power fails and also the data should be allowed to make changes in it without the system interface i.e., there should be a provision in such a way that the data should be accessed (or modified) while it is in system board but not external erasure and programming. The flash memory inbuilt in the microcontroller can erase the entire contents in less than a second and the erasure method is electrical. But the major drawback of Flash memory is that when flash memorys contents are erased, the entire device will be erased but not a desired section or byte. For this purpose, we prefer EEPROM in our project.
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contents of ROM are erased. The main advantage of EEPROM is that one can program and erase its contents while it is in system board. It does not require physical removal of the memory chip from its socket. In general, the cost per bit for EEPROM is much higher when compared to other devices. The EEPROM used in this project is 24C04 type. 4.5 Features of 24C04 EEPROM:
1 million erase/write cycles with 40 years data retention. Single supply voltage. 3v to 5.5v for st24x04 versions. 2.5v to 5.5v for st25x04 versions. Hardware write control versions. St24w04 and st25w04 versions. Programmable write protection. Two wire serial interface, fully i2c bus compatible. Byte and multibyte write (up to 4 bytes). Page write (up to 8 bytes). Byte, random and sequential read modes Self timed programming cycle Automatic address incrementing Enhanced ESD/Latch up performances
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4.6 DESCRIPTION: The 24C04 is a 4Kbit electrically erasable programmable memory (EEPROM), organized as 2 blocks of 256 x8 bits. They are manufactured in ST Microelectronics Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. Both
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Plastic Dual-in-Line and Plastic Small Outline packages are available. The memories are compatible with the I2C standard, two wire serial interface which uses a bidirectional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. This is used together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices may be attached to the I2C bus and selected individually. The memories behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.
Table:4.6.2 Operating Modes When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus
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master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. 4.6.1 Power on Reset: VCC locks out write protect : In order to prevent data corruption and inadvertent write operations during power up, a Power on Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. 4.7 SIGNAL DESCRIPTIONS: Serial Clock (SCL): The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up. Serial Data (SDA): The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-ORed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up. Chip Enable (E1 - E2): These chip enable inputs are used to set the 2 least significant bits (b2, b3) of the 7 bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code. Protect Enable (PRE): The PRE input pin, in addition to the status of the Block Address Pointer bit (b2, location 1FFh as in below figure), sets the PRE write protection active.
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Fig: 7.1 Memory Protection Mode (MODE): The MODE input is available on pin 7 and may be driven dynamically. It must be at VIL or VIH for the Byte Write mode, VIH for Multibyte Write mode or VIL for Page Write mode. When unconnected, the MODE input is internally read as VIH (Multibyte Write mode). Write Control (WC): An hardware Write Control feature (WC) is offered only for ST24W04 and ST25W04 versions on pin 7. This feature is useful to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or disable (WC =VIL) the internal write protection. When unconnected, the WC input is internally read as VIL and the memory area is not write protected.
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Start Condition:
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START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x04 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition: STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25x04 and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK): An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input: During data input the ST24/25x04 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing: To start communication between the bus master and the slave ST24/25x04, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit. The 4 most significant bits of the device select code are the device type identifier, corresponding to the I2C bus definition. For these memories the 4 bits are fixed as 1010b. The following 2 bits identify the specific memory on the bus. They are matched to the chip enable signals E2, E1. Thus up to 4 x 4K memories can be connected on the same bus giving a memory capacity total of 16 Kilobits.
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After a START condition any memory on the bus will identify the device code and compare the following 2 bits to its chip enable inputs E2, E1. The 7th bit sent is the block number (one block = 256 bytes). The 8th bit sent is the read or write bit (RW), this bit is set to 1 for read and 0 for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time.
Fig: 4.8.1 AC Waveforms Write Operations: The Multibyte Write mode (only available on the ST24/25C04 versions) is selected when the MODE pin is at VIH and the Page Write mode when MODE pin is at VIL. The MODE pin may be driven dynamically with CMOS input levels. Following a START condition the master sends a device select code with the RW bit
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reset to 0. The memory acknowledges this and waits for a byte address. The byte address of 8 bits provides access to one block of 256 bytes of the memory. After receipt of the byte address the device again responds with an acknowledge. For the ST24/25W04 versions, any write command with WC = 1 will not modify the memory content. Byte Write: In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. The Write mode is independent of the state of the MODE pin which could be left floating if only this mode was to be used. However it is not a recommended operating mode, as this pin has to be connected to either VIH or VIL, to minimize the stand-by current. Multibyte Write: For the Multibyte Write mode, the MODE pin must be at VIH. The Multibyte Write mode can be started from any address in the memory. The master sends from one up to 4 bytes of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a STOP condition. The duration of the write cycle is Tw = 10ms maximum except when bytes are accessed on 2 rows (that is have different values for the 6 most significant address bits A7-A2), the programming time is then doubled to a maximum of 20ms. Writing more than 4 bytes in the Multibyte Write mode may modify data bytes in an adjacent row (one row is 8 bytes long). However, the Multibyte Write can properly write up to 8 consecutive bytes as soon as the first address of these 8 bytes is the first address of the row, the 7 following bytes being written in the 7 following bytes of this same row.
Page Write: For the Page Write mode, the MODE pin must be at VIL. The Page Write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is the 5 most significant memory address bits (A7-A3) are the same inside one block. The master sends from one up to
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8 bytes of data, which are each acknowledged by the memory. After each byte is transferred, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter roll-over which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. 4.9 Minimizing System Delays by Polling on ACK: During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (Tw) is given from the AC Characteristics, since the typical time is shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the master.
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Fig:4.9.1 Write Cycle Polling using ACK Data in the upper block of 256 bytes of the memory may be write protected. The memory is write protected between a boundary address and the top of memory (address 1FFh) when the PRE input pin is taken high and when the Protect Flag (bit b2 in location 1FFh) is set to 0. The boundary address is user defined by writing it in the Block Address Pointer. The Block Address Pointer is an 8 bit EEPROM register located at the address 1FFh. It is composed by 5 MSBs Address Pointer, which defines the bottom boundary address and 3 LSBs which must be programmed at 0. This Address Pointer can therefore address a boundary in steps of 8 bytes.
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write the data to be protected into the top of the memory, up to, but not including, location 1FFh; set the protection by writing the correct bottom boundary address in the Address Pointer (5 MSBs of location 1FFh) with bit b2 (Protect flag) set to 0. Note that for a correct functionality of the memory, all the 3 LSBs of the Block Address Pointer must also be programmed at 0. The area will now be protected when the PRE input pin is taken high. While the PRE input pin is read at 0 by the memory, the location 1FFh can be used as a normal EEPROM byte.
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Read operations are independent of the state of the MODE pin. On delivery, the memory content is set at all "1s" (or FFh). Current Address Read: The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a memory address with the RW bit set to 1. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. Random Address Read: A dummy write is performed to load the address into the address counter. This is followed by another START condition from the master and the byte address is repeated with the RW bit set to 1. The memory acknowledges this and outputs the byte addressed. The master has to NOT acknowledge the byte output, but terminates the transfer with a STOP condition. Sequential Read: This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will rollover and the memory will continue to output data.
Acknowledge in Read Mode: In all read modes the ST24/25x04 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25x04 terminate the data transfer and switches to a standby state.
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4.11 PROGRAMMING THE FLASH AND EEPROM Atmels AT89S8252 Flash Microcontroller offers 8K bytes of in-system reprogrammable Flash Code memory and 2K bytes of EEPROM Data memory. The AT89S8252 is normally equipped with the on-chip Flash Code and EEPROM Data memory arrays in the erased state (i.e. contents = FFH) and ready to be programmed.
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This device supports a high-voltage (12-V VPP) Parallel programming mode and a low-voltage (5-V VCC) Serial programming mode. Serial Programming mode: This mode provides a convenient way to reprogram the AT89S8252 inside the users system. The Code and Data memory arrays are mapped via separate address spaces in this mode. An auto-erase cycle is provided with the self-timed programming operation. There is no need to perform the Chip Erase operation to reprogram any memory location in this programming mode unless any of the lock bits have been programmed. Parallel Programming mode: The parallel programming mode is compatible with conventional third party Flash or EPROM programmers. In this mode, the two arrays occupy one contiguous address space: 0000H to 1FFFH for the Code array and 2000H to 27FFH for the Data array. In this mode, there is no auto-erase cycle. To reprogram any non-blank byte, the user needs to use the Chip Erase operation first to erase both arrays. The Code and Data memory arrays on the AT89S8252 are programmed byteby-byte in either programming mode.
To program and verify the AT89S8252 in the parallel programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to H. Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 milliseconds.
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2. Set PSEN pin to L ALE pin to H EA pin to H and all other pins to H. 3. Apply the appropriate combination of H or L logic levels to pins P2.6, P2.7, P3.6, and P3.7 to select one of the programming operations shown in the Flash Programming Modes table. 4. Apply the desired byte address to pins P1.0 to P1.7 and P2.0 to P2.5. Apply data to pins P0.0 to P0.7 for Write Code operation. 5. Raise EA/VPP to 12V to enable Flash programming, erase or verification. 6. Pulse ALE/PROG once to program a byte in the Code memory array, the Data mem-ory array or the lock bits. The byte-write cycle is self-timed and typically takes 1.5 ms. 7. To verify the byte just programmed, bring pin P2.7 to L and read the programmed data at pins P0.0 to P0.7. 8. Repeat steps 3 through 7 changing the address and data for the entire 2K or 8K bytes array or until the end of the object file is reached. 9. Power-off sequence: Set XTAL1 to L. Set RST and EA pins to L. Turn VCC power off.
4.13 Ready/Busy:
The progress of byte programming in the parallel programming mode can also be monitored by the RDY/BSY output signal. Pin P3.4 is pulled Low after ALE goes
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high during programming to indicate BUSY. P3.4 is pulled High again when programming is done to indicate READY.
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Code and Data memory arrays have separate address spaces: 0000H to 1FFFH for Code memory and 000H to 7FFH for Data memory. Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/40 of the crystal frequency. With a 24 MHz oscillator clock, the maximum SCK frequency is 600 kHz.
At the end of a programming session, RST can be set low to commence normal
operation.
6. Power-off sequence (if needed): Set XTAL1 to L (if a crystal is not used). Set RST to L. Turn VCC power off. The algorithm used in this project to enable EEPROM is serial programming mode. 4.17 Machine cycle for the 8052
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The CPU takes a certain number of clock cycles to execute an instruction. In the 8052 family, these clock cycles are referred to as machine cycles. The length of the machine cycle depends on the frequency of the crystal oscillator. The crystal oscillator, along with on-chip circuitry, provides the clock source for the 8052 CPU. The frequency can vary from 4 MHz to 30 MHz, depending upon the chip rating and manufacturer. But the exact frequency of 11.0592 MHz crystal oscillator is used to make the 8052 based system compatible with the serial port of the IBM PC. In the original version of 8052, one machine cycle lasts 12 oscillator periods. Therefore, to calculate the machine cycle for the 8052, the calculation is made as 1/12 of the crystal frequency and its inverse is taken. 4.18 RELAYS: A relay is an electrically controllable switch widely used in industrial controls, automobiles and appliances. The relay allows the isolation of two separate sections of a system with two different voltage sources i.e., a small amount of voltage/current on one side can handle a large amount of voltage/current on the other side but there is no chance that these two voltages mix up.
Fig:4.18 Circuit symbol of a relay 4.19 Operation: When a current flow through the coil, a magnetic field is created around the coil i.e., the coil is energized. This causes the armature to be attracted to the coil. The armatures contact acts like a switch and closes or opens the circuit. When the coil is
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not energized, a spring pulls the armature to its normal state of open or closed. There are all types of relays for all kinds of applications.
Transistors and ICs must be protected from the brief high voltage 'spike' produced when the relay coil is switched off. The above diagram shows how a signal diode (eg 1N4148) is connected across the relay coil to provide this protection. The diode is connected 'backwards' so that it will normally not conduct. Conduction occurs only when the relay coil is switched off, at this moment the current tries to flow continuously through the coil and it is safely diverted through the diode. Without the diode no current could flow and the coil would produce a damaging high voltage 'spike' in its attempt to keep the current flowing. In choosing a relay, the following characteristics need to be considered: 1. The contacts can be normally open (NO) or normally closed (NC). In the NC type, the contacts are closed when the coil is not energized. In the NO type, the contacts are closed when the coil is energized. 2. There can be one or more contacts. i.e., different types like SPST (single pole single throw), SPDT (single pole double throw) and DPDT (double pole double throw) relays.
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3. The voltage and current required to energize the coil. The voltage can vary from a few volts to 50 volts, while the current can be from a few milliamps to 20milliamps. The relay has a minimum voltage, below which the coil will not be energized. This minimum voltage is called the pull-in voltage. 4. The minimum DC/AC voltage and current that can be handled by the contacts. This is in the range of a few volts to hundreds of volts, while the current can be from a few amps to 40A or more, depending on the relay.
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Vcc
The operation of this circuit is as follows: The input to the base of the transistor is applied from the microcontroller port pin P1.0. The transistor will be switched on when the base to emitter voltage is greater than 0.7V (cut-in voltage). Thus when the voltage applied to the pin P1.0 is high i.e., P1.0=1 (>0.7V), the transistor will be switched on and thus the relay will be ON and the load will be operated. When the voltage at the pin P1.0 is low i.e., P1.0=0 (<0.7V) the transistor will be in off state and the relay will be OFF. Thus the transistor acts like a current driver to operate the relay accordingly. 4.21 RELAY INTERFACING WITH THE MICROCONTROLLER:
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AT 89S52
LOAD
P1.0
LCD INTERFACING
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Fig:5.1 LCD A model described here is for its low price and great possibilities most frequently used in practice. It is based on the HD44780 microcontroller (Hitachi) and can display messages in two lines with 16 characters each . It displays all the alphabets, Greek letters, punctuation marks, mathematical symbols etc. In addition, it is possible to display symbols that user makes up on its own. Automatic shifting
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message on display (shift left and right), appearance of the pointer, backlight etc. are considered as useful characteristics.
5.1Pin Functions:
There are pins along one side of the small printed board used for connection to the microcontroller. There are total of 14 pins marked with numbers (16 in case the background light is built in). Their function is described in the table below:
Pin Number 1 2 3
Logic State 0 1
Description 0V +5V 0 - Vdd D0 D7 are interpreted as commands D0 D7 are interpreted as data Write data (from controller
RS
Control of operating
R/W
0 1 0
to LCD) Read data (from LCD to controller) Access to LCD disabled Normal operating Data/commands are
1 From 1 to
Data / commands
7 8 9 10 11 12 13 14
0 transferred to LCD D0 0/1 Bit 0 LSB D1 0/1 Bit 1 D2 0/1 Bit 2 D3 0/1 Bit 3 D4 0/1 Bit 4 D5 0/1 Bit 5 D6 0/1 Bit 6 D7 0/1 Bit 7 MSB Table 5.1 pin functions
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RS = 0 - Bits D0 - D7 are commands which determine display mode. List of commands which LCD recognizes are given in the table below:
Command Clear display Cursor home Entry mode set Display on/off control Cursor/Display Shift Function set Set CGRAM address Set DDRAM address Read BUSY flag (BF) Write to CGRAM or DDRAM Read from CGRAM or DDRAM I/D 1 = Increment (by 1) 0 = Decrement (by 1) S 1 = Display shift on 0 = Display shift off D 1 = Display on 0 = Display off U 1 = Cursor on 0 = Cursor off B 1 = Cursor blink on
Execution Time 1.64mS 1.64mS 40uS 40uS 40uS 40uS 40uS 40uS 40uS 40uS
0 0 0 0 0 0 0 0 0 1 1 BF
0 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 R/L 1 = Shift right 0 = Shift left DL 1 = 8-bit interface 0 = 4-bit interface N 1 = Display in two lines 0 = Display in one line
F 1 = Character format 5x10 dots 0 = Character format 5x7 dots D/C 1 = Display shift
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0 = Cursor shift
5.4 LCD Initialization: Once the power supply is turned on, LCD is automatically cleared. This process lasts for approximately 15mS. After that, display is ready to operate. The mode of operating is set by default. This means that: 1. Display is cleared 2. Mode DL = 1 Communication through 8-bit interface N = 0 Messages are displayed in one line F = 0 Character font 5 x 8 dots 3. Display/Cursor on/off D = 0 Display off U = 0 Cursor off B = 0 Cursor blink off 4. Character entry ID = 1 Addresses on display are automatically incremented by 1 S = 0 Display shift off Automatic reset is mainly performed without any problems. Mainly but not always! If for any reason power supply voltage does not reach full value in the course of 10mS, display will start perform completely unpredictably? If voltage supply unit can not meet this condition or if it is needed to provide completely safe operating, the process of initialization by which a new reset enabling display to operate normally must be applied. Algorithm according to the initialization is being performed depends on whether connection to the microcontroller is through 4- or 8-bit interface. All left over to be done after that is to give basic commands and of course- to display messages.
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1 2 3
Vcc Gnd
89S52
D0 D1 D2 D3 D4 D5 D6 D7
Fig: 5.5 Sending Commands to LCD To send commands we simply need to select the command register. Everything is same as we have done in the initialization routine. But we will summarize the common steps and put them in a single subroutine. Following are the steps: Move data to LCD port select command register select write operation send enable signal wait for LCD to process the command
5.6 CODE:
void LCD_command(unsigned char var) { LCD_data = var; LCD_rs = 0; LCD_rw = 0; LCD_en = 1; //Function set: 2 Line, 8-bit, 5x7 dots //Selected command register //We are writing in instruction register //Enable H->L
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LCD_en = 0; LCD_busy(); } // Using the above function is really simple // var will carry the command for LCD // e.g. // // LCD_command(0x01); Sending Data to LCD //Wait for LCD to process the command
To send data we simply need to select the data register. Everything is same as the command routine. Following are the steps: Move data to LCD port select data register select write operation send enable signal wait for LCD to process the data
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Keeping these steps in mind we can write LCD command routine as. 5.7 CODE: void LCD_senddata(unsigned char var) { LCD_data = var; LCD_rs = 1; LCD_rw = 0; LCD_en = 1; LCD_en = 0; LCD_busy(); } // Using the above function is really simple // we will pass the character to display as argument to function // e.g. // // LCD_senddata('A'); //Wait for LCD to process the command //Function set: 2 Line, 8-bit, 5x7 dots //Selected data register //We are writing //Enable H->L
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Switches are the most widely used input/output devices of the 8052. CPU accesses the switches through ports. Therefore these switches are connected to a microcontroller. This switch is connected between the supply and ground terminals. A single microcontroller (consisting of a microprocessor, RAM and EEPROM and several ports all on a single chip) takes care of hardware and software interfacing of the switch. These switches are connected to an input port. When no switch is pressed, reading the input port will yield 1s since they are all connected to high (Vcc). But if any switch is pressed, one of the input port pins will have 0 since the switch pressed provides the path to ground. It is the function of the microcontroller to scan the switches continuously to detect and identify the switch pressed. The switches that we are using in our project are 4 leg micro switches of momentary type.
Vcc
P0.2 Gnd
Fig: 5.8 Interfacing switch with the microcontroller Thus now the two conditions are to be remembered:
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1. When the switch is open, the total supply i.e., Vcc appears at the port pin P0.2 P0.2 = 1 2. When the switch is closed i.e., when it is pressed, the total supply path is provided to ground. Thus the voltage value at the port pin P0.2 will be zero. P0.2 = 0 By reading the pin status, the microcontroller identifies whether the switch is pressed or not. When the switch is pressed, the corresponding related to this switch press written in the program will be executed.
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circuit that serves as a clock source to the chip. The ADE7757 eliminates the cost of an external crystal or resonator, thus reducing the overall cost of a meter built with this IC. The chip directly interfaces with shunt resistor. The ADE7757 provides instantaneous and average real power based on line current and voltage. The part specifications surpass the accuracy requirements as quoted in the IEC1036 standard. The only analog circuitry used in the ADE7757 is in the ADCs and reference circuit. All other signal processing (e.g., multiplication and filtering) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The small analog input full-scale allows the chip to interface to low value shunt resistances without losing dynamic range. The ADE7757 is available in 16-lead SOIC narrow-body package.
The design parameters are as follows: Line voltage = 220 V (nominal) IMAX = 30 A (Ib = 5 A) Counter = 100 imp/kWh Meter constant = 1600 imp/kWh Shunt size = 350 micro ohms.
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100 imp/hour = 100/3600 sec = 0.02777 Hz Meter calibration at Ib (5 A) Power dissipation at Ib = 220 V 5 A = 1.2 kW Freq. on F1 (and F2) at Ib = 1.1 0.0277 Hz = 0.0305555 Hz Voltage across shunt (V1) at Ib = 5 A x 350 (micro ohms) = 1.75 mV rms
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230V AC
50Hz
D.C Output
Bridge Rectifier
Filter
Regulator
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6.1Transformer:
Usually, DC voltages are required to operate various electronic equipment and these voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus the a.c input available at the mains supply i.e., 230V is to be brought down to the required voltage level. This is done by a transformer. Thus, a step down transformer is employed to decrease the voltage to a required level.
Fig:6.1 Transformer
6.2 Rectifier:
The output from the transformer is fed to the rectifier. It converts A.C. into pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a bridge rectifier is used because of its merits like good stability and full wave rectification.
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The Bridge rectifier is a circuit, which converts an ac voltage to dc voltage using both half cycles of the input ac voltage. The Bridge rectifier circuit is shown in the figure. The circuit has four diodes connected to form a bridge. The ac input voltage is applied to the diagonally opposite ends of the bridge. The load resistance is connected between the other two ends of the bridge. For the positive half cycle of the input ac voltage, diodes D1 and D3 conduct, whereas diodes D2 and D4 remain in the OFF state. The conducting diodes will be in series with the load resistance RL and hence the load current flows through RL. For the negative half cycle of the input ac voltage, diodes D2 and D4 conduct whereas, D1 and D3 remain OFF. The conducting diodes D2 and D4 will be in series with the load resistance RL and hence the current flows through RL in the same direction as in the previous half cycle. Thus a bi-directional wave is converted into a unidirectional wave.
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6.3Filter:
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Capacitive filter is used in this project. It removes the ripples from the output of rectifier and smoothens the D.C. Output received from this filter is constant until the mains voltage and load is maintained constant. However, if either of the two is varied, D.C. voltage received at this point changes. Therefore a regulator is applied at the output stage.
Fig:6.4Voltage Regulator
As the name itself implies, it regulates the input applied to it. A voltage regulator is an electrical regulator designed to automatically maintain a constant voltage level. In this project, power supply of 5V and 12V are required. In order to obtain these voltage levels, 7805 and 7812 voltage regulators are to be used. The first number 78 represents positive supply and the numbers 05, 12 represent the required output voltage levels. The L78xx series of three-terminal positive regulators is available in TO-220, TO-220FP, TO-3, D2PAK and DPAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide eliminating the associated with single local on-card regulation, distribution problems point regulation.
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Fig Voltage Regulator Each type employs internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltage and currents.
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Software Tools
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7.2 Steps To Write An Assembly / C Language Program In Keil And How To Compile It:
1. Install the Keil Software in the PC in any of the drives. 2. After installation, an icon will be created with the name Keil uVision3. Just drag this icon onto the desktop so that it becomes easy whenever you try to write programs in keil. 3. Double click on this icon to start the keil compiler. 4. A page opens with different options in it showing the project workspace at the leftmost corner side, output window in the bottom and an ash coloured space for the program to be written. 5. Now to start using the keil, click on the option project. 6. A small window opens showing the options like new project, import project, open project etc. Click on New project. 7. A small window with the title bar Create new project opens. The window asks the user to give the project name with which it should be created and the destination location. The project can be created in any of the drives available. You can create a new folder and then a new file or can create directly a new file. 8. After the file is saved in the given destination location, a window opens where a list of vendors will be displayed and you have to select the device for the target you have created.
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` 9.
The most widely used vendor is Atmel. So click on Atmel and now the family of microcontrollers manufactured by Atmel opens. You can select any one of the microcontrollers according to the requirement.
10.
When you click on any one of the microcontrollers, the features of that particular microcontroller will be displayed on the right side of the page. The most appropriate microcontroller with which most of the projects can be implemented is the AT89S52. Click on this microcontroller and have a look at its features. Now click on OK to select this microcontroller.
11. A small window opens asking whether to copy the startup code into the file you have created just now. Just click on No to proceed further. 12. Now you can see the TARGET and SOURCE GROUP created in the project workspace. 13. Now click on File and in that New. A new page opens and you can start writing program in it.
14.
After the program is completed, save it with any name but with the .asm or .c extension. Save the program in the file you have created earlier.
15. You can notice that after you save the program, the predefined keywords will be highlighted in bold letters. 16. Now add this file to the target by giving a right click on the source group. A list of options open and in that select Add files to the source group. Check for this file where you have saved and add it. 17. Right click on the target and select the first option Options for target. A window opens with different options like device, target, output etc. First click on target. 18. Since the set frequency of the microcontroller is 11.0592 MHz to interface with the PC, just enter this frequency value in the Xtal (MHz) text area and put a tick on the Use on-chip ROM. This is because the program what we write here in the keil will later be dumped into the microcontroller and will be stored in the inbuilt ROM in the microcontroller. 19. Now click the option Output and give any name to the hex file to be created in the Name of executable text area and put a tick to the Create HEX file option present in the same window. The hex file can be created in any of the drives. You can change the folder by clicking on Select folder for Objects.
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20. Now to check whether the program you have written is errorless or not, click on the icon exactly below the Open file icon which is nothing but Build Target icon. You can even use the shortcut key F7 to compile the program written. 21. To check for the output, there are several windows like serial window, memory window, project window etc. Depending on the program you have written, select the appropriate window to see the output by entering into debug mode. 22. The icon with the letter d indicates the debug mode. 23. Click on this icon and now click on the option View and select the appropriate window to check for the output. 24. After this is done, click the icon debug again to come out of the debug mode. 25. The hex file created as shown earlier will be dumped into the microcontroller with the help of another software called Proload.
7.3 PROLOAD: Proload is a software which accepts only hex files. Once the machine code is converted into hex code, that hex code has to be dumped into the microcontroller placed in the programmer kit and this is done by the Proload. Programmer kit contains a microcontroller on it other than the one which is to be programmed. This microcontroller has a program in it written in such a way that it accepts the hex file from the keil compiler and dumps this hex file into the microcontroller which is to be programmed. As this programmer kit requires power supply to be operated, this power supply is given from the power supply circuit designed above. It should be noted that this programmer kit contains a power supply section in the board itself but in order to switch on that power supply, a source is required. Thus this is accomplished from the power supply board with an output of 12volts or from an adapter connected to 230 V AC. 1. Install the Proload Software in the PC. 2. Now connect the Programmer kit to the PC (CPU) through serial cable. 3. Power up the programmer kit from the ac supply through adapter. 4. Now place the microcontroller in the GIF socket provided in the programmer kit.
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5. Click on the Proload icon in the PC. A window appears providing the information like Hardware model, com port, device type, Flash size etc. Click on browse option to select the hex file to be dumped into the microcontroller and then click on Auto program to program the microcontroller with that particular hex file. 6. The status of the microcontroller can be seen in the small status window in the bottom of the page.After this process is completed, remove the microcontroller from the programmer kit and place it in your system board. Now the system board behaves according to the program written in the microcontroller.
7.4 Advantages:
1. Sophisticated security 2. Monitors all hazards and threats 3. Alerts whenever the units are nearing to zero units 4. Can be recharged at any time.
7.5 Applications:
1. Banks 2. Offices 3. Industries 4. Jeweler Shops and Home Applications
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RESULT
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RESULT
By using our project we can reduce the electricity bill, it can be paid now through E-Seva centers,ATMs,Net-banking and even through mobile phones . But prepaid electricity is a unique and new concept which saves lot of time and a power for electricity department. At every instant units values are stored in EEPROM .So that no data loss even in power failure cases.
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CONCLUSION
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CONCLUSION
This project presents a Prepaid Energy Meter using 89S52. The Energy consumption calculation based on the counting of pulses is designed and implemented with Atmel 89S52 MCU in embedded system domain. Set up on the Energy tracking system, the counting of pulses is used to determine the energy consumption. The proposed Energy Meter is used can track the energy consumption automatically. Thus, the efficiency of Energy Meter Calculation can be increased. Experimental work has been carried out carefully. The result shows that higher efficiency is indeed achieved using the embedded system. The proposed method is verified to be highly beneficial for the Domestic purpose.
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REFERENCES
REFERENCES
1. 2. 3.
Embedded and real time projects system by Dr.kvk.prasad ,Black book Embedded System By Raj Kamal fourth edition 8052 Microcontroller And Embedded Systems By Ali Mazzidi
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4. 8051 micro controller by Ak.ayala second edition 5. micro processor and interfacing by A.k.ray fourth edition 6. micro controllers and assembly language by dougles .Vhall forth edition
7. 8. 9.
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APPENDIX
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Features
Compatible with MCS-51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory
4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag
Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
Rev. 1919A-07/01
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Pin Configurations
PDIP
(T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 P1.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
PLCC
P1.1 (T2 EX) P1.0 (T2) P1.4 P1.2 P1.3 NC P0.0 (AD0) (AD2) P0.1 (AD1) (AD3) P0.2 P0.3
VCC
(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
(WR) P3.6 XTAL1 C(A8) P2.0 (A11) P2.3 (RD) P3.7 GND XTAL2 N (A9) P2.1 P2.2 P2.4 (A10) (A12)
TQFP
P1.1 (T2 EX) P1.0 (T2) P1.4 P1.2 P1.3 NC P0.0 (AD0) (AD2) P0.1 (AD1) (AD3) P0.2 P0.3
VCC
44 43 42 41 40 39 38 37 36 35 34 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (WR) P3.6 XTAL1 ND (A9) P2.1 P2.2 P2.4 (RD) P3.7 GND (A8) P2.0 (A11) P2.3 XTAL2 G (A10) (A12) 33 32 31 30 29 28 27 26 25 24 23 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
AT89S52
90
AT89S52
`
Block Diagram
P0.0 - P0.7 P2.0 - P2.7
RAM
PORT 0 LATCH
PORT 2 LATCH
FLASH
B REGISTER
ACC
STACK POINTER
PC INCREMENTER
PSW
PROGRAM COUNTER
PSEN ALE/PROG EA / V
PP
INSTRUCTION REGISTER
DUAL DPTR
PROGRAM LOGIC
P3.0 - P3.7
P1.0 - P1.7
91
Pin Description
VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I ) because of the internal pullups. IL In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin P1.0 P1.1 P1.5 P1.6 P1.7 Alternate Functions T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control) MOSI (used for In-System Programming) MISO (used for In-System Programming) SCK (used for In-System Programming)
external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I ILbecause of the pullups. ) Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.
Port Pin P3. 0 P3. 1 P3. 2 P3. 3 P3. 4 P3. 5 P3. 6 P3. 7 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe)
RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I ) because of the internal pullups. IL Port 2 emits the high-order address byte during fetches from external program memory and during accesses to 4
AT89S52
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AT89S52
` weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Table 1. AT89S52 SFR Map and Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00 000000 DP0L 00 000000 TL1 00000000 DP0H 00000000 TH0 0000000 0 DP1L 0000000 0 TH1 00000000 DP1H 00000000 AUXR XXX00XX0 PCON 87H 0XXX0000 SBUF XXXXXXXX AUXR1 XXXXXXX0 WDTRST XXXXXXXX PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00 000000 RCAP2H 00000000 TL2 0000000 0 TH2 00000000 ACC 00000000 B 00000000 0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V CC for internal program executions. This pin also receives the 12-volt programming enable voltage (V PP ) during Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier.
93
new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 1. or TCLK = Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must beby software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). cleared Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Modes Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Modes 1 and Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/Stop control for Timer 2. TR2 = 1 starts the timer. Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
AT89S52
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AT89S52
` Table 3a. AUXR: Auxiliary Register
AUXR Address = 8EH Not Bit Addressable Bit 7 6 5 WDIDLE 4 DISRTO 3 2 1 DISALE 0 Reset Value = XXX00XX0B
DISALE
Reserved for future expansion Disable/Enable ALE DISALE 0 1 Operating Mode ALE is emitted at a constant rate of 1/6 the oscillator frequency ALE is active only during a MOVX or MOVC instruction
DISRTO
Disable/Enable Reset out DISRTO 0 1 Reset pin is driven High after WDT times out Reset pin is input only
WDIDLE
Disable/Enable WDT in IDLE mode WDIDLE 0 1 WDT continues to count in IDLE mode WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the Table 3b. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Not Bit Addressable Bit 7 6 5 4
appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1 during power up. It can be set and rest under software control and is not affected by reset.
DPS 0
DPS
Reserved for future expansion Data Pointer Register Select DPS 0 1 Selects DPTR Registers DP0L, DP0H Selects DPTR Registers DP1L, DP1H
95
Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to V CC , program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
AT89S52
96
AT89S52
`
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
UART
The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select Products, then 8051-Architecture Flash Microcontroller, then Product Overview.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select Products, then 8051-Architecture Flash Microcontroller, then Product Overview.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. Table 3. Timer 2 Operating Modes
RCLK +TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 MODE 16-bit Auto-reload 16-bit Capture Baud Rate Generator (Off)
97
` In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. Figure 5. Timer in Capture Mode
OSC 12 C/T2 = 0
TH2 CONTROL
TL2
TF2 OVERFLOW
TR2
EXEN2
Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 6. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
10
AT89S52
98
AT89S52
` Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
OSC 12 C/T2 = 0 TH2 CONTROL TR2 C/T2 = 1 T2 PIN RCAP2H RCAP2L TF2 TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 EXF2 RELOAD TIMER 2 INTERRUPT TL2 OVERFLOW
11
99
OSC
12
OVERFLOW C/T2 = 0 TH2 CONTROL TR2 C/T2 = 1 TIMER 2 INTERRUPT RCAP2H RCAP2L TL2 TF2
2
"0" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 "1" SMOD1
OSC
"1"
16
"1" "0" TCLK
T2 PIN RCAP2H TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 EXF2 TIMER 2 INTERRUPT RCAP2L
16
Tx CLOCK
12
AT89S52
100
AT89S52
`
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
TR2
RCAP2H
P1.0 (T2)
EXF2
EXEN2
13
101
Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.
Symbol EA
Position IE.7
Function Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit.
Clock-Out Frequency
ET2
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
Interrupts
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
User software should never write 1s to unimplemented bits, because they may be used in future AT89 products.
0 INT0 1 IE0
TF0
0 INT1 1 IE1
14
AT89S52
102
AT89S52
`
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 12. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
active long enough to allow the oscillator to restart and stabilize. Figure 11. Oscillator Connections
C2 XTAL2
C1 XTAL1
Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
GND
Note:
NC
XTAL2
XTAL1
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V restored to its normal operating level and must be held
GND
CC
is
15
103
3 4
P P
P P
U P
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.
Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89S52 features Data Polling to indicate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (100H) = 52H indicates 89S52 (200H) = 06H Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns - 500 ns. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output.
16
AT89S52
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AT89S52
` frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz. appropriate Write instruction. The write cycle is selftimed and typically takes less than 1 ms at 5V. 4. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6. 5. At the end of a programming session, RST can be set low to commence normal device operation. Power-off sequence (if needed): Set XTAL1 to L (if a crystal is not used). Set RST to L. Turn V CC power off. Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during a write cycle an attempted read of the last byte written will result in the complement of the MSB of the serial output byte on MISO.
17
105
AT89S52
`
Flash Programming and Verification Characteristics (Parallel Mode) ProgrammingVInterfaceto5.5V Parallel Mode T = 20C to 30C, = 4.5
Every code byte in the Flash array can be programmed by Symbol Parameter using the appropriate combination of control signals. The write operation cycle is Programming Supply Voltage self-timed and once initiated, will VPP automatically time itself to completion. IPP Programming Supply Current Table 8. Flash Programming Modes
ICC VCC Supply Current 1/t CLCL
Mode VCC 5V
A CC
All major programming vendors offer worldwide support for Min Max Units the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. 11.5 12.5 V
10 30
P0. 7-0 33 Data
IN
mA
P2.4-0
mA
tAVGL
Write Code Data
Oscillator Frequency ALE/ RST PSEN PROG Address Hold After PROG
H L
P2. 6 L L H H H
P2. 7
P3. 3
P3. 6
48 tCLCL 48 tCLCL
P3.7
MHz
P1.7-0
tGHAX
HHHH D L H H L L H H H
A7-0 A7-0 X
H 48t CLCL
H H L L
DOUT X X X
12V
PP (3)
48 tCLCL H 48 tCLCL
L
tSHGL tGHSL
12V
(3)
10 10
s X s s
X
12V
tGLGH
Read Lock Bits tAVQV 1, 2, 3
PROG Width
5V Address to Data Valid H L H
(1)
0.2
H H H L H L
1
P0.2, 48t P0.3,CLCL P0.4 X
tELQV
48t CLCL
X X 0000 X 0001 X 0010 X
4 8tCLCL X 1.0
s 00H
00H
50
Read 5V H L H LLLLL00H 06H FigureDeviceFlash Programming and VerificationHWaveforms Parallel Mode 15. ID
Each PROG pulse is 200 ns - 500 ns for Chip Erase. Each PROG pulse is 200 ns - 500 ns for Write Code Data. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. RDY/BSY signal is output on P3.0 during programming. X = dont care. tDVGL
tAVQV
AT89S52
AT89S52
ADDR. 0000H/1FFFH A0 - A7 A8 - A12 SEE FLASH PROGRAMMING MODES TABLE P1.0-P1.7 P2.0 - P2.4 P2.6 P2.7 P3.3 P3.6 P3.7 XTAL2
VCC P0
tSHGL
PGM DATA PROG
tGLGH
A0 - A7 A8 - A12
ALE
ALE VIH EA
EA
V/V IH
PP
3-33 MHz 3-33 MHz P3.0 RDY/ BSY XTAL1 XTAL1 GND RST PSEN VIH GND RST PSEN VIH
18
AT89S52
106
19
AT89S52
VCC
XTAL2
3-33 MHz
XTAL1 GND
RST
VIH
20
AT89S52
107
AT89S52
` Table 9. Serial Programming Instruction Set
Instruction Format Instruction Programming Enable Byte 1 1010 1100 Byte 2 0101 00 11 Byte 3 xxxx xxxx Byte 4 xxxx xxxx 0110 1001 (Output) xxxx xxxx
D7 6 5 4 D3 D1 DD D D2 D0 D7 6 5 4 D3 D1 0 DDD D2 D
Operation Enable Serial Programming while RST is high Chip Erase Flash memory array Read data from Program memory in the byte mode Write data to Program memory in the byte mode Write Lock bits. See Note (2). Read back current status of the lock bits (a programmed lock bit reads back as a 1) Read Signature Byte Read data from Program memory in the Page Mode (256 bytes) Write data to Program memory in the Page Mode (256 bytes)
Chip Erase Read Program Memory (Byte Mode) Write Program Memory (Byte Mode) Write Lock Bits (2) Read Lock Bits
xxxx xxxx
A AA A A A A7 6 5 4A3 2 1 0 A A A A A1 A7 6 5 4A3 2 A0
00 10 01 00
xxxx xxxx
Read Signature Bytes Read Program Memory (Page Mode) Write Program Memory (Page Mode) Notes:
(1)
0010 0011
1000 0000
Signature Byte Byte 1... Byte 255 Byte 1... Byte 255
0101
0000
Byte 0
1. The signature bytes are not readable in Lock Bit Modes 3 and 4. 2. B1 = 0, B2 = 0 ---> Mode 1, no lock protection Each of the lock bits needs to be activated sequentially before B1 = 0, B2 = 1 ---> Mode 2, lock bit 1 activated Mode 4 can be executed. B1 = 1, B2 = 0 ---> Mode 3, lock bit 2 activated B1 = 1, B1 = 1 ---> Mode 4, lock bit 3 activated
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded.
21
108
tSHOX tSHSL
tSLSH
22
AT89S52
109
AT89S52
`
DC Characteristics
The values shown in this table are valid for T = -40C to 85C and V A
Symbol VIL VIL1 VIH VIH1 VOL VOL1 Parameter Input Low Voltage I n p V o l Input High Voltage ( E A Input High Voltage Output Low Voltage Output Low Voltage (Port 0, ALE, PSEN)
(1) (1)
CC
Condition ( u t ) t a E x c e
(Ports 1,2,3)
VOH
VOH1
Output High Voltage (Port 0 in External Bus Mode) Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pulldown Resistor Pin Capacitance Power Supply Current Power-down Mode
(1)
Test Freq. = 1 MHz, T = 25C A Active Mode, 12 MHz Idle Mode, 12 MHz VCC = 5.5V
ICC
Notes:
1. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum I OL per port pin: 10 mA Maximum I OL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total I OL for all output pins: 71 mA If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum V CC for Power-down is 2V.
23
110