Application Specific Integrated Circuits

Application Specific Integrated Circuits
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ABSTRACT
An Application Specific Integrated Circuit or ASIC in common language is a custom chip designed for you and your products alone. An ASIC has all the advantages of integrating your own design into a single IC. These include low power requirements, reliability (smaller PCB, reduced number of discrete components and joints), design security, more economic and reduced size. ASICs may be classified into Full-Custom, standard cell, gate array, PLD and FPGA. FPGAs are the newest member of the ASIC family and are rapidly growing in importance, replacing TTL in microelectronic systems. The steps involved in the design of ASICs are: design entry, logic synthesis, system partitioning, pre layout simulation, floor planning, placement, routing, extraction and post layout simulation. The purpose of design entry is to describe a microelectronic system to a set of electronic-design automation (EDA) tools. Design entry for systems may be low level or high level. The low-level design entry uses Schematic capture. High-level design entry is done with Hardware Description Languages (HDL). Two standard HDLs are VHDL and Verilog.
Perhaps, the most important phase is that of simulation; it can uncover errors before they are set in silicon. Behavioral simulation, functional simulation and static timing analysis are some of the modes of simulation. Testing is also an important phase of ASIC design. System partitioning, floor planning, placement and routing form the
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physical part of ASIC design. This paper describes the architecture and introduces the steps involved in the design of an ASIC.
1. INTRODUCTION 1.1WHAT IS AN ASIC? An Application Specific Integrated Circuit or ASIC in common language is a custom chip designed for you and your products alone. It is a chip that can be designed by an engineer with no particular knowledge of semiconductor physics or semiconductor processes. The ASIC vendor has created a library of cells and functions that the designer can use. Customers implement their designs in a single silicon die by mapping their functions to these sets of pre-designed library of cells. ASICs are used in a wide variety of products ranging from consumer products such as video games, digital cameras, automobiles and personal computers, to high and technology products such as workstations and supercomputers. An ASIC has all the advantages of integrating your own design into a single IC. These include low power requirements, reliability (smaller PCB, reduced number of discrete components and joints), design security, more economic and reduced size.
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CLASSIFICATION OF ASICs: Full-Custom ASICs: In a full-custom ASIC an engineer designs some or all of the logic cells, circuits, or layout specifically for one ASIC. This means the designer abandons the approach of using pre-tested and pre-characterized cells for all or part of that design. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design. This might be because existing cell libraries are not fast enough, or the logic cells are not small enough or consume too much power. Fewer and fewer full-custom ICs are being designed because of the problems with these special parts of the ASIC. A microprocessor is an example of a full-custom IC. The manufacturing lead time (the time it takes just to make an ICnot including design time) is typically eight weeks for a full-custom IC. Standard-CellBased ASICs: A cell-based ASIC (cell-based IC, or CBIC) uses predesigned logic cells (AND gates, OR gates, multiplexers, and flip-flops, for example) known as standard cells. The standard-cell areas (also called flexible blocks) in a CBIC are built of rows of standard cells. The standard-cell areas may be used in combination with larger predesigned cells, perhaps micro controllers or even microprocessors, known as mega cells. The ASIC designer defines
only the placement of the standard cells and the interconnect in a CBIC. However, the standard cells can be placed anywhere on the silicon.
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The advantage of CBICs is that designers save time, money, and reduce risk by using a predesigned, pretested, and precharacterized standard-cell library. In addition each standard cell can be optimized individually. Gate-ArrayBased ASICs: In a gate array or gate-arraybased ASIC the transistors are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the base array, and the smallest element that is replicated to make the base array is the base or primitive cell. Only the top few layers of metal, which define the interconnect between transistors, are defined by the designer using custom masks. The designer chooses from a gate-array library of predesigned and precharacterized logic cells. The logic cells in a gate-array library are often called macros. A channeled gate array contains rows of cells separated by channels used for interconnect whereas a channel less gate array has no predefined areas set aside for routing between cells. Instead we route over the top of the gate-array devices. In an embedded gate array we set aside some of the IC area and dedicate it to a specific function (for example, micro-controller).
Programmable Logic Devices: The simplest type of programmable IC is a read-only memory (ROM). The most common types of ROM use a metal fuse that can be blown permanently (a programmable ROM or PROM). By using the programmable devices in a large array of AND gates and an array of OR gates, we create a family of flexible and programmable logic devices called logic arrays. A logic array can be placed as a cell on a custom ASIC. This type of logic array is called
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a programmable logic array (PLA). There is a difference between a PAL and a PLA: a PLA has a programmable AND logic array, followed by a programmable OR logic array; a PAL has a programmable AND plane and, in contrast to a PLA, a fixed OR plane. Field-Programmable Gate Arrays: A step above the PLD in complexity is the field-programmable gate array (FPGA). There is very little difference between an FPGA and a PLDan FPGA is usually just larger and more complex than a PLD. In fact, some companies that manufacture programmable ASICs call their products FPGAs and some call them complex PLDs. FPGAs are the newest member of the ASIC family and are rapidly growing in importance, replacing TTL in microelectronic systems. Essential characteristics are: A method for programming the basic logic cells and the interconnect.
The core is a regular array of programmable basic logic cells that can implement combinational as well as sequential logic (flip-flops). A matrix of programmable interconnects surrounds the basic logic cells.
DESIGN FLOW: The sequence of steps to the designer an ASIC we call this a design flow. Design entry. Enter the design into an ASIC design system, either using a hardware description language (HDL) or schematic entry. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a net list a description of the logic cells and their connections. System partitioning. Divide a large system into ASIC-sized pieces.
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Prelayout simulation. Check to see if the design functions correctly. Floor planning. Arrange the blocks of the net list on the chip. Placement. Decide the locations of cells in a block. Routing. Make the connections between cells and blocks. Extraction. Determine the resistance and capacitance of the interconnect.
Post layout simulation. Check to see the design still works with the added loads of the interconnect.
ASIC Cell Libraries: The cell library is the key part of ASIC design. Each cell in an ASIC cell library must contain the following: A physical layout A behavioral model A Verilog/VHDL model A detailed timing model A test strategy A circuit schematic A cell icon A wire-load model A routing model
The ASIC designer needs a high-level, behavioral model for each cell because simulation at the detailed timing level takes too long for a complete ASIC design. The designer may require Verilog and VHDL models in addition to
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the models for a particular logic simulator. ASIC designers also need a detailed timing model for each cell to determine the performance of the critical pieces of an ASIC. It is too difficult, too time-consuming, and too expensive to build every cell in silicon and measure the cell delays. Instead library engineers simulate the delay of each cell, a process known as characterization. The cell schematic (a net list description) describes each cell so that the cell designer can perform simulation for complex cells. If the ASIC designer uses schematic entry, each cell needs a cell icon together with connector and naming information that can be used by design tools from different vendors. We also need a routing model for each cell.
2. LOGIC CELLS: ASICs are manufactured widely using CMOS technology mainly due to its low power consumption.
2.1
COMBINATIONAL LOGIC CELLS: The AND-OR-INVERT (AOI) and the OR-AND-INVERT (OAI) logic
cells are particularly efficient in CMOS. For example we can use an AOI221 and an OAI321 logic cell All indices (the indices are the numbers after AOI or OAI) in the logic cell name greater than 1 correspond to the inputs to the first level or stage. An index of '1' corresponds to a direct input to the second-stage cell.
2.2 SEQUENTIAL LOGIC CELLS: The advantages of synchronous design usually outweigh every other consideration in the choice of a clocking scheme. The vast majority of ASICs use
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a rigid synchronous design style. The latch and flip flop implementation in CMOS can be done.
2.3 DATAPATH LOGIC CELLS: To build an n -bit adder (that adds two n -bit numbers) and to exploit the regularity of this function in the layout, a data path structure can be used. The following two functions, SUM and COUT, implement the sum and carry out for a full adder with two data inputs (A, B) and a carry in, CIN: SUM = SUM (A, B, CIN) = PARITY (A, B, CIN) COUT = A B + A CIN + B CIN = MAJ (A, B, CIN). The sum uses the parity function ('1' if there are an odd numbers of '1's in the inputs). The carry out, COUT, uses the 2-of-3-majority function ('1' if the majority of the inputs are '1'). This principle is used to implement the ripple carry adder (RCA). The data path structures can be used to implement similar logic circuits.
3. PROGRAMMABLE ASIC Programmable ASIC is also called field programmable gate array or FPGA it is most widely used one of the programmable device. Programmable devices are a class of general purpose chips that can be configured for a wide variety of applications. There are five components of a programmable ASIC or FPGA: (1) the programming technology, (2) the basic logic cell, (3) the I/O cell, (4) the interconnect, and (5) the design software that allows you to program the ASIC.
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The design software is much more closely tied to the FPGA architecture than is the case for other types of ASICs. Interconnect resources
Fig. The FPGA
3.1
PROGRAMMING TECHNOLOGY:
FPGAs: There are two types of programmable ASICs: programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs). An FPGA is a chip that a systems designer can program. An IC foundry produces FPGAs with some connections missing. You perform design entry and simulation. Next, special software creates a string of bits describing the extra connections required -the configuration file. Then connect a computer to the chip and program the chip to make the necessary connections according to the configuration file. The Antifuse: An antifuse is the opposite of a regular fusean antifuse is normally an open circuit until you force a programming current through it (about 5 mA). In a
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polydiffusion antifuse the high current density causes large power dissipation in a small area, which melts a thin insulating dielectric between polysilicon and diffusion electrodes and forms a thin (about 20 nm in diameter), permanent, and resistive silicon link. The programming process also drives dopant atoms from the poly and diffusion electrodes into the link, and the final level of doping determines the resistance value of the link. The Static RAM: In static RAM FPGA programmable connections are made using pass transistors, transmission gates or multiplexers that can be controlled by SRAM cells. The advantage of this technology is that it allows fast in circuit
reconfiguration. The major disadvantage is the size of the chip required by RAM technology. EPROM/EEPROM technology This method is same as used in EPROM memories. One advantage of this technology is that it can be reprogram without external storage of configuration; through the EPROM transistors cannot be reprogram in circuit.
3.2
THE BASIC LOGIC CELL All programmable ASICs or FPGAs contain a basic logic cell replicated
in a regular array across the chip (analogous to a base cell in an MGA). There are the following three different types of basic logic cells: (1) multiplexer based, (2) look-up table based, and (3) programmable array logic. MUX based logic cell:
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A 2:1 MUX can be used to implement different logical functions of which the following six are useful:
INV. The MUX acts as an inverter for one input only. BUF. The MUX just passes one of the MUX inputs directly to the output. AND. A two-input AND. OR. A two-input OR. AND1-1. A two-input AND gate with inverted input, equivalent to an NOR-11: (A . B)
NOR1-1. A two-input NOR gate with inverted input, equivalent to an AND-11: (A + B).
3.3
THE I/O CELL: All programmable ASICs contain some type of input/output cell (I/O
cell). These I/O cells handle driving logic signals off-chip, receiving and conditioning external inputs, as well as handling such things as electrostatic protection. The following are different types of I/O requirements: DC output. Driving a resistive load at DC or low frequency (less than 1 MHz). AC output. Driving a capacitive load with a high-speed (greater than 1 MHz) logic signal off-chip. Example loads are other logic chips, a data or address bus, ribbon cable. DC input. Example sources are a switch, sensor, or another logic chip. The digital value of the input should be correctly interpreted. AC input. Example sources are high-speed logic signals (higher than 1
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MHz) from another chip. Fast enough interpretation. Clock input. Examples are system clocks or signals on a synchronous bus. The transfer the timing information should be appropriate. Power input. Required to supply power to the I/O cells and the logic in the core, without introducing voltage drops or noise. I/O cells are designed so as to satisfy above conditions. Choices are to be made among totem pole configuration, bus transceivers, use of pull-up/down resistors, buffers (drivers), etc. depending on the requirements for the ASIC.
3.4
THE INTERCONNECT All FPGAs contain some type of programmable interconnect. The
structure and complexity of the interconnect is largely determined by the programming technology and the architecture of the basic logic cell. The raw material that we have to work with in building the interconnect is aluminumbased metallization. Usually three layers are used. Horizontal and vertical lines run over the logic cells to obtain the required interconnections.
3.5
THE DESIGN SOFTWARE Schematic entry is one method of design entry for FPGAs. A solution to
some of the problems with schematic entry for FPGA design is to use one of several hardware description languages (HDL s) for which there are some standards. After completing design entry and generating a net list, the next step is simulation. Logic Synthesis: The term logic synthesis is used to cover a broad range of software and
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software capabilities. Many logic synthesizers are based on logic minimization.
4. DESIGN ENTRY The purpose of design entry is to describe a microelectronic system to a set of electronic-design automation (EDA) tools. Design entry for systems may be low level or high level. The low-level design entry uses Schematic capture. High-level design entry is done with Hardware Description Languages (HDL). Two standard HDLs are VHDL and Verilog.
4.1 SCHEMATIC CAPTURE: Design entry in the low-level usually consists of drawing a picture, a schematic. The schematic consists of symbols representing the basic units of the design connected together with signals, the connectivity of an ASIC. This type of design-entry process is called schematic entry or schematic capture. The symbols used come from a library of parts that the designer uses to build the schematic. The output of a schematic-entry tool is a net list file that contains a description of all the components in a design and their interconnections.
4.2 VHDL: VHDL (VHSIC hardware description language) was developed as part of the VHSIC (very high-speed IC) program in the early 1980s. VHDL has been standardised as the documentation, simulation, and verification medium for ASICs.
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VHDL is a HDL with strong emphasis on concurrency. The language supports hierarchical description of hardware from system to gate or even switch level. Some of the basic building blocks of VHDL are entity, architecture, configuration, package, attribute and process. The entity declaration specifies its interface; architecture describes the operation by its structure or by behaviour. Subprograms are grouped by use of packages. Configurations are used to customize descriptions.
All hardware components have a timing associated with it and with the events in the circuit. Accurate modeling of concurrency is possible. Sequential assignments are done sequentially. The timing delays are also described in VHDL. Default delays are called Inertial delays. A transport delay is that due to passage through wire (usually for delay lines). VHDL also allows definition and use of functions and procedures generally called Subprograms. Operators: a <= b - for assigning signals
a : = b assigns variables of type integer, boolean, etc. +, -, *, / - Arithmetic AND, OR logical An example of a VHDL description for an invertor is as shown.
ENTITY inv IS PORT (i1 : IN BIT; o1 : OUT BIT); END inv;
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ARCHITECTURE single_delay OF inv IS BEGIN o1 <= NOT i1 AFTER 4 NS; END single_delay;
4.3
VERILOG HDL: Gateway Design Automation developed Verilog as a simulation
language. Verilog is a fairly simple language to learn and very much similar to the C programming language. Operators: ?: || && |, ~| - conditional - logical OR
- logical AND - bitwise OR, NOR
= =, != - logical <, <=, >, >= - lt, lt or equal, gt, gt or equal >>, << +, -, *, /, % - shift - arithmetic
The code shows Verilog syntax for modeling 3 NAND gates as shown. module primitive; nand (strong0, strong1) #2.2 Nand_1(n001, n004, n005), Nand_2(n003, n001, n005, n002); nand (n006, n005, n002);
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endmodule
4.4
LOGIC SYNTHESIS: Logic synthesis provides a link between an HDL (Verilog or VHDL) and
a net list. Once a behavioral HDL model is complete, two items are required to proceed: a logic synthesizer (software and documentation) and a cell library (the logic cellsNAND gates and such) that is called the target library. The behavioral model is simulated to check that the design meets the specifications and then the logic synthesizer is used to generate a net list, a structural model, which contains only references to logic cells. The net list is then passed to software that maps the net list to FPGA architecture. There is no standard format for the net lists that logic synthesis produces.
5. SIMULATION Perhaps, the most important phase is that of simulation; it can uncover errors before they are set in silicon. Simulators are usually divided into the following categories or simulation modes: Behavioral simulation Functional simulation Static timing analysis Gate-level simulation Switch-level simulation Transistor-level or circuit-level simulation
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This list is ordered from high-level to low-level simulation. Proceeding from high-level to low-level simulation, the simulations become more accurate, but they also become progressively more complex and take longer to run.
5.1
TYPES OF SIMULATION: There are several ways to create an imaginary simulation model of a
system. One method models large pieces of a system as black boxes with inputs and outputs. This type of simulation (often using VHDL or Verilog) is called behavioral simulation. Functional simulation ignores timing and includes unitdelay simulation, which sets delays to a fixed value (for example, 1 ns). Once a behavioral or functional simulation predicts that a system works correctly, the next step is to check the timing performance. At this point a system is partitioned into ASICs and a timing simulation is performed for each ASIC separately (otherwise the simulation run times become too long). One class of timing simulators employs timing analysis that analyzes logic in a static manner, computing the delay times for each path. This is called static timing analysis because it does not require the creation of a set of test (or stimulus) vectors (an enormous job for a large ASIC). Timing analysis works best with synchronous systems whose maximum operating frequency is determined by the longest path delay between successive flip-flops. The path with the longest delay is the critical path. Logic simulation or gate-level simulation can also be used to check the timing performance of an ASIC. In a gate-level simulator, a logic gate or logic
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cell is treated as a black box modeled by a function whose variables are the input signals. The function may also model the delay through the logic cell. Setting all the delays to unit value is the equivalent of functional simulation. If the timing simulation provided by a black-box model of a logic gate is not accurate enough, the next, more detailed, level of simulation is switch-level simulation which models transistors as switcheson or off. Switch-level simulation can provide more accurate timing predictions than gate-level simulation, but without the ability to use logic-cell delays as parameters of the models. The most accurate, but also the most complex and time-consuming, form of simulation is transistorlevel simulation.
6. TEST ASICs are tested at two stages during manufacture using production tests. First, the silicon die is tested after fabrication is complete at wafer test. A second, final test is carried out on the packaged ASIC (usually with the same test vectors used at wafer sort) before the ASIC is shipped to the customer.
6.1. SCAN TECHNIQUES: They are of two types: Boundary-scan test (BST) is a method for testing boards using a fourwire interface. The BST interface provides a standard means of communicating with test circuits on-board an ASIC. This is an example of increasing the cost and
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complexity (as well as potentially reducing the performance) of an ASIC to reduce the cost of testing the ASIC and the system. In order to include BST on an ASIC, we add a special logic cell to each ASIC I/O pad. These cells are joined together to form a chain and create a boundary-scan shift register that extends around each ASIC. The input to a boundary-scan shift register is the test-data input (TDI). The output of a boundary-scan shift register is the test-data output (TDO). These boundary-scan shift registers are then linked in a serial fashion with the boundary-scan shift registers on other ASICs to form one long boundary-scan shift register. The boundary-scan shift register in each ASIC is one of several test-data registers (TDR) that may be included in each ASIC. All the TDRs in an ASIC are connected directly between the TDI and TDO ports. A special register that decodes instructions provides a way to select a particular TDR and control operation of the boundary-scan test process. Controlling all of the operations involved in selecting registers, loading data, performing a test, and shifting out results are the test clock (TCK) and test-mode select (TMS). The boundary-scan standard specifies a four-wire test interface using the four signals: TDI, TDO, TCK, and TMS. These four dedicated signals, the testaccess port (TAP), are connected to the TAP controller inside each ASIC. The TAP controller is a state machine clocked on the rising edge of TCK, and with state transitions controlled by the TMS signal. The test-reset input signal (TRST) is an optional (fifth) dedicated interface pin to reset the TAP controller. Normally the boundary-scan shift-register cells at each ASIC I/O pad are transparent, allowing signals to pass between the I/O pad and the core logic. When an ASIC is put into boundary-scan test mode, we first tell the TAP
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controller which TDR to select. The TAP controller then tells each boundaryscan shift register in the appropriate TDR either to capture input data, to shift data to the neighboring cell, or to output data. In Full-scan design, each sequential element is replaced with a scan flipflop. This results in an internal form of boundary scan.
6.2 FAULTS: Fabrication of an ASIC is a complicated process requiring hundreds of processing steps. Problems may introduce a defect that in turn may introduce a fault. Any problem during fabrication may prevent a transistor from working and may break or join interconnections. Two common types of defects occur in metallization: either under-etching the metal (a problem between long, closely spaced lines), which results in a bridge or short circuit (shorts) between adjacent lines, or over-etching the metal and causing breaks or open circuits (opens). Defects may also arise after chip fabrication is completewhile testing the wafer, cutting the die from the wafer, or mounting the die in a package. Fault Simulation: Fault simulation is used after logic simulation is completed to see what happens in a design when we deliberately introduce faults. In a production test we only have access to the package pinsthe primary inputs (PIs) and primary outputs (POs). To test an ASIC we must devise a series of sets of input patterns that will detect any faults. A stimulus is the application of one such set of inputs (a test vector) to the PIs of an ASIC. A typical ASIC may have several hundred PIs and therefore each test vector is several hundred bits long. A test program consists of a set of test vectors.
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As each fault is inserted, the fault simulator runs the test program. If the fault simulation shows that the POs of the faulty circuit are different than the PIs of the good circuit at any strobe time, then we have a detected fault; otherwise we have an undetected fault. Fault coverage = detected faults / detectable faults. The set of input vectors and faulty output vectors that uniquely identify a fault is the fault signature. This information can be useful to test engineers, allowing them to work backward from production test results and pinpoint the cause of a problem if several ASICs fail on the tester for the same reasons. Fault signatures are only useful in diagnosing fault locations if there is one, or a very few faults.
6.3. AUTOMATIC TEST-PATTERN GENERATION: Automatic test pattern generation (ATPG) is a method of managing fault coverage. Fault coverage refers to the percentage of faults than can be found when testing an ASIC. As ASICs become more complex, it is not often obvious how to generate tests that improve the fault coverage. ATPG software analyses the design and generates tests that allow you to increase the fault coverage with minimal effort. In order for an ATPG system to provide a test for a fault on a node it must be possible to both control and observe the behavior of the node.
6.4 BUILT-IN SELF-TEST Built-in self-test (BIST) is a set of structured-test techniques for combinational and sequential logic, memories, multipliers, and other embedded logic blocks. In each case the principle is to generate test vectors, apply them to
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the circuit under test or device under test, and then check the response. If the input sequence and the serial-input signature register (SISR) are long enough, it is unlikely (though possible) that two different input sequences will produce the same signature. If the input sequence comes from logic that we wish to test, a fault in the logic will cause the input sequence to change. This causes the signature to change from a known good value and thus the circuit under test is known to be bad. This technique is called signature analysis. There is a small probability that the signature of a bad circuit will be the same as a good circuit. This problem is known as aliasing.
7. ASIC CONSTRUCTION: The physical design of ASICs is normally divided into system partitioning; floor planning, placement and routing.
7.1 SYSTEM PARTITIONING Microelectronic systems typically consist of many functional blocks. If a functional block is too large to fit in one ASIC, it should be split, or partitioned, into pieces using goals and objectives that should be specified. There will be many objectives or constraints that are needed to take into account during partitioning. For example, certain logic cells in a system may need to be located on the same ASIC in order to avoid adding the delay of any external interconnections. Some logic cells may consume more power than others and you may need to add power constraints to avoid exceeding the powerhandling capability of a single ASIC. Certain logic cells may only be available in a certain technology. In such cases, technology constraints will keep together
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logic cells requiring similar technologies. The best CAD tool to help you with these decisions is a spreadsheet. 7.2. FLOORPLANNING AND PLACEMENT The input to the floor-planning step is the output of system partitioning and design entrya net list. Floor planning precedes placement. The output of the placement step is a set of directions for the routing tools. The input to a floor planning tool is a hierarchical net list that describes the interconnection of the blocks (RAM, ROM, ALU, cache controller, and so on); the logic cells (NAND, NOR, D flip-flop, and so on) within the blocks; and the logic cell connectors (the terms terminals, pins, or ports mean the same thing as connectors). The net list is a logical description of the ASIC; the floor plan is a physical description of an ASIC. Floor planning is thus a mapping between the logical description (the net list) and the physical description (the floor plan). The objectives of floor planning are to minimize the chip area and minimize delay Placement defines the location of the logic cells within the flexible blocks and sets aside space for the interconnect to each logic cell. Placement for a gate-array or standard-cell design assigns each logic cell to a position in a row. For an FPGA, placement chooses which of the fixed logic resources on the chip are used for which logic cells. 7.3 ROUTING: Once the designer has floor planned a chip and the logic cells within the flexible blocks have been placed, it is time to make the connections by routing the chip. Routing is usually split into global routing followed by detailed routing. Global routing determines where the interconnections between the placed
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logic cells and blocks will be situated. Only the routes to be used by the interconnections are decided in this step, not the actual locations of the interconnections within the wiring areas. Global routing is sometimes called loose routing for this reason. Local routing joins the logic cells with interconnections. Information on which interconnection areas to use comes from the global router. Only at this stage of layout do we finally decide on the width, mask layer, and exact location of the interconnections. Local routing is also known as detailed routing.
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8. CONCLUSION: Application Specific Integrated circuits is a fast growing field since the quest for technology and the need for miniaturization is never ending. This paper describes the architecture and introduces the steps involved in the design of an ASIC.

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