UNISONIC TECHNOLOGIES CO.

, LTD MJE13007
NPN BIPOLAR POWER TRANSISTOR FOR SWITCHING POWER SUPPLY APPLICATIONS
DESCRIPTION
The UTC MJE13007 is designed for highvoltage, highspeed power switching inductive circuits where fall time is critical. It is particularly suited for 115 and 220 V switch mode applications.

NPN SILICON TRANSISTOR

1 TO-220

TO-220F

FEATURES
* VCEO(SUS) 400 V * 700 V Blocking Capability *Pb-free plating product number: MJE13007L

ORDERING INFORMATION
Order Number Normal Lead Free Plating MJE13007-TA3-T MJE13007L-TA3-T MJE13007-TF3-T MJE13007L-TF3-T Package TO-220 TO-220F Pin Assignment 1 2 3 B C E B C E Packing Tube Tube

MJE13007L-TA3-T

(1)Packing Type (2)Package Type (3)Lead Plating

(1)T: Tube (2) TA3: TO-220, TF3: TO-220F (3) L: Lead Free Plating, Blank: Pb/Sn

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ABSOLUTE MAXIMUM RATING
PARAMETER Collector-Emitter Sustaining Voltage Collector-Emitter Breakdown Voltage Emitter-Base Voltage Collector Current Base Current Emitter Current Continuous Peak (1) Continuous Peak (1) Continuous SYMBOL VCEO VCBO VEBO IC ICM IB IBM IE

NPN SILICON TRANSISTOR

RATINGS 400 700 9.0 8.0 16 4.0 8.0 12

UNIT V V V A A A A A

Peak (1) IEM 24 A Total Device Dissipation TC = 25 PD 80 W Operating and Storage Junction Temperature Range TJ, TSTG -65 ~ +125 Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.

THERMAL DATA
PARAMETER SYMBOL RATINGS UNIT Thermal Resistance Junction to Case JC 1.56 /W Thermal Resistance Junction to Ambient /W 62.5 JA Note 1: Pulse Test: Pulse Width = 5.0 ms, Duty Cycle10%. Measurement made with thermocouple contacting the bottom insulated mounting surface of the package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied at a mounting torque of 6 to 8lbs.

ELECTRICAL CHARACTERISTICS (TC=25, unless otherwise noted)

PARAMETER Collector-Emitter Sustaining Voltage Collector Cutoff Current Emitter Cutoff Current DC Current Gain SYMBOL TEST CONDITIONS VCEO(SUS) IC=10mA, IB=0 VCBO=700V ICBO VCBO=700V, TC=125 IEBO VEB=9.0V, IC=0 hFE1 IC=2.0A, VCE=5.0V hFE2 IC=5.0A, VCE=5.0V IC=2.0A, IB=0.4A IC=5.0A, IB=1.0A VCE(SAT) IC=8.0A, IB=2.0A IC=5.0A, IB=1.0A, TC=100 IC=2.0A, IB=0.4A VBE(SAT) IC=5.0A, IB=1.0A IC=5.0A, IB=1.0A, TC=100 fT IC=500mA, VCE=10V, f=1.0 MHz Cob VCB=10V, IE=0, f=0.1MHz MIN 400 TYP MAX UNIT V 0.1 mA 1.0 mA 100 A 40 30 1.0 V 2.0 V 3.0 V 3.0 V 1.2 V 1.6 V 1.5 V MHz pF 0.1 1.5 3.0 0.7

8.0 5.0

Collector-Emitter Saturation Voltage

Base-Emitter Saturation Voltage

Current-Gain-Bandwidth Product Output Capacitance Resistive Load (Table 1) Delay Time tD VCC=125V, IC=5.0A, Rise Time tR IB1=IB2=1.0A, tp=25s, Storage Time tS Duty Cycle1.0% Fall Time tF * Pulse Test: Pulse Width300s, Duty Cycle2.0%

4.0

14 80 0.025 0.5 1.8 0.23

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TYPICAL THERMAL RESPONSE
1 0.7 D=0.5 0.5 D=0.2 D=0.1 0.1 0.07 D=0.05 0.05 D=0.02 0.02 D=0.01 0.2 P(pk) t1 t2 SINGLE PULSE 0.05 0.1 0.2 0.5 1 2

NPN SILICON TRANSISTOR

Figure1. Typical Thermal Response

Transient thermal resistance, r(t) (NORMALIZED)

DUTY CYCLE, D=t1/t2 5 10 20 50

RJC(t)=r(t)RJC RJC=1.56/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t 1 TJ(pk) -TC=P(pk )RJC (t) 100 200 500 10k

0.01 0.01 0.02

Time, t (msec)

There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC-VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 7 is based on TC = 25; TJ(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be debated when TC 25. Second breakdown limitations do not debate the same as thermal limitations. Allowable current at the voltages shown on Figure 7 may be found at any case temperature by using the appropriate curve on Figure 9. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. Use of reverse biased safe operating area data (Figure 8) is discussed in the applications information section.

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VCC

NPN SILICON TRANSISTOR

Table 1. Test Conditions for Dynamic Performance RESISTIVE SWITCHING
+125

REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING

TEST CIRCUITS

+15V 1F

150 3W
MPF930

100 3W

MTP8P10 MTP8P10

100F

MUR8100E

RB1 +10V
MPF930 MUR105

RC
A IB IB TUT IC
Vclamp=300V

R MJE210 B2 COMMON Voff 500 500F

150 3W

RB
5.1k VCE 51

TUT D1

SCOPE

MTP12N10

1F

-4V

CIRCUIT VALUES

Inductive Switching L=20mH L=10mH RB2=0 RB2=8 VCC=20V VCC=15V IC(pk )=100mA RB1 selected for desired IB1 BVCEO (SUS)
IC ICM t

RBSOA L=500mH R B2=0 VCC=15Volts R B1 selected for desired IB1

TYPICAL WAVEFORMS VCE PEAK VCE IB1 IB I B2

VCC=125V RC=25 D1=1N5820 OR EQUIV

tf CLAMPED t f UNCLAMPEDt2 t1 ADJUSTED TO OBTAIN I C t1 t1 tf Lcoil(ICM) VCC

+11V 0

25s

Lcoil(ICM) t2 Vclamp TEST EQUIPMENT SCOPE-TEKTRONIX 475 OR EQUIVALENT t

9V tr, t f<10ns DUTY CYCLE=1.0% RB AND RC ADJUSTED FOR DESIRED IB AND I C

VCE VCEM Vclamp

TIME

t2

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TYPICAL CHARACTERISTICS
Figure 2. Base-Emitter Saturation Voltage 1.4
Base-Emitte Saturation Voltage, VBE(SAT) (V) Collector-Emitte Saturation Voltage, VCE(SAT) (V)

NPN SILICON TRANSISTOR

Figure 3. Collector-Emitter Saturation Voltage 10 5 2 1 0.5 0.2 0.1 0.05 0.02 IC=-40 25 100 2 5 10 IC/IB =5

IC/IB=5

1.2 1 I C=-40 0.8 0.6 25 100

0.4 0.01 0.02 0.05 0.1 0.2 0.5 1

5 10

0.01 0.01 0.02 0.05 0.1 0.2 0.5 1

Collector Current, IC (A)

Collector Current, IC (A)

Figure 4. Collector Saturation Region 3

Collector-Emitter Voltage, VCE (V)

Figure 5. DC Current Gain 100

DC Current Gain, hFE

TJ=25

VCE=5 TJ=100 25

2.5 2 1.5 1 0.5 I C=1A 0.5 1 2 3 5 10 IC=5A IC=3A I C=8A

10

40

0 0.01 0.02 0.05 0.1 0.2

1 0.01

0.1

10

Base Current, IB (A)

Collector Current, IC (A)

Figure 6. Capacitance 10000 T J=25 100 50

Figure 7. Maximum Forward Bias Safe Operating Area Extended SOA@1s,10s

Collector Current, I C (A)

10 100 1000

Capacitance, C (pF)

Cib 1000 Cob 100

10 0.1

1s 10 5 s 2 TC=25 1ms DC 1 5ms 0.5 0.2 Bonding wire limit 0.1 Thermal limit 0.05 Second breakdown limit curves apply below 0.02 rated VCE O 0.01 10 20 30 50 70 100 200300 500 1000 Collector-Emitter Voltage, VCE (V)

20 10

Reverse Voltage,VR (V)

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TYPICAL CHARACTERISTICS
Figure 8. Maximum Reverse Bias Switching Safe Operating Area 10 1

NPN SILICON TRANSISTOR

Figure 9. Forward Bias Power Derating SECOND BREAKDOWN DERATING

Collector Current, I C (A)

8 6 4 2 0V 0 T C100 G AIN4 LC=500H

Power Derating Factor

0.8 0.6 0.4 0.2 0 20 THERMAL DERATING

VBE(OFF) -5V -2V

0 100 200 300 400 500 600 700 800 Collector-Emitter Clamp Voltage, VCEV (V)

40

60

80

100 120 140 160

Case Temperature, T C ()

Figure 10. Turn-On Time(Resistive Load) 10000 VCC=125V IC/IB=5 IB(on)=IB(off ) 1000 TJ=25 PW=125s 10000 7000 5000 tR

Figure 11. Turn-Off Time (Resistive Load ) VCC=125V IC/I B=5 IB(ON)=I B(OFF) TJ=25 tr PW=25s

tS

Time, t (ns)

Time, t (ns)

2000 1000 700 500 tF 200 100 1 2 3 4

100 tD 10 1 2 3 4 5 6 7 8 9 10

5 6 7 8 9 10

Collector Current, IC (A)

Collector Current, IC (A)

UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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