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EXP NO: 01

DATE:

BINARY ADDERS
AIM To develop the VHDL source code for binary adders a. Half adder b. Full adder c. 4-bit parallel adder and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. BASIC ADDERS HALF ADDER VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hadd is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end hadd; architecture dataflow of hadd is begin sum <= a xor b; carry <= a and b; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity haddbehavioral is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end haddbehavioral;

architecture Behavioral of haddbehavioral is begin p1:process (a,b) begin sum<= a xor b; carry<= a and b; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity haddstructural is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end haddstructural; architecture structural of haddstructural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; begin x1: xor2 port map (a,b,sum); a1: and2 port map (a,b,carry); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<= a and b; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow; Simulation output:

Synthesis RTL Schematic:

FULL ADDER VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_dataflow is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_dataflow; architecture dataflow of fadd_dataflow is signal p,q,r,s:std_logic; begin p<= a xor b; q<= a and b; r<= b and c; s<= c and a; sum<= p xor c; carry<= q or r or s; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_behv is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_behv; architecture Behavioral of fadd_behv is begin p1:process(a,b,c) variable r,s,t:std_logic; begin r:= a and b; s:= b and c;

t:= c and a; sum<= a xor b xor c; carry<= r or s or t; end process p1; end Behavioral;

Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_structural is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_structural; architecture structural of fadd_structural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; component or3 port(a,b,c:in std_logic; z:out std_logic); end component; signal p,q,r,s:std_logic; begin x1: xor2 port map (a,b,p); x2: xor2 port map (p,c,sum); a1: and2 port map (a,b,q); a2: and2 port map (b,c,r); a3: and2 port map (c,a,s); o1: or3 port map (q,r,s,carry); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2;

architecture dataflow of and2 is begin z<= a and b; end dataflow; or3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end or3; architecture dataflow of or3 is begin z<= a or b or c; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow; Simulation output:

Synthesis RTL Schematic:

4-BIT PARALLEL ADDER (Binary adder): VHDL SOURCE CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rca is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); c : in std_logic; s : out std_logic_vector(3 downto 0); cout : out std_logic); end rca; architecture structural of rca is component fadd_behv port(a,b,c:in std_logic; sum,carry:out std_logic); end component; signal c0,c1,c2:std_logic; begin f1:fadd_behv port map (a(0),b(0),c,s(0),c0); f2:fadd_behv port map (a(1),b(1),c0,s(1),c1); f3:fadd_behv port map (a(2),b(2),c1,s(2),c2); f4:fadd_behv port map (a(3),b(3),c2,s(3),cout); end structural; fadd_behv component source code:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_behv is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_behv; architecture Behavioral of fadd_behv is begin p1:process(a,b,c) variable r,s,t:std_logic; begin r:= a and b; s:= b and c; t:= c and a; sum<= a xor b xor c; carry<= r or s or t; end process p1; end Behavioral;

Simulation output:

Synthesis RTL Schematic:

RESULT Thus the OUTPUTs of Binary adders are verified and simulating the VHDL code.

EXP NO: 02

DATE:

MULTIPLEXER
AIM To develop the VHDL source code for multiplexer and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code.

VHDL SOURCE CODE Dataflow Modeling:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_dataflow is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_dataflow; architecture dataflow of mux_dataflow is signal s0bar,s1bar,p,q,r,st:std_logic; begin p<= d(0) and s0bar and s1bar; q<= d(1) and s0bar and s(1); r<= d(2) and s(0) and s1bar; st<= d(3) and s(0) and s(1); s0bar<= not s(0); s1bar<= not s(1); y<= p or q or r or st; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_behv is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_behv; architecture Behavioral of mux_behv is begin p1:process(d,s) begin if (s(0)<='0' and s(1)<='0') then y<=d(0); elsif (s(0)<='0' and s(1)<='1') then y<=d(1); elsif (s(0)<='1' and s(1)<='0') then y<=d(2); else y<=d(3); end if; end process p1; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux1 is Port ( D : in STD_LOGIC_VECTOR (0 to 3); S : in STD_LOGIC_VECTOR (1 downto 0);

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Y : out STD_LOGIC); end mux1; architecture Behavioral of mux1 is begin with S select Y<= D(0) when "00", D(1) when "01", D(2) when "10", D(3) when others; end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux3 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; S : in INTEGER RANGE 0 to 3; Y : out STD_LOGIC); end mux3; architecture Behavioral of mux3 is begin Y<= A when S=0 else B when S=1 else C when S=2 else D; end Behavioral;

Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_struct is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_struct; architecture structural of mux_struct is component not1 port(a:in std_logic;

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z:out std_logic); end component; component and3 port(a,b,c:in std_logic; z:out std_logic); end component; component or4 port(a,b,c,d:in std_logic; z:out std_logic); end component; signal s0bar,s1bar,p,q,r,st:std_logic; begin n1:not1 port map (s(0),s0bar); n2:not1 port map (s(1),s1bar); a1:and3 port map (d(0),s0bar,s1bar,p); a2:and3 port map (d(1),s0bar,s(1),q); a3:and3 port map (d(2),s(0),s1bar,r); a4:and3 port map (d(3),s(0),s(1),st); o1:or4 port map (p,q,r,st,y); end structural; and3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end and3; architecture dataflow of and3 is begin z<=a and b and c; end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow; or4 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic); end or4; architecture dataflow of or4 is begin z<=a or b or c or d; end dataflow; Simulation output:

Synthesis RTL Schematic:

RESULT Thus the OUTPUTs of Multiplexer is verified and simulating the VHDL code.

EXP NO: 03

DATE:

DEMULTIPLEXER
AIM To develop the VHDL source code for demultiplexer and obtain the simulation.

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ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_dataflow is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end demux_dataflow; architecture dataflow of demux_dataflow is signal s0bar,s1bar:std_logic; begin s0bar<= not s(0); s1bar<= not s(1); z(0)<=d and s0bar and s1bar; z(1)<=d and s0bar and s(1); z(2)<=d and s(0) and s1bar; z(3)<=d and s(0) and s(1); end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_behv is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end demux_behv; architecture Behavioral of demux_behv is begin p1:process(d,s) begin if (s(0)<='0' and s(1)<='0') then z(0)<=d; z(1)<='Z'; z(2)<='Z'; z(3)<='Z'; elsif (s(0)<='0' and s(1)<='1') then z(0)<='Z'; z(1)<=d; z(2)<='Z'; z(3)<='Z'; elsif (s(0)<='1' and s(1)<='0') then

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z(0)<='Z'; z(1)<='Z'; z(2)<=d; z(3)<='Z'; else z(0)<='Z'; z(1)<='Z'; z(2)<='Z'; z(3)<=d; end if; end process p1; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1 is Port ( Din : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (0 to 3)); end demux1; architecture Behavioral of demux1 is begin with s select y<= Din &"000"when "00", '0'& Din&"00"when "01", "00"& Din&'0' when "10", "000"&Din when others; end Behavioral;

Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_struct is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end demux_struct; architecture structural of demux_struct is component not1 port(a:in std_logic; z:out std_logic); end component; component and3

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port(a,b,c:in std_logic; z:out std_logic); end component; signal s0bar,s1bar:std_logic; begin n1:not1 port map (s(0),s0bar); n2:not1 port map (s(1),s1bar); a1:and3 port map (d,s0bar,s1bar,z(0)); a2:and3 port map (d,s0bar,s(1),z(1)); a3:and3 port map (d,s(0),s1bar,z(2)); a4:and3 port map (d,s(0),s(1),z(3)); end structural; and3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end and3; architecture dataflow of and3 is begin z<=a and b and c; end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow;

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Simulation output:

Synthesis RTL Schematic:

RESULT Thus the OUTPUTs of Demultiplexer is verified and simulating the VHDL code.

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EXP NO: 04

DATE:

DECODERS
AIM To develop the source code for decoders by using VHDL and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_dataflow is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_dataflow; architecture dataflow of decoder_dataflow is signal abar,bbar:std_logic; begin abar<= not a; bbar<= not b; z(0)<= not (abar and bbar and e); z(1)<= not (abar and b and e); z(2)<= not (a and bbar and e); z(3)<= not (a and b and e); end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_behv is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_behv; architecture Behavioral of decoder_behv is begin

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p1:process(a,b) begin if (e='1') then z(0)<= not a and not b ; z(1)<= not a and b; z(2)<= a and not b; z(3)<= a and b; else z<="1111"; end if; end process p1; end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec1 is Port ( s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0)); end dec1; architecture Behavioral of dec1 is begin with s select y<="1000"when "00", "0100"when "01", "0010" when "10", "0001" when others;

end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_struct is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_struct; architecture structural of decoder_struct is component nand3 port(a,b,c:in std_logic; z:out std_logic); end component;

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component not1 port(a:in std_logic; z:out std_logic); end component; signal abar,bbar:std_logic; begin n1:not1 port map (a,abar); n2:not1 port map (b,bbar); a1:nand3 port map (abar,bbar,e,z(0)); a2:nand3 port map (abar,b,e,z(1)); a3:nand3 port map (a,bbar,e,z(2)); a4:nand3 port map (a,b,e,z(3)); end structural; nand3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end nand3; architecture dataflow of nand3 is begin z<= not (a and b and c); end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow;

Simulation output:

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Synthesis RTL Schematic:

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RESULT Thus the OUTPUTs of Decoder is verified and simulating the VHDL code. EXP NO: 05 DATE:

ENCODER
AIM To develop the source code for encoder by using VHDL and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. ENCODER VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_dataflow is Port ( d : in std_logic_vector(7 downto 0); z : out std_logic_vector(2 downto 0)); end encoder_dataflow; architecture dataflow of encoder_dataflow is begin z(2)<= d(4) or d(5) or d(6) or d(7); z(1)<= d(2) or d(3) or d(6) or d(7); z(0)<= d(1) or d(3) or d(5) or d(7); end dataflow;

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Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_behv is Port ( d : in std_logic_vector(7 downto 0); e : in std_logic; z : out std_logic_vector(2 downto 0)); end encoder_behv; architecture Behavioral of encoder_behv is begin p1:process(d,e) begin if (e='1') then case d is when "10000000"=>z<="000"; when "01000000"=>z<="001"; when "00100000"=>z<="010"; when "00010000"=>z<="011"; when "00001000"=>z<="100"; when "00000100"=>z<="101"; when "00000010"=>z<="110"; when "00000001"=>z<="111"; when others=>z<="ZZZ"; end case; else z<="XXX"; end if; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_struct is Port ( d : in std_logic_vector(7 downto 0); z : out std_logic_vector(2 downto 0)); end encoder_struct; architecture structural of encoder_struct is component or4 port(a,b,c,d:in std_logic; z:out std_logic); end component; begin o1:or4 port map (d(4),d(5),d(6),d(7),z(0)); o2:or4 port map (d(2),d(3),d(6),d(7),z(1)); o3:or4 port map (d(1),d(3),d(5),d(7),z(2)); end structural; or4 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic); end or4; architecture dataflow of or4 is begin z<=a or b or c or d; end dataflow;

Simulation output:

Synthesis RTL Schematic:

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RESULT Thus the OUTPUTs of Encoder is verified and simulating the VHDL code.

EXP NO: 06

DATE:

LATCHES AND FLIP FLOPS


AIM To develop the VHDL source code for a. D latch b. D flip flop c. JK flip flop and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code.

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D LATCH library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dlatch is Port ( D : in STD_LOGIC; clk : in STD_LOGIC; Q : inout STD_LOGIC; Qbar : out STD_LOGIC); end dlatch; architecture Behavioral of dlatch is begin process(clk) begin if (clk='1')then Q<= D; end if; Qbar <= not D; end process; end Behavioral;

Simulation output:

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Synthesis RTL Schematic:

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D FLIPFLOP: VHDL SOURCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end dff; architecture Behavioral of dff is begin process(d,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (d='0') then q<='0'; qbar<='1'; else q<='1'; qbar<='0'; end if; end if; end process; end Behavioral; Simulation output:

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Synthesis RTL Schematic:

JK FLIPFLOP: VHDL SOURCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j : in std_logic; k : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end jkff; architecture Behavioral of jkff is begin process(j,k,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (j='0' and k='0') then q<=q; qbar<=qbar; elsif (j='0' and k='1') then

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q<='0'; qbar<='1'; elsif (j='1' and k='0') then q<='1'; qbar<='0'; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral; Simulation output:

Synthesis RTL Schematic:

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RESULT Thus the OUTPUTs of Latches and Flip Flops are verified and simulating the VHDL code.

EXP NO: 07

DATE:

SHIFT REGISTERS
AIM To develop the VHDL source code for shift register and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code.

SERIAL-IN SERIAL-OUT SHIFT REGISTER: VHDL SOURCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : out std_logic); end siso; architecture Behavioral of siso is signal x:std_logic_vector(7 downto 0); begin process(d,clk,rst) begin if (rst='1') then q<='X'; elsif (clk='1' and clk'event) then x(0)<=d; x(1)<=x(0); x(2)<=x(1); x(3)<=x(2); x(4)<=x(3); x(5)<=x(4); x(6)<=x(5); x(7)<=x(6); q<=x(7); end if; end process;

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end Behavioral;

Simulation output:

Synthesis RTL Schematic:

SERIAL IN PARALLEL OUT SHIFT REGISTER: VHDL SOURCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sipo is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(7 downto 0)); end sipo; architecture Behavioral of sipo is begin

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process(d,clk,rst) begin if (rst='1') then q<="ZZZZZZZZ"; elsif (clk='1' and clk'event) then q(0)<=d; q(1)<=q(0); q(2)<=q(1); q(3)<=q(2); q(4)<=q(3); q(5)<=q(4); q(6)<=q(5); q(7)<=q(6); end if; end process; end Behavioral; Simulation output:

Synthesis RTL Schematic:

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER: VHDL SOURCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pipo is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; q : out std_logic_vector(7 downto 0)); end pipo; architecture Behavioral of pipo is begin process(d,clk,rst) begin if (rst='1') then q<="ZZZZZZZZ"; elsif (clk='1' and clk'event) then q(0)<=d(0); q(1)<=d(1); q(2)<=d(2); q(3)<=d(3); q(4)<=d(4); q(5)<=d(5); q(6)<=d(6); q(7)<=d(7); end if; end process; end Behavioral; Simulation output:

Synthesis RTL Schematic:

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PARALLEL-IN SERIAL-OUT SHIFT REGISTER: VHDL SOURCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity piso is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; load : in std_logic; q : out std_logic); end piso; architecture Behavioral of piso is begin process(d,clk,rst,load) variable x:std_logic_vector(7 downto 0); begin if (clk='1' and clk'event) then if (rst='1') then q<='Z'; else if (load='0') then x:=d; else q<=x(0); x(0):=x(1); x(1):=x(2); x(2):=x(3); x(3):=x(4);

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x(4):=x(5); x(5):=x(6); x(6):=x(7); x(7):='Z'; end if; end if; end if; end process; end Behavioral;

Simulation output:

Synthesis RTL Schematic:

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UNIVERSAL REGISTER VHDL SOURCE CODE Behavioral modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity usrg8 is Port ( D : in STD_LOGIC_VECTOR (7 downto 0); mode : in STD_LOGIC_VECTOR (2 downto 0); Dsl : in STD_LOGIC;

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Dsr : in STD_LOGIC; clk : in STD_LOGIC; pl : in STD_LOGIC; e : in STD_LOGIC; y : out STD_LOGIC_VECTOR (7 downto 0)); end usrg8; architecture Behavioral of usrg8 is signal z:std_logic_vector(7 downto 0); begin process(clk,e,pl) begin If(e='0') then If(pl='1') then If(clk'event and clk='1') then case conv_integer(mode) is when 0 => z<="00000000"; when 1 => z<=z(6 downto 0)& Dsl; when 2 => z<=Dsr & z(7 downto 1); when 3 => z<=z(6 downto 0)& z(7); when 4 => z<=z(0)& z(7 downto 1); when 5 => z<=z(6 downto 0)& '0'; when 6 => z<=z(7)& z(7 downto 1); when others => null ; end case; end if; else z<=D; end if; end if; end process; y<=z; end Behavioral;

RESULT Thus the OUTPUTs of 8-bit shift register are verified and simulating the VHDL code.

EXP NO: 08

DATE:

SYNCHRONOUS AND ASYNCHRONOUS COUNTER


AIM To develop the VHDL source code for synchronous and asynchronous counter and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code.

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SYNCHRONOUS COUNTER: VHDL SOURCE CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity syncounter is Port ( clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(3 downto 0)); end syncounter; architecture structural of syncounter is component tff port(t,clk,rst:in std_logic; q,qbar:inout std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; signal x1,x2:std_logic; signal x3,x4,x5,x6:std_logic:='Z'; begin t1:tff port map ('1',clk,rst,q(0),x3); t2:tff port map (q(0),clk,rst,q(1),x4); t3:tff port map (x1,clk,rst,q(2),x5); t4:tff port map (x2,clk,rst,q(3),x6); a1:and2 port map (q(0),q(1),x1); a2:and2 port map (x1,q(2),x2); end structural; tff component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff; architecture Behavioral of tff is begin process(t,clk,rst,q,qbar) begin if (rst='1') then q<='0';

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qbar<='1'; elsif (clk='1' and clk'event) then if (t='0') then q<=q; qbar<=qbar; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<=a and b; end dataflow;

Simulation output:

Synthesis RTL Schematic:

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ASYNCHRONOUS COUNTER: VHDL SOURCE CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity asyncounter is Port ( clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(3 downto 0)); end asyncounter; architecture structural of asyncounter is component tff port(t,clk,rst:in std_logic; q,qbar:inout std_logic); end component; signal x1,x2,x3:std_logic; signal x4:std_logic:='Z'; begin t1:tff port map ('1',clk,rst,q(0),x1); t2:tff port map ('1',x1,rst,q(1),x2); t3:tff port map ('1',x2,rst,q(2),x3); t4:tff port map ('1',x3,rst,q(3),x4); end structural; tff component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic;

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clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff; architecture Behavioral of tff is begin process(t,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (t='0') then q<=q; qbar<=qbar; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral; Simulation output:

Synthesis RTL Schematic:

RESULT Thus the OUTPUTs of Synchronous and Asynchronous counter are verified and simulating the VHDL code.

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EXP NO: 09

DATE:

MINI PROJECT 8-TAP FIR FILTER


AIM To develop the VHDL source code for 8-TAP FIR FILTER and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. VHDL SOURCE CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity DELAY is Port( D: in std_logic_vector(7 downto 0); CLK : in std_logic; Q,QN: out std_logic_vector(7 downto 0)); end DELAY; architecture DELAY of DELAY IS begin process(CLK) begin if (CLK'event and CLK = ?1?) then Q<=D; QN<= not D; end if; end process; end DELAY; Entity mul_8X8 is Port (A,B : in std_logic_vector(7 downto 0); C : out std_logic_vector(15 downto 0)); End mul_8X8; Architecture mul_8X8 of mul_8X8 is Begin C <= signed(A) * signed(B); End mul_8X8;

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Entity adder_16bit is Generic (len : integer := 16); Port (A,B : in std_logic_vector(15 downto 0); SUM : out std_logic_vector(16 downto 0)); End adder_16bit; Architecture adder_16bit of adder_16bit is Signal C : std_logic_vector(16 downto 0); Signal S : std_logic_vector(15 downto 0); Signal Cout : std_logic; Component onebit FA Port (A,B,Cin : in std_logic; SUM,Cout: out std_logic); End component; Begin C(0) <=0; G1: for i in 0 to (len-1) generate FA : onebit FA port map(A(i),B(i),C(i),S(i),C(i+1)); End generate; Cout <= C(len); SUM <= Cout & S (15 downto 0 ); End adder_16bit; Entity adder_17bit is Generic (len : integer :=17); Port (A,B : in std_logic_vector(16 downto 0); SUM : out std_logic_vector(17 downto 0)); End adder_17bit; Architecture adder_17bit of adder_17bit is Signal C : std_logic_vector(17 downto 0); Signal S : std_logic_vector(16 downto 0); Signal Cout : std_logic; Component onebit FA Port (A,B,Cin : in std_logic; SUM,Cout: out std_logic); End component; Begin C(0) <=0; G1: for i in 0 to (len-1) generate FA : onebit FA port map(A(i),B(i),C(i),S(i),C(i+1)); End generate; Cout <= C(len); SUM <= Cout & S (16 downto 0 ); End adder_17bit; Entity adder_17bit is Generic (len : integer :=18); Port (A,B : in std_logic_vector(17 downto 0); SUM : out std_logic_vector(18 downto 0)); End adder_18bit; Architecture adder_18bit of adder_18bit is

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Signal C : std_logic_vector(18 downto 0); Signal S : std_logic_vector(17 downto 0); Signal Cout : std_logic; Component onebit FA Port (A,B,Cin : in std_logic; SUM,Cout: out std_logic); End component; Begin C(0) <=0; G1: for i in 0 to (len-1) generate FA : onebit FA port map(A(i),B(i),C(i),S(i),C(i+1)); End generate; Cout <= C(len); SUM <= Cout & S (17 downto 0 ); End adder_18bit; Entity FIR_filter is Port (x,h0,h1,h2,h3,h4,h5,h6,h7 : in std_logic_vector(7 down to 0); CLK : in std_logic; Y : out std_logic_vector(18 down to 0)); End FIR_filter; Architecture FIR_filter of FIR_filter is Signal x0,x1,x2,x3,x4,x5,x6,x7 : std_logic_vector(7 downto 0); Signal x0_bar,x1_bar,x2_bar,x3_bar,x4_bar,x5_bar,x6_bar,x7_bar : std_logic_vector(7 downto 0); Signal p0,p1,p2,p3,p4,p5,p6,p7 : std_logic_vector(15 downto 0); Signal s0,s1,s2,s3 : std_logic_vector(16 downto 0); Signal s4,s5 : std_logic_vector(17 downto 0); Component DELAY Port( D: in std_logic_vector(7 downto 0); CLK : in std_logic; Q,QN: out std_logic_vector(7 downto 0)); End component; Component mul_8X8 Port (A,B : in std_logic_vector(7 downto 0); C : out std_logic_vector(15 downto 0)); End component; Component adder_16bit Port (A,B : in std_logic_vector(15 downto 0); SUM : out std_logic_vector(16 downto 0)); End component; Component adder_17bit Port (A,B : in std_logic_vector(16 downto 0); SUM : out std_logic_vector(17 downto 0)); End component; Component adder_18 bit Port (A,B : in std_logic_vector(17 downto 0); SUM : out std_logic_vector(18 downto 0));

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End component; Begin D0 : DELAY port map(x,CLK,x0,x0_bar); D1 : DELAY port map(x0,CLK,x1,x1_bar); D2 : DELAY port map(x1,CLK,x2,x2_bar); D3 : DELAY port map(x2,CLK,x3,x3_bar); D4 : DELAY port map(x3,CLK,x4,x4_bar); D5 : DELAY port map(x4,CLK,x5,x5_bar); D6 : DELAY port map(x5,CLK,x6,x6_bar); D7 : DELAY port map(x6,CLK,x7,x7_bar); M0 : mul_8X8 port map(x0,h0,p0); M1 : mul_8X8 port map(x1,h1,p1); M2 : mul_8X8 port map(x2,h2,p2); M3 : mul_8X8 port map(x3,h3,p3); M4 : mul_8X8 port map(x4,h4,p4); M5 : mul_8X8 port map(x5,h5,p5); M6 : mul_8X8 port map(x6,h6,p6); M7 : mul_8X8 port map(x7,h7,p7); A0 : adder_16bit port map (p0,p1,s0); A1 : adder_16bit port map (p2,p3,s1); A2 : adder_16bit port map (p4,p5,s2); A3 : adder_16bit port map (p6,p7,s3); A4 : adder_16bit port map (s0,s1,s4); A5 : adder_16bit port map (s2,s3,s5); A6 : adder_16bit port map (s4,s5,y); End FIR_filter

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RESULT Thus the OUTPUTs of 8 TAP FIR FILTER are verified and simulating the VHDL code. EXP NO:10 DATE:

BASIC MATHEMATICAL OPERATIONS


AIM To develop the 8051 Assembly language code for basic mathematical operations d. e. f. g. h. i. j. PROGRAMS ;************ Program description ;8 bit unsigned addition using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP ORG START: CLR MOV MOV MOV 0x0000 START 0X0040 A R4,A R2,#20 R3,#30 ;LOAD VALUES IN REGISTER ;clear result vars Addition. Subtraction. Division. Multiplication. Multibyte Addition/ Addition of .series of 8 bit number. Matrix Addition.

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MOV ADD JNC INC NOOFLOW: MOV SJMP END

A,R2 A,R3 NOOFLOW R5 R4,A $ ;Control stays here

;************ Program description ;16 bit Add ;************ Constants ;************ variable declaration ORG LJMP ORG START: MOV R6,#1Ah MOV R7,#44h MOV R4,#22h MOV R5,#0DBh LCALL ADD16_16 SJMP $ ;Call the 16-bit addition routine ;Control stays here ;Load the first value into R6 and R7 ;Load the second value into R4 and R5 0x0000 START 0X0040

ADD16_16: ;Step 1 of the process MOV A,R7 ADD A,R5 MOV R3,A ;Step 2 of the process MOV A,R6 ADDC A,R4 MOV R2,A ;Step 3 of the process ;Move the high-byte into the accumulator ;Add the second high-byte `to the accumulator, plus carry. ;Move the answer to the high-byte of the result ;Move the low-byte into the accumulator ;Add the second low-byte to the accumulator ;Move the answer to the low-byte of the result

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MOV A,#00h ADDC A,#00h MOV R1,A RET END

;By default, the highest byte will be zero. ;Add zero, plus carry from step 2. ;Move the answer to the highest byte of the result ;Return - answer now resides in R1, R2, and R3.

;************ Program description ;8 bit unsigned addition using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP ORG START: CLR MOV MOV MOV MOV ADD JNC INC NOOFLOW: MOV 0x0000 START 0X0040 A R4,A R2,#20 R3,#30 A,R2 A,R3 NOOFLOW R5 R4,A ;LOAD VALUES IN REGISTER ;CLEAR RESULT

SJMP END

;CONTROL STAYS HERE

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************ Program description ;16 bit SUB ;************ Constants ;************ variable declaration ORG LJMP ORG START: 0x0000 START 0X0040

MOV R6,#22h MOV R7,#0DBh MOV R4,#1Ah MOV R5,#0F9h LCALL SUBB16_16 SJMP $

;Load the first value into R6 and R7 ;Load the second value into R4 and R5

;Call the 16-bit SUb routine ;Control stays here

SUBB16_16: ;Step 1 of the process MOV A,R7 CLR C SUBB MOV R3,A ;Step 2 of the process MOV A,R6 SUBB A,R4 MOV R2,A RET END ;Move the high-byte into the accumulator ;Subtract the second high-byte from the accumulator ;Move the answer to the low-byte of the result ;Return - answer now resides in R2, and R3. ;Move the low-byte into the accumulator ;Always clear carry before first subtraction ;Subtract the second low-byte from the accumulator ;Move the answer to the low-byte of the result

;************ Program description ;8 bit Division using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants

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;************ variable declaration ORG LJMP ORG START: MOV MOV MOV MOV MOV LOOP2: SUBB A,R3 JC INC LOOP1 R5 R2,#4 R3,#2 A,R3 R4,A A,R2 ;LOAD VALUES IN REGISTER 0x0000 START 0X0040

DJNZ R4, LOOP2 SJMP LOOP3 LOOP1: LOOP3: INC R5 MOV SJMP END R6,A $ ;Control stays here

*********** Program description ;16 bit Multiplication ;************ Constants ;************ variable declaration ORG LJMP ORG START: 0x0000 START 0X0040

MOV R6,#62h MOV R7,#30h MOV R4,#43h MOV R5,#2Eh

;Load the first value into R6 and R7 ;Load the first value into R4 and R5

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LCALL MUL16_16 SJMP $

;Call the 16-bit subtraction routine

MUL16_16: ;Multiply R5 by R7 MOV A,R5 MOV B,R7 MUL AB MOV R2,B MOV R3,A ;Move the R5 into the Accumulator ; Move R7 into B ;Multiply the two values ; Move B (the high-byte) into R2 ;Move A (the low-byte) into R3

;Multiply R5 by R6 MOV A,R5 MOV B,R6 MUL AB ADD A,R2 MOV R2,A MOV A,B ADDC A,#00h MOV R1,A MOV A,#00h ADDC A,#00h MOV R0,A ;Multiply R4 by R7 MOV A,R4 MOV B,R7 MUL AB ADD A,R2 MOV R2,A MOV A,B ADDC A,R1 MOV R1,A MOV A,#00h ADDC A,R0 ;Move R4 into the Accumulator ;Move R7 into B Multiply the two values ;Add the low-byte into the value already in R2 ; Move the resulting value back into R2 ;Move the high-byte into the accumulator ;Add the current value of R1 (plus any carry) ;Move the resulting answer into R1. ;Load the accumulator with zero ;Add the current value of R0 (plus anycarry) ;Move R5 back into the Accumulator ;Move R6 into B ;Multiply the two values ;Add the low-byte into the value already in R2 ;Move the resulting value back into R2 ;Move the high-byte into the accumulator ;Add zero (plus the carry, if any) ;Move the resulting answer into R1 ;Load the accumulator with zero ;Add zero (plus the carry, if any) ;Move the resulting answer to R0.

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MOV R0,A ;Multiply R4 by R6 MOV A,R4 MOV B,R6 MUL AB ADD A,R1 MOV R1,A MOV A,B ADDC A,R0 MOV R0,A ; RET END;

; Move the resulting answer to R1.

;Move R4 back into the Accumulator ;Move R6 into B ;Multiply the two values Add the low-byte into the value already in R1 ;Move the resulting value back into R1 ;Move the high-byte into the accumulator ;Add it to the value already in R0 (plus any carry) Move the resulting answer back to R0 ;Return - answer is now in R0, R1, R2, and R3

************ Program description ;8 bit Multiply using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ORG LJMP ORG START: MOV R0,#00h MOV R1,#0B3h MOV R2,#08h MOV R3,#00h LCALL div16_16 SJMP $ div16_16: CLR C ;Clear carry initially ;Call the 16-bit DIV routine ;Load the first value into R3 and R2 ;Load the first value into R0 and R1 0x0000 START 0X0040

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MOV R4,#00h MOV R5,#00h MOV B,#00h div1: INC B MOV A,R2 RLC A MOV R2,A MOV A,R3 RLC A MOV R3,A JNC div1 div2: MOV A,R3 RRC A MOV R3,A MOV A,R2 RRC A MOV R2,A CLR C MOV 07h,R1 MOV 06h,R0 MOV A,R0 SUBB A,R2 MOV R0,A MOV A,R1 SUBB A,R3 MOV R1,A JNC div3 MOV R1,07h MOV R0,06h div3: CPL C MOV A,R4 RLC A MOV R4,A

;Clear R4 working variable initially ;CLear R5 working variable initially ;Clear B since B will count the number of left-shifted bits ;Increment counter for each left shift ;Move the current divisor low byte into the accumlator ;Shift low-byte left, rotate through carry to apply to high-byte ;Save the updated divisor low-byte ;Move the current divisor high byte into the accumulator high, rotating in carry from low-byte ;Save the updated divisor high-byte Repeat until carry flag is set from high-byte ;Shift right the divisor ;Move high-byte of divisor into accumulator ;Rotate high-byte of divisor right and into carry ;Save updated value of high-byte of divisor ;Move low-byte of divisor into accumulator ;Rotate low-byte of divisor right, with carry from high-byte ;Save updated value of low-byte of divisor ;Clear carry, we don't need it anymore ;Make a safe copy of the dividend high-byte ;Make a safe copy of the dividend low-byte ;Move low-byte of dividend into accumulator ;Dividend - shifted divisor = result bit (no factor, only 0 or 1) ;Save updated dividend ;Move high-byte of dividend into accumulator ;Subtract high-byte of divisor (all together 16-bit substraction) ;Save updated high-byte back in high-byte of divisor ;If carry flag is NOT set, result is 1 ;Otherwise result is 0, save copy of divisor to undo subtraction highest bit

;Invert carry, so it can be directly copied into result ;Shift carry flag into temporary result

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MOV A,R5 RLC A MOV R5,A DJNZ B,div2 MOV R3,05h MOV R2,04h RET END ;Now count backwards and repeat until "B" is zero ;Move result to R3/R2 ;Move result to R3/R2

;************ Program description ;8 bit unsigned addition of series of numbers using indirect addressing ;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51 ;;************ Constants Input Result ResMsb EQU EQU EQU 0x40 0x50 0x30

;************ variable declaration ORG LJMP ORG 0x0000 START 0X0040

START:

MOV MOV MOV MOV

A,#0 ResMsb,A R0,#Input R1,#Result ;INITIALISE MEMORY LOCATION ;INITIALISE COUNTER, R2 IS USED AS COUNTER ;INITIALISE TEMP VARIABLES ;INITIALISE POINTERS

ACALL InitInputs MOV MOV INC CLR ADD_AGAIN: ADD JNC INC A,@R0 R2,A R0 A A,@R0 NOOFLOW ResMsb

;CLEAR ACCUMULATOR TO STORE RESULT

;increment if carry occurs

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NOOFLOW:

INC DJNZ MOV INC MOV SJMP

R0 R2,ADD_AGAIN @R1,A R1 @R1,ResMsb $ ;STORE MSB IN RESULT LOCATION ;Control stays here ;STORE LSB IN RESULT LOCATION

;FUNCTION TO LOAD VALUE AT MEMORY LOCATION InitInputs: MOV MOV MOV INC DO_AGAIN: MOV INC DJNZ MOV RET END @R0,#8 A,@R0 R2,A R0 @R0,#50 R0 R2,DO_AGAIN R0,#Input ;INITIALISE POINTERS ;LOAD 50 IN TO MEMORY LOCATION ;8 numbers to be added ;INITIALISE COUNTER

********** Program description ;8 bit unsigned addition using register addressing ;R2 = NUM1; R3 = NUM2 ;R4 = LSB, R5 = MSB ;************ Constants ;************ variable declaration ORG LJMP ORG START: CLR 0x0000 START 0X0040 A

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MOV MOV MOV MOV ADD JNC INC NOOFLOW: MOV SJMP END

R4,A R2,#20 R3,#30 A,R2 A,R3 NOOFLOW R5 R4,A $

;clear result vars ;LOAD VALUES IN REGISTER

;Control stays here

;************ Program description ;8 bit unsigned addition of series of numbers using indirect addressing ;INPUT LOCATION 41 to 48 - Array1, 50 to 58 - Array2, 60 to 68 results ;************ Constants Array1 Array2 EQU EQU 0x40 0x50 0x60 0x30 ;Array address

ResArray EQU AddResult EQU

;************ variable declaration ORG LJMP ORG 0x0000 START 0X0040

START:

MOV MOV MOV MOV

R0,#Array1 R1,#Array2

;INITIALISE POINTERS

R3,#ResArray ; ;INITIALISE MEMORY LOCATION ;INIT COUNTER ;INITIALISE COUNTER, R2 IS USED AS COUNTER R2,#9 A,@R0 A,@R1 R0 R1 AddResult,A A,R3 ;STORE RESULT TEMPORARILY

ACALL InitInputs ADD_AGAIN: MOV ADD INC INC MOV MOV

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XCH MOV INC XCH DJNZ SJMP

A,R0 @R0,AddResult R3 A,R0 R2,ADD_AGAIN $ ;Control stays here

;FUNCTION TO LOAD VALUE AT MEMORY LOCATION InitInputs: REFILL: MOV MOV MOV MOV INC INC INC DJNZ MOV MOV RET END A,#1 R2,#9 @R0,A @R1,A A R0 R1 R2,REFILL R0,#Array1 R1,#Array2 ;INITIALISE POINTERS ;9 numbers to be added ;INITIALISE DATA

RESULT Thus the 8051 Assembly language code for basic mathematical operations was developed.

EXP NO:11

DATE:

SMALLEST AND LARGEST NUMBER


AIM To develop the 8051 Assembly language code for find Smallest and largest number in given Array of number. PROGRAM

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;************ Program description ;8 bit unsigned addition of series of numbers using indirect addressing ;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51 ;;************ Constants Input Result Big EQU EQU EQU 0x40 0x50 0x30

;************ variable declaration ORG LJMP ORG START: MOV MOV MOV MOV 0x0000 START 0X0040 A,#0 Big,A R0,#Input R1,#Result ;INITIALISE MEMORY LOCATION ;INITIALISE COUNTER, R2 IS USED AS COUNTER ;INITIALISE TEMP VARIABLES ;INITIALISE POINTERS

ACALL InitInputs MOV MOV INC CLR CHK_AGAIN: MOV JC MOV OOFLOW: INC DJNZ MOV A,@R0 R2,A R0 C A,@R0 OOFLOW Big,@R0 R0

SUBB A,Big ;Small = A, if carry occurs

R2,CHK_AGAIN @R1,Big ;STORE LSB IN RESULT LOCATION

SJMP

;Control stays here

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;FUNCTION TO LOAD VALUE AT MEMORY LOCATION InitInputs: MOV MOV MOV INC MOV DO_AGAIN: MOV INC INC DJNZ MOV RET END @R0,#8 A,@R0 R2,A R0 A,#20 @R0,A ;LOAD 20,21... IN TO MEMORY LOCATION A R0 R2,DO_AGAIN R0,#Input ;INITIALISE POINTERS ;8 numbers to be processed ;INITIALISE COUNTER

RESULT Thus the 8051 Assembly language code for find Smallest and largest number in given Array of number was developed.

EXP NO: 12

DATE:

COUNT THE NUMBER OF EVEN AND ODD NUMBERS

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AIM To develop the 8051 Assembly language code to count the Number of Even and odd numbers in given Array of number. PROGRAM ;************ Program description ;8 bit unsigned addition of series of numbers using indirect addressing ;INPUT LOCATION 41 to 4F,40 -number of digits, OUTPUT LOCATION 50 & 51 ;50 - even numbers, 51 - oddnumbers ;R3 - even numbers,R4 - odd nubers ;************ Constants Input Result EQU EQU EQU 0x40 0x50 0x30 0x31

EvenNum EQU OddNum

;************ variable declaration ORG LJMP ORG START: MOV MOV MOV MOV MOV MOV MOV INC CLR CHK_AGAIN: MOV RRC JNC INC SJMP EVEN: AGAIN: INC INC A,@R0 A EVEN OddNum AGAIN EvenNum R0 ;EVEN COUNT INCREMENTED ;ODD COUNT INCREMENTED A,#0 EvenNum,A OddNum,A R0,#Input R1,#Result ;INITIALISE MEMORY LOCATION ;INITIALISE COUNTER, R2 IS USED AS COUNTER A,@R0 R2,A R0 C ;INITIALISE POINTERS ;INITIALISE TEMP REGISTERS 0x0000 START 0X0040

ACALL InitInputs

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DJNZ MOV INC MOV

R2 ,CHK_AGAIN @R1,EvenNum ;STORE LSB IN RESULT LOCATION R1 @R1,OddNum ;STORE LSB IN RESULT LOCATION

SJMP

;Control stays here

;************ FUNCTION TO LOAD VALUE AT MEMORY LOCATION ********************** InitInputs: MOV MOV MOV INC MOV DO_AGAIN: MOV INC INC DJNZ MOV RET END @R0,#8 A,@R0 R2,A R0 A,#20 @R0,A ;LOAD 20,21... IN TO MEMORY LOCATION A R0 R2,DO_AGAIN R0,#Input ;INITIALISE POINTERS ;8 numbers to be processed ;INITIALISE COUNTER

RESULT Thus the 8051 Assembly language code to count the Number of Even and odd numbers in given Array of number was developed.

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EXP NO:13

DATE:

TO FIND THE POSITIVE AND NEGATIVE NUMBER


AIM To develop the 8051 Assembly language code to Find the Positive and Negative number . PROGRAM ;************ Program description ;CHECKS THE GIVEN NUMBER IS ODD OR EVEN using indirect addressing ;INPUT LOCATION 40,OUTPUT LOCATION 41 = 0, if POSITIVE else 41 = 1 ;************ Constants Input EQU 0x40 ORG LJMP ORG START: MOV MOV CLR MOV INC RLC JC MOV SJMP NEGATIVE: DONE: MOV SJMP END R0,#Input @R0,#31 C A,@R0 R0 A NEGATIVE @R0,#0 DONE @R0,#1 $ ;NUMBER IS NEGATIVE ;Control stays here ;NUMBER IS POSITIVE ;INITIALISE POINTERS ;LOAD DATA IN MEMORY 0x0000 START 0X0040 ;************ variable declaration

RESULT Thus the 8051 Assembly language code to Find the Positive and Negative number was developed .

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EXP NO:14

DATE:

SORTING OF NUMBER
AIM To develop the 8051 Assembly language code to Sort the number in Ascending and descending order. PROGRAM ASCENDING ORG 00h ;-----------------------------------Data Required for the Program-----------------------------------MOV R4,#04h MOV 50h,#0x05 MOV 51h,#0x03 MOV 52h,#0x02 MOV 53h,#0x04 ;----------------------------Sort in Ascending Order Using Bubble Sort------------------------------LOOP1: MOV R0, #03h MOV R1,#50h MOV A, R0 MOV R3, A ;Point to beginning of array ;Initialize R0 - the counter for LOOP2 ;to the value of R0 - the number of iterations in each pass is same ;as the number of elements minus serial number of the current pass. LOOP2: MOV A, @R1 MOV R3, A INC R1 MOV A, @R1 SUBB A, R3 JNC Continue2 ;Inner Loop - Handles each pass. ;Copy a number of the array to the accumulator ;and store it in R3. ;Move to the net number ;and store that in the accumulator. ;Subtract the first from the second. ;If no carry is generated the second is greater and the numbers are ;in order with respect to each other. Otherwise they must be swapped. MOV A, @R1 ;Move the second number to the accumulator. ;Outer Loop - Handles number of passes ;Counter for LOOP1

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XCH A, R3 MOV @R1, A DEC R1 MOV A, R3 MOV @R1, A INC R1 Continue2: DJNZ R0, LOOP2 Continue1: DJNZ R4, LOOP1 Here: SJMP Here END

;Exchange contents of the accumulator and R3. This makes A contain the first number and R1 the second. ;Store the first number at the place where the second one was stored. ;Move to the previous memory location. ;Copy the second number to the accumulator ;and store it in the first number's place. ;Move to the next memory location.

;Move on to the next iteration of the current pass.

;Move on to the next pass. ;End of program - Loop here indefinitely.

;---------------------------------------------------------------------------------------------------DESENDING ;---------------------------------------------------------------------------------------------------ORG 00h ;-----------------------------------Data Required for the Program-----------------------------------MOV R4,#04h MOV 50h,#0x02 MOV 51h,#0x04 MOV 52h,#0x03 MOV 53h,#0x05 ;----------------------------Sort in Desending Order Using Bubble Sort------------------------------LOOP1: MOV R0, #03h MOV R1,#50h MOV A, R0 MOV R3, A ;Point to beginning of array ;Initialize R1 - the counter for LOOP2 ;to the value of R0 - the number of iterations in each pass is same as the number of elements minus serial number of the current pass. LOOP2: MOV A, @R1 ;Inner Loop - Handles each pass. ;Copy a number of the array to the accumulator ;Outer Loop - Handles number of passes ;Counter for LOOP1

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MOV R3, A INC R1 MOV A, @R1 SUBB A, R3 JC Continue2

;and store it in R2. ;Move to the net number ;and store that in the accumulator. ;Subtract the first from the second. ;If no carry is generated the second is greater and the numbers are

in order with respect to each other. Otherwise they must be swapped. MOV A, @R1 XCH A, R3 and R2 the second. MOV @R1, A DEC R1 MOV A, R3 MOV @R1, A INC R1 Continue2: DJNZ R0, LOOP2 Continue1: DJNZ R4, LOOP1 Here: SJMP Here END ;End of program - Loop here indefinitely. ;Move on to the next pass. ;Move on to the next iteration of the current pass. ;Store the first number at the place where the second one was stored. ;Move to the previous memory location. ;Copy the second number to the accumulator ;and store it in the first number's place. ;Move to the next memory location. ;Move the second number to the accumulator. ;Exchange contents of the accumulator and R2. This makes A contain the first number

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RESULT Thus the 8051 Assembly language code to Sort the number in Ascending and descending order was developed.

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