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This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version C based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3 ,4 ,5, and 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x8) , 84 ball(x16) FBGA 67.60 x 30.00 mm form factor RoHS compliant
ORDERING INFORMATION
Part Name HYMP164S64CP6-C4/Y5/S5/S6 HYMP164S64CR6-C4/Y5/S5/S6 HYMP112S64CP6-C4/Y5/S5/S6 HYMP112S64CR6-C4/Y5/S5/S6 HYMP125S64CP8-C4/Y5/S5/S6 HYMP125S64CR8-C4/Y5/S5/S6 Density 512MB 512MB 1GB 1GB 2GB 2GB Organization 64Mx64 64Mx64 128Mx64 128Mx64 256Mx64 256Mx64 # of DRAMs 4 4 8 8 16 16 # of ranks 1 1 2 2 2 2 Materials Lead free Halogen free Lead free Halogen free Lead free Halogen free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Dec. 2009 1
1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS
C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK
ADDRESS TABLE
Density Organization Ranks 512MB 1GB 2GB 64M x 64 128M x 64 256M x 64 1 2 2 SDRAMs 64Mb x 16 64Mb x 16 128Mb x 8 # of DRAMs 4 8 16 # of row/bank/column Address 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms
NC,TEST 164
119 NC/ODT1
NC/CKE1 129
Pin Location
Front Side
Pin #1 Pin #39 Pin #41 Pin #99
Back Side
DQS0 /DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 /DQS2 DM2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
DQS4 /DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 /DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
D0
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
D2
DQS2 /DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 /DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
/CS
ODT
CKE
DQS6 /DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 /DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
D1
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
/CS
ODT
CKE
D3
3 +/-5%
SDRAMS D0-3 SDRAMS D0-3 SDRAMS D0-3 SDRAMS D0-3 SDRAMS D0-3
SCL A0 A1 A2
Serial PD
WP
SDA
SDA
VDDSPD VREF
Serial PD
SDRAMS D0-D3 SDRAMS D0-D3, VDD and VDDQ SDRAMS D0-D3, SPD
2 loads
VDD VSS
2 loads
D0
D4
DQ38 DQ39 DQS5 /DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
D2
D6
DQS2 /DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 /DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
/CS
D1
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
/CS
D5
DQ54 DQ55 DQS7 /DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
/CS
D3
LDQS /UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
/CS
ODT
ODT
ODT
ODT
CKE
CKE
D7
CKE
3 +/-5%
SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15
SCL A0 A1 A2
Serial PD
WP
SDA
SDA
VDDSPD VREF
Serial PD
SDRAMS D0-D3 SDRAMS D0-D3, VDD and VDDQ SDRAMS D0-D3, SPD
VDD VSS
CK1 /CK1
4 loads
D0
D8
D1
D9
DQS1 /DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
/CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQS5 /DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
D10
/CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
/CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D11
DQS2 /DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
/CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
/CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQS6 /DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
D12
/CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
/CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D13
DQS3 /DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
/CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
/CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQS7 /DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
D14
/CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
/CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
10 +/-5%
SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15
SCL A0 A1 A2
Serial PD
WP
SDA
SDA
VDDSPD VREF
Serial PD
SDRAMS D0-D15 SDRAMS D0-D15, VDD and VDDQ SDRAMS D0-D15, SPD
VDD VSS
8 loads
Notes 1 1 2 3
% K Pascal
oC
DC OPERATING CONDITIONS
Symbol VDD VDDL VDDQ VREF VTT VDDSPD Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage EEPROM Supply Voltage
(SSTL_1.8)
Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 1.8 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 3.3
Units V V V mV V V
Note: 1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device.
DDR2 667/800
Min Max
Unit V V
VREF + 0.250 -
VREF - 0.250
VREF + 0.200 -
VREF - 0.200
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
VIX or VOX
Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
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1200pin Unbuffered DDR2 SDRAM SO-DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS
Symbol VOTR Notes: 1. The VDDQ of the device under test is referenced. Parameter Output Timing Measurement Reference Level SSTL_18 0.5 * VDDQ Units V Notes 1
Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement.
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1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25) 512MB : HYMP164S64CP(R)6
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 12.5 27 25 6 Max 15 30 32 7.5 Unit pF pF pF pF
1GB : HYMP112S64CP(R)6
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 17 22 28.5 10 Max 20 25 37 12 Unit pF pF pF pF
2GB : HYMP125S64CP(R)8
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Notes: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Symbol CCK CI1 CI2 CIO Min 17 24 31 7 Max 29 38 56 12 Unit pF pF pF pF
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C4 (DDR2 533@CL4) 520 620 80 216 280 160 96 360 820 820 840 80 40 1220
Y5 (DDR2 667@CL5) 560 660 80 240 320 200 96 400 980 980 900 80 40 1260
S5/S6 (DDR2 800@CL5&6) 600 700 80 256 360 200 96 440 1120 1120 920 80 40 1300
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1 1
14
IDD1
mA mA mA mA mA mA mA
IDD3P
IDD3N
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD7
mA
Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.0 / Dec. 2009 15
Notes: 1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G8(16)31CFP). 2. 0C TCASE 85C 3. 85C TCASE 95C
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Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time
(differential strobe)
Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRE tWPST tIS tIH tRPRE tRPST tRAS tRRD tRRD tFAW tFAW
DDR2-667 min -450 -400 0.45 0.45 min(tCL, tCH) 3000 100 175 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 200 275 0.9 0.4 45 7.5 10 37.5 50 max +450 +400 0.55 0.55 8000 tAC max tAC max tAC max 240 340 +0.25 0.6 1.1 0.6 70000 -
DDR2-800 min -400 -350 0.48 0.48 min(tCL, tCH) 2500 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 175 250 0.9 0.4 45 7.5 10 35 45 max +400 +350 0.52 0.52 8000 tAC max tAC max tAC max 240 300 +0.25 0.6 1.1 0.6 70000 -
Unit ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns ns
Note
1 1
Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write preamble Write postamble Address and control input setup time Address and control input hold time Read preamble Read postamble Activate to precharge command Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB page size Four Active Window for 1KB page size products Four Active Window for 2KB page size products
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DDR2-667 min 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 12 7.8 3.9 2 tAC(max)+0.7 2tCK+ tAC(max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1 max 2 15
DDR2-800 min max 2 tAC(max)+0.7 2tCK+ tAC(max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1 12 7.8 3.9
Unit Note tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us 2 3
WR+tRP 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH -
Notes: 1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G8(16)31CFP). 2. 0C TCASE 85C 3. 85C TCASE 95C
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4.00 0.10 30.00 Detail B PIN 1 2.15 PIN 39 11.40 6.00 1.80 0.10 4.20 Detail B 47.40 PIN 41 Detail A PIN 199 20.00
Back
47.40
SIDE
3.8MAX
2.45
PIN42
PIN 200
1.00 0.10
Detail of Contacts A
0.45 0.03
0.60
2.55
1.80
Note: 1. All dimensions are in millimeters. 2. All outline dimensions and tolerances follow the JEDEC standard.
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4.00 0.10 30.00 Detail B PIN 1 2.15 PIN 39 11.40 6.00 1.80 0.10 4.20 2.45 11.40 1.50 0.10 PIN 2 PIN 40 PIN42 Detail B PIN 200 47.40 PIN 41 Detail A PIN 199 20.00
Back
47.40
SIDE
3.8MAX
1.00 0.10
Detail of Contacts A
0.20 0.15
0.60
2.55
0.45 0.03
2.40 0.10
1.80
Note: 1. All dimensions are in millimeters. 2. All outline dimensions and tolerances follow the JEDEC standard.
21
4.00 0.10 30.00 Detail B PIN 1 2.15 11.40 6.00 1.80 0.10 4.20 11.40 1.50 0.10 PIN 2 PIN 40 PIN42 PIN 200 Detail B 47.40 PIN 39 PIN 41 Detail A PIN 199 20.00
Back
47.40
SIDE
3.8MAX
2.45
1.00 0.10
Detail of Contacts A
0.45 0.03
0.60
2.55
Note: 1. All dimensions are in millimeters. 2. All outline dimensions and tolerances follow the JEDEC standard.
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