Vlsi Design Unit 1

VLSI DESIGN
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Preface
The India Semiconductor Association (ISA), an Indian semiconductor industry organization, has briefed growth, trends and forecasts for the Indian semiconductor market in collaboration with a U.S. consulting company Frost & Sullivan. The report titled as "ISA-Frost & Sullivan 2007/2008 Indian Semiconductor Market Update." According to the report, total semiconductor consumption in India (total value of semiconductors used for devices marketed in India) was $2.69 billion (USD) in 2006. The $2.69 billion represents 1.09% of the global semiconductor market. Of the total semiconductor consumption in India, consumption by local Indian set manufacturers accounted for $1.26 billion. The overall Indian semiconductor consumption will grow at an average rate of 26.7% per year in 2006 through 2009. Based on the actual consumption in 2006, the overall Indian semiconductor consumption is forecast to be $5.49 billion in 2009. This represents 1.62% of the global semiconductor market in 2009. Semiconductor consumption by local Indian set manufacturers is predicted to increase at 35.8% per year in 2006 through 2009 and amount to $3.18 billion in 2009. This material is the result of the Verilog Course Teams practical experience both in Design/Verification and Training. Many of the examples illustrated throughout the material are real designs models. With Verilog Course Teams training experience has led to step by step presentation, which addresses common mistakes and hard-to-understand concepts in a way that eases learning. Verilog Course Team invites suggestion and feedbacks from both students and faculty community to improve the quality, content and presentation of the material.
VLSI DESIGN UNIT 1

MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY
1 .1 NMOS ENHANCEMENT TRANSISTOR 1.2 PMOS ENHANCEMENT TRANSISTOR 1.3 THRESHOLD VOLTAGE 1 . 3 . 1 Threshold Voltage Equations 1.4 BODY EFFECT 1.5 MOS Device Design Equations 1.5.1 Basic DC Equations 1.5.2 Second Order Effects 1.5.2.1 Threshold Voltage-Body Effect 1.5.2.2 Subthreshold Region 1.5.2.3 Channel-length Modulation 1.5.2.4 Mobility Variation 1.6 MOS MODELS 1.7 SMALL SIGNAL AC CHARACTERISTICS 1.9 AN OVERVIEW OF SILICON SEMICONDUCTOR TECHNOLOGY 1.9.1 The Fabrication of a Semiconductor Device 1.9.2 Wafer Fabrication 1.9.3 Assembly 1.10 Basic CMOS Technology 1.10.1 A Basic n-well CMOS Process 1.10.2 A Basic p-well CMOS Process 1.10.3 Twin-Tub (Twin-Well) CMOS Process 1.10.4 Silicon On Insulator (SOI) Process
1 4 4 5 7 7 7 9 9 10 10 11 11 12 14 14 15 19 20 21 24 25 25
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UNIT-1 1.1 NMOS ENHANCEMENT TRANSISTOR

The structure for an n-channel enhancement-type transistor, shown in figure 1.1, consists of a moderately doped p-type silicon substrate into which two heavily doped n+ regions, the source and the drain, are diffused. Between these two regions there is a narrow region of p-type substrate called the channel, which is covered by a thin insulating layer of silicon dioxide (SiO 2 ), called gate oxide. Over this oxide layer is a polycrystalline silicon (polysilicon) electrode, referred to as the gate. Polycrystalline silicon is silicon that is not composed of a single crystal. Since the oxide layer is an insulator, the DC current from the gate to channel is essentially zero. Because of the inherent symmetry of the structure, there is no physical distinction between the drain and source regions. Since SiO 2 has relatively low loss and high dielectric is strength, the application of high gate fields is feasible. In operation, a positive voltage is applied between the source and the Drain (Vdy ). With zero gate bias (Vs = 0), no current flows from source to drain because they are effectively insulated from each other by the two reversed biased pn junctions shown in figure 1.1 (indicated by the diode symbols). However, a voltage applied to the gate, which is positive with respect to 'he source and the substrate, produces an electric field E across the substrate, which attracts electrons toward the gate and repels holes. If the gate voltage is sufficiently large, the region under the gate changes from p-type to n-type (due to accumulation of attracted electrons) and provides a conduction path between the source and the drain.
Figure 1.1 Physical structure of an nMOS transistor Under such a condition, the surface of the underlying p-type silicon is said to be inverted. The term n-channel is applied to the structure. This concept is further illustrated by figure 1.2(a), which shows the initial distribution of mobile positive holes in a p-type silicon substrate of MOS structure for a voltage, V gs , much less than a voltage, Vt, which is the threshold voltage. This is termed the accumulation mode. As V gs is raised above Vt in potential, the holes are repelled causing a depletion region under the gate. Now the structure is in the depletion mode (figure 1.2b). Raising Vgs further above Vt. results in electrons being attracted to the
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region of the substrate under the gate. A conductive layer of electrons in the p substrate gives rise to the name inversion mode (figure 1.2c).
Figure 1.2 Accumulation, Depletion and Inversion modes in an MOS structure The difference between a pn junction that exists in a bipolar transistor or diode (or between the source or drain and substrate) and the inversion layer substrate junction is that in the pn junction, the n-type conductivity is brought about by a metallurgical process; that is, the electrons are introduced into the semiconductor by the introduction of donor ions. In an inversion layer substrate junction, the n-type layer is induced by the electric field E applied to the gate. Thus, this junction, instead of being a metallurgical junction, is a field-induced junction. Electrically, an MOS device therefore acts as a voltage-controlled switch that conducts initially when the gate-to-source voltage, V gs , is equal to the threshold voltage, Vt. When a voltage V d s is applied between source and drain, with Vgs . = Vt , the horizontal and vertical components of the electrical held due to the source-drain voltage and gate-to-substrate voltage interact, causing conduction to occur along the channel. The horizontal component of the electric field associated with the drain-tosource voltage (i.e., V ds > 0) is responsible for sweeping the electrons in the channel from the source toward the drain. As the voltage from drain to source is increased, the resistive drop along the channel begins to change the shape of the channel characteristic. This behavior is shown in figure 1.3. At the source end of the channel, the full gate voltage is
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effective in inverting the channel. However, the drain end of the channel, only the difference between the gate and n voltages is effective. When the effective gate voltage (V gs . Vt) is greater than the drain voltage, the channel becomes deeper as V g s is increased. This is termed the
Figure 1.3 nMOS device behavior under the influence of different terminal voltages "linear," "resistive," "nonsaturated," or "unsaturated" region, where the channel current Ids is a function of both gate and drain voltages. If Vds > Vgs Vt, then Vgd < Vt (Vgd is the gate to drain voltage), and the channel becomes pinched off- the channel no longer reaches the drain. This is illustrated in figure 1.3(c). However, in this case, conduction is brought about by a drift mechanism of electrons under the influence of the positive drain voltage. As the electrons leave the channel, they are injected into the drain depletion region and are subsequently accelerated toward the drain. The voltage across the pinched-off channel tends to remain fixed at (V gs V t ). This condition is the "saturated" state in which the channel current is controlled by the gate voltage and is almost independent of the drain voltage. For the fixed drain-to-source voltage and fixed gate voltage, the factors influence the level of drain current, Ids , flowing between source and drain are: the distance between source and drain the channel width www.verilogcourseteam.com
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the the the the
threshold voltage V, thickness of the gate-insulating oxide layer dielectric Constant of the insulator carrier (electron or hole) mobility
The normal conduction characteristics of an MOS transistor can be categorized as follows: "Cut-off' region: where the current flow is essentially zero (accumulation region). "Nonsaturated" region: weak inversion region where the drain current is dependent on the gate and the drain voltage (with respect to the substrate). "Saturated" region: channel is strongly inverted and the drain current flow is ideally independent of the drain-source voltage (strong inversion region). An abnormal conduction condition called avalanche breakdown or punch-through can occur if very high voltages are applied to the drain. Under these circumstances, the gate has no control over the drain current.
1.2 PMOS ENHANCEMENT TRANSISTOR

As discussed in previous topic toward nMOS; a reversal of n-type and ptype regions yields a p-channel MOS transistor. This is illustrated by figure 1.4. Application of a negative gate voltage (w.r.t. source) draws holes into the region below the gate, resulting in the channel changing from n-type to p-type. Thus, similar to nMOS, a conduction path is created between the source and the drain. In this instance, how-ever, conduction results from the movement of holes (versus electrons) in the channel. A negative drain voltage sweeps holes from the source through the channel to the drain.
Figure 1.4 Physical structure of a pMOS transistor
1.3 THRESHOLD VOLTAGE

The threshold voltage, Vt, for an MOS transistor can be defined as the voltage applied between the gate and the source of an MOS device below which he drain-to-source current Ids , effectively drops to zero. The word effectively is used because the drain current never really is zero but drops to a very small value that may be deemed insignificant for the
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current application .In general, the threshold voltage is a function of a number of parameters including the following Gate conductor material. Gate insulation material. Gate insulator thickness-channel doping. Impurities at the silicon-insulator interface. Voltage between the source and the substrate, V sb
In addition, the absolute value of the threshold voltage decreases with an increase in temperature. This variation is approximately - 4 mV/C for high substrate doping levels, and - 2 mV/C for low doping levels. 1 . 3 . 1 Threshold Voltage Equations Threshold voltage, Vt, may be expressed as
(1.1)
where V t_mos., is the ideal threshold voltage of an ideal MOS capacitor and V fb is what is termed the flat-band voltage. Vt_mos is the threshold where there is no work function difference between the gate and substrate materials. The MOS threshold voltage, V t-mos , is calculated by considering the MOS capacitor structure that forms the gate of the MOS transistor (see for e x a m p l e or 3 ). The ideal threshold voltage may be expressed as
(1.2)
where and
is the oxide capacitance
which is called the bulk charge term. The symbol b is the bulk potential, a term that accounts for the doping of the substrate. It represents the difference between the Fermi energy level of the doped semiconductor and the Fermi energy level of the intrinsic semiconductor. The intrinsic level is midway between the valence-band edge and the conduction band edge of the semiconductor. In a p type semiconductor the Fermi level is closer to the valence hand, while in an n-type s emiconductor it is closer to the conduction band. NA is the density of carriers in the doped semiconductor substrate, and N i is the carrier concentration in intrinsic silicon .N i is equal to 1.45 x 10 10 cm -3 at 3000K. The lowercase k is Boltzmanns constant (1.380 x 10 -23 J/K).T is
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the temperature (K) and q i s t h e electronic charge (1.602 x10 -1 9 Coulomb). The expression kT / q equals 0.02586 Volts at 300 0 K. The term C ox is the permittivity of silicon (1.06 x 10 -12 Farads/cm). The term C o x is the gate-oxide capacitance, which is inversely proportional to the gateoxide thickness (t ox ).The threshold voltage, Vt-mos is positive for ntransistors and negative for p-transistors. The flatband voltage,V fb , is given by Vfb=ms-(Qfc/Cox)
(1.3)
The term V fb is the flat-band voltage. The term Qfc represents the fixed charge due to surface states that arise due to imperfections in the siliconoxide interface and doping. The term ms is the work function difference between the gate material and the silicon substrate ( gate - si ), which may the calculated for an n + gate over a p substrate as follows
(1.4a)
and T is the temperature (K). For an n+ poly gate on an n-substrate
(1.4b)
From these equations it may be seen that for a given gate and substrate material the threshold voltage may be varied by changing the doping concentration o f the substrate (NA ), the oxide capacitance (C ox ), or the surface state charge (Q fc .). In addition, the temperature variation mentioned above may be seen. It is often necessary to adjust the native (original) threshold voltage of an MOS device. Two common techniques used for the adjustment of the threshold voltage entail varying the doping concentration at the siliconinsulator interface through ion implantation or using different insulating material for gate. The former approach introduces a small doped region at the oxide/substrate interface that adjusts the flat-band voltage by varying the Q fc term in equation (1.3). In the latter approach for instance, a layer of silicon nitride (Si 3 N 4 ) is combined with a layer of silicon dioxide resulting in an effective relative permittivity of about 6, which is substantially larger than the dielectric constant SiO 2 . Consequently, for the same thickness as an insulating layer consisting of only silicon dioxide, the dual dielectric process will be electrically equivalent to a thinner layer of SiO 2 leading to a higher C ox value.
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1.4 BODY EFFECT

In general, all devices comprising an MOS device are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. (In some analog circuits this may not be true.) However, in ran gin g the devices to form gating functions it might be necessary to connect several devices in series as shown in figure. 1.5. This may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (V sb1 =0, V sb2 0). Under normal conditions that is, when V gs >V t the depletion-layer width remains constant and charge carriers are pulled into the channel from the source. However, as the substrate bias V sb (Vsource-Vsubstrate) is increased, the width of the channel substrate depletion layer also increases, resulting in an increase in the density of the trapped carriers in the depletion laver. For charge neutrality to hold, the channel charge must decrease. The resultant effect is that the substrate voltage, Vsb , adds to the channelsubstrate junction potential. This increases the gate-channel voltage drop. The overall effect is an increase in the threshold voltage V t (V t2 -V t1 )
Figure 1.5 The effect of substrate bias on series-connected n-transistors
1.5 MOS DEVICE DESIGN EQUATIONS

1.5.1 Basic DC Equations The MOS transistors have three regions of operation: Cutoff or subthreshold region. Nonsaturation or linear region. Saturation region.
The ideal (first order, Shockley) equations describing the behavior of an nMOS device in the three regions are: The cutoff region: Ids=0
Vgs Vt
(1.5a)
The nonsaturation, linear or triode region:
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(1.5b) The saturation region: Ids=(/2)(Vgs-Vt)2 (1.5c)
where Ids is the drain-to-source current, Vgs is the gate-to-source voltage, Vt is the device threshold, and is the MOS transistor gain factor. The last factor is dependent on both the process parameters and the device geometry, and is given by =(/tox)(W/L) (1.6)
where is the effective surface mobility of the carriers in the channel, is the permittivity of the gate insulator, tox is the thickness of the gate insulator, W is the width of the channel, and L is the length of the channel. The gain factor thus consists of a process dependent factor /tox, which contains all the process terms that account for such factors as doping density and gate-oxide thickness and a geometry dependent term (W/L), which depends on the actual layout dimensions of the device. The process dependent factor is sometimes written as Cox, where C ox = / t o x is the gate oxide capacitance. The geometric terms in Eq. (1.6) are illustrated in figure 1.6 in relation to the physical MOS structure.
Figure 1.6 Geometric terms in the MOS device equation
Figure 1.7 VI characteristics for n- and p-transistors
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The voltage-current characteristics of the n- and p-transistors in the non-saturated and saturated regions are represented in figure 1.7 (with the SPICE circuit for obtaining these characteristics for an n-transistor). Note that we use the absolute value of the voltages concerned to plot the characteristics of the p- and ntransistors on the same axes. The boundary between the linear and saturation regions corresponds to the condition | Vds| = | Vgs - Vt | and appears as a dashed line in figure 1.7. The drain voltage at which the device becomes saturated is called Vdsat, or the drain saturation voltage. In the above equations that is equal to Vgs-Vt 1.5.2 Second Order Effects Equation 1.5 represents the simplest view of the MOS transistor DC voltage current equations. There have been many research papers published on more detailed and accurate models that have been created to fill a variety of requirements, such as accuracy, computational efficiency, and the conservation of charge. The circuit simulation program SPICE and its commercial and proprietary derivations generally use a parameter called LEVEL to specify which model equation, are LEVEL1 models build on those defined in Eq. (1.5) and include some important second order effects. LEVEL 2 models calculate the currents based on physics. LEVEL 3 is a semiempirical approach that relies on parameters selected on the basis of matching the equations to real circuits. The MOS device equations in terms of the LEVEL 1 parameters used in SPICE will be covered here. First the term /tox(Cox) is defined as the p r o c es s gain factor. In SPICE this is referred to as KP. Depending on the vintage of the process and the type of transistor, KP may vary from 10-100 pA/V2. In addition, it is not unusual to expect a variation of 10%-20% in KP within a given process as a result of variations in starting materials and variation in SiO2 growth. 1.5.2.1 Threshold Voltage-Body Effect The threshold voltage Vt is not constant with respect to the voltage difference between the substrate and the source of the MOS transistor. This is known as the substrate-bias effect or body effect. The expression for the threshold voltage may be modified to incorporate Vsb, the difference between the source and the substrate.
(1.7) where Vsb is the substrate bias, Vto is the threshold voltage for Vsb=0 , and is the constant that describes the substrate bias effect. The term b is defined in Eq 1.2. Typical values for lie in the range of 0.4 to 1.2. It may be expressed as
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(1.8) in which q is the charge on an electron, ox, is the dielectric constant of the silicon dioxide, si; is the dielectric constant of the silicon substrate, and NA is the doping concentration density of the substrate. The term is the SPICE parameter called GAMMA. Vto is the parameter VTO, N A is he parameter NSUB, and s=2b is PHI, the surface potential at the onset of strong inversion. Thus the threshold shifts by approximately half a volt with the source at 2.5 volts for these process parameters. The type of CMOS process can have a large impact on this parameter for both n- and p-transistors. The increase in threshold voltage leads to lower device currents, which in turn leads to slower circuits. 1.5.2.2 Sub-threshold Region The cutoff region described by Eq. (1.5a) is also referred to as the subthreshold region where Ids increases exponentially with Vds and Vgs. Although the value of Ids is very small (Ids =0), the finite value of Ids may be used to advantage to construct very low power circuits or it may adversely affect circuits such as dynamic-charge storage nodes. As an approximation, Level 1 SPICE models set the subthreshold current to 0. 1.5.2.3 Channel-length Modulation The simplified equations that describe the behavior of an MOS device assume that the carrier mobility is constant, and do not take into account the variations in channel length due to the changes in drain-to-source voltage, Vds . For long channel lengths, the influence of channel variation is of little consequence. However, as devices are scaled down, this variation should be taken into account. When an MOS device is in saturation, the effective channel length actually is decreased such that Leff=L-Lshort where (1.9)
The reduction in channel length increases the (W/L) ratio, thereby increasing as the drain voltage increases. Thus rather than appearing as a constant current source with infinite output impedance, the MOS device has a unite output impedance. An approximation that takes this behavior into account is represented by the following equation:
(1.10) Where k is the process gain factor /tox and is an empirical channel-length modulation factor having a value in the range 0.02V-1 to 0.005V-1
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1.5.2.4 Mobility Variation The mobility , describes the ease with which carriers drift in the substrate material. It is defined by =average carrier drift velocity (V)/ Electric Field (E) (1.11)
If the velocity, V, is given in cm/sec, and the electric field, E, in V/cm, the mobility has the dimensions cm2/V-sec. The mobility may vary in a number of ways. Primarily, mobility varies according to the type of charge carrier. Electrons (negative-charge carriers) in silicon have a much higher mobility than holes (positive-charge carriers), resulting in n-devices having higher currentproducing capability than the corresponding p-devices. Mobility decreases with increasing doping-concentration and increasing temperature. The temperature variation becomes less pronounced as the doping density increases. In SPICE is specified by the parameter UO.
1.6 MOS MODELS

In the previous section the ideal equations that describe the behavior of MOS transistors. While these incorporate some non ideal effects (channellength modulation, threshold-voltage variation), they may not accurately model a specific device in a particular process. That is especially true for devices that have very small dimensions (gate lengths, gate widths, oxide thicknesses) as the modeling process becomes increasingly 3D in nature. Parameter VTO KP nMOS 0.7 8x10-5 pMOS 0.7 2.5x105
Units Volt A/V2 V0.5
Description Threshold voltage Transconductance coefficient Bulk threshold parameter Surface potential at strong inversion Channel length modulation parameter Lateral diffusion
GAMMA
0.4
0.5
PHI
0.37
0.36
volt
LAMBDA
0.01
0.01
Volt-1
LD
0.1 x 10-6
0.1x106
Meter
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TOX NSUB
2x10-8 2x1016
2x10-8 4x1016
Meter 1/cm3
Oxide thickness Substrate doping density
Table 1.1 SPICE DC Parameters Researchers have developed and refined a wide range of MOS models in an effort to predict more accurately the performance of MOS devices before they are fabricated for varying design scenarios. For instance, one might predict DC currents very accurately from raw process parameters, thus helping predict the behavior of an as yet untested device. However, because of the complexity of the model, it might not be appropriate for a fast execution time model that might be needed for digital simulation purposes. In that case, a model based on parameters measured from an actual process might be appropriate. Depending on the particular circuit level simulator that may be available, a wide variety of MOS simulation models may be used. For instance in one commercial circuit simulators there are over 10 different MOS models. Many semiconductor vendors expend a great deal of effort to model the device they manufacture. Many times these efforts are aimed at internal circuit simulators and proprietary models. Most CMOS digital foundry operation have been standardized on the LEVEL 3 models in SPICE as the level of circuit modeling that is required for CMOS digital system design. Table 1.1 is a summary of the main SPICE DC parameters that are used in Levels 1, 2, and 3 with representative values for a 1 n-well CMOS process.
1.7 SMALL SIGNAL AC CHARACTERISTICS

The MOS transistor can be represented by the simplified (Vsb = 0) small signal equivalent model shown in figure1.8 when biased appropriately. Here the MOS transistor is modeled as a voltage-controlled current source (g m ), an output conductance (g ds ), and the interelectrode capacitances. These values may be used, for instance, to calculate voltage amplification factors (gain) or bandwidth characteristics when considered along with other circuit elements.
Figure 1.8 Small signal model for an MOS transistor
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The output conductance (gds ) in the linear region can be obtained by differentiating Eq. (1.5b) with respect to Vds, which results in an output drain-source conductance of g ds =((V gs - V t )-2 V ds ) (Vgs-Vt) (1.12)
Note that consistent with Eq. (2.5b), Vds must be small compared to V gs for the MOS device to be in a linear operating regime. On rearrangement, the channel resistance R c is approximated by Rc(linear) =1/ (Vgs-Vt) (1.13)
which indicates that it is controlled by the gate-to-source voltage. The relation defined by Eq. (1.13) is valid for gate to source voltages that maintain constant mobility in the channel. In contrast, in saturation [i.e., V ds (V gs - Vt)], the MOS device behaves like a current source, the current being almost independent of Vds . This may be verified from Eq. (1.5c) since
(1.14) In practice, however, due to channel shortening (Eq. 1.9) and other effects, the drain-current characteristics have some slope. This slope defines the g ds of the transistor. The output conductance can be decreased by lengthening the channel (i.e., L). The transconductance g m expresses the relationship between output current Ids and the input voltage V gs and is defined by (1.15) It is used to measure the gain of an MOS device. In the linear region g m given by g m(linear) =V ds (1.16) and in the saturation region by g m(sat) = (Vgs-Vt) (1.17)
Since transconductance must have a positive value, the absolute value is used for voltages applied to p-type devices.
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1.9 AN OVERVIEW OF SILICON SEMICONDUCTOR TECHNOLOGY

Silicon in its pure or intrinsic state is a semiconductor, having a bulk electrical resistance somewhere between that of a conductor and an insulator. The conductivity of silicon can be varied over several orders of magnitude by introducing impurity atoms onto silicon crystal lattice. These dopants may either supply free electrons or holes. Impurity elements that use electrons are referred to as acceptors, since they accept some of the electrons already in the silicon, leaving vacancies or holes. Similarly, donor elements provide electrons. Silicon that contains a majority of donors is known as n-type and that which contains a majority are brought together, the region where the silicon changes from n-type and p-type materials are brought together, the region where the silicon changes from n-type to p-type is called a junction. By arranging junctions in certain physical structures and combining these with other physical structures, various semiconductor devices may be constructed. Over the years, silicon semiconductor processing has evolved sophisticated techniques for building these junctions and other structures having special properties. An integrated circuit is a small but sophisticated device implementing several electronic functions. It is made up of two major parts: a tiny and very fragile silicon chip (die) and a package which is intended to protect the internal silicon chip and to provide users with a practical way of handling the component. The various steps in manufacturing processes of transistor both in front-end and back-end is taken as example, because it uses the MOS technology. Actually, this technology is used for the majority of the ICs manufacturing companies. 1.9.1 The Fabrication of a Semiconductor Device The manufacturing phase of an integrated circuit can be divided into two steps. The first, wafer fabrication, is the extremely sophisticated and intricate process of manufacturing the silicon chip. The second, assembly, is the highly precise and automated process of packaging the die. Those two phases are commonly known as Front-End and Backend. They include two test steps: Wafer probing and Final test.
The flow chart is shown in figure 1.9.
Figure 1.9 Manufacturing Flow Chart of an Integrated Circuit
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1.9.2 Wafer Fabrication (Front-End) Identical integrated circuits, called die, are made on each wafer in a multi-step process. Each step adds a new layer to the wafer or modifies the existing one. These layers form the elements of the individual electronic circuits. The main steps for the fabrication of a die are summarized in the following table. Some of them are repeated several times at different stages of the process. The order given here doesn't reflect the real order of fabrication process.
PhotoMasking
This step shapes the different components. The principle is quite simple (see drawing on next page). Resin is put down on the wafer which is then exposed to light through a specific mask. The lighten part of the resin softens and is rinsed off with solvents (developing step).
Etching
This operation removes a thin film material. There are two different methods: wet (using a liquid or soluble compound) or dry (using a gaseous compound like oxygen or chlorine).
Diffusion
This step is used to introduce dopants inside the material or to grow a thin oxide layer onto the wafer. Wafers are inserted into a high temperature furnace (up to 1200 C) and doping gazes penetrate the silicon or react with it to grow a silicon oxide layer.
Ionic Implantation
It allows to introduce a dopant at a given depth into the material using a high energy electron beam.
Metal Deposition
It allows the realization of electrical connections between the different cells of the integrated circuit and the outside. Two different methods are used to deposit the metal: evaporation or sputtering.
Passivation
Wafers are sealed with a passivation layer to prevent the device from contamination or moisture attack. This layer is usually made of silicon nitride or a silicon oxide composite.
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Back-lap
Its the last step of wafer fabrication. Wafer thickness is reduced (for microcontroller chips, thickness is reduced from 650 to 380 microns), and sometimes a thin gold layer is deposited on the back of the wafer.
Initially, the silicon chip forms part of a very thin (usually 650 microns), round silicon slice: the raw wafer. Wafer diameters are typically 125, 150 or 200 mm (5, 6 or 8 inches). However raw pure silicon has a main electrical property: it is an isolating material. So some of the features of silicon have to be altered, by means of well controlled processes. This is obtained by "doping" the silicon. Dopants (or doping atoms) are purposely inserted in the silicon lattice, hence changing the features of the material in predefined areas: they are divided into N and P categories representing the negative and positive carriers they hold. Many different dopants are used to achieve these desired features: Phosphorous, Arsenic (N type) and Boron (P type) are the most frequently used ones. Semiconductors manufacturers purchase wafers predoped with N or P impurities to an impurity level of.1 ppm (one doping atom per ten million atoms of silicon). There are two ways to dope the silicon. The first one is to insert the wafer into a furnace. Doping gases are then introduced which impregnate the silicon surface. This is one part of the manufacturing process called diffusion (the other part being the oxide growth). The second way to dope the silicon is called ionic implantation. In this case, doping atoms are introduced inside the silicon using an electron beam. Unlike diffusion, ionic implantation allows to put atoms at a given depth inside the silicon and basically allows a better control of all the main parameters during the process. Ionic implantation process is simpler than diffusion process but more costly (ionic implanters are very expensive machines).
Figure 1.10 Diffusion and Ionic Implantation Processes PhotoMasking (or masking) is an operation that is repeated many times during the process. This operation is described in figure 1.11. This step is called photomasking because the wafer is masked in some areas (using a specific pattern), in the same way one masks out or protects the windscreens of a car before painting the body. But even if the process is somewhat similar to the painting of a car body, in the case of a silicon chip the dimensions are measured in tenth of microns. The photoresist will replicate this pattern on the wafer. The
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exposed part of the photoresist is then rinsed off with a solvent (usually hydrofluoric or phosphoric acid).
Figure 1.11 Photo Masking Process Metal deposition is used to put down a metal layer on the wafer surface. There are two ways to do that. The process shown in the figure 1.12, is called sputtering. It consists first in creating a plasma with argon ions. These ions bump into the target surface (composed of a metal, usually aluminium) and rip metal atoms from the target. Then, atoms are projected in all the directions and most of them condense on the substrate surface.
Figure 1.12 Metal Deposition Process Etching process is used to etch into a specific layer the circuit pattern that has been defined during the photomasking process. Etching process usually occurs after deposition of the layer that has to be etched. For instance, the poly gates of a transistor are obtained by etching the poly layer. A second example is the aluminium connections obtained after etching of the aluminum layer.
Figure 1.13 Etching Process
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Photomasking, ionic implantation, diffusion, metal deposition, and etching processes are repeated many times, using different materials and dopants at different temperatures in order to achieve all the operations needed to produce the requested characteristics of the silicon chip. The resolution limit (minimal line size inside the circuit) of current technology is 0.35 microns. Achieving such results requires very sophisticated processes as well as superior quality levels. Backlap is the final step of wafer fabrication. The wafer thickness is reduced from 650 microns to a minimum of 180 microns (for smartcard products). Wafer fabrication takes place in an extremely clean environment, where air cleanliness is one million times better than the air we normally breathe in a city, or some orders of magnitude better than the air in a heart transplant operating theatre. Photomasking, for example, takes place in rooms where theres maximum one particle whose diameter is superior to 0.5 micron (and doesnt exceed 1 micron) inside one cubic foot of air. All these processes are part of the manufacturing phase of the chip itself. Silicon chips are grouped on a silicon wafer (in the same way postage stamps are printed on a single sheet of paper) before being separated from each other at the beginning of the assembly phase. Wafer Probing. This step takes place between wafer fabrication and assembly. It verifies the functionality of the device performing thousands of electrical tests, by means of special microprobes. Wafer probing is composed of two different tests: 1. Process parametric test: This test is performed on some test samples and checks the wafer fabrication process itself. 2. Full wafer probing test: This test verifies the functionality of the finished product and is performed on all the dies. The bad dies are automatically marked with a black dot so they can be separated from good die after the wafer is cut. A record of what went wrong with the non-working die is closely examined by failure analysis engineers to determine where the problem occurred so that may be corrected. The percentage of good die on an individual wafer is called its yield.
Figure 1.14 Description of the Wafer Probing Operation
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1.9.3 Assembly (Back-End)
Figure 1.15 The first step of assembly is to separate the silicon chips: this step is called die cutting (figure 1.14). Then, the dies are placed on a lead frame: the leads are the chip legs (which will be soldered or placed in a socket on a printed circuit board. On a surface smaller than a baby's fingernail we now have thousands (or millions) of electronic components, all of them interconnected and capable of implementing a subset of a complex electronic function. At this stage the device is completely functional, but it would be impossible to use it without some sort of supporting system. Any scratch would alter its behavior (or impact its reliability), any shock would cause failure. Therefore, the die must be put into a ceramic or plastic package to be protected from the external world.
Figure 1.15 Description of The Assembly Process
Figure 1.16 Wire Bonding Wires thinner than a human hair (for microcontrollers the typical value is 33 microns) are required to connect chips to the external world and enable electronic signals to be fed through the chip. The process of connecting these thin wires from the chips bond pads to the package lead is called wire bonding.
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The chip is then mounted in a ceramic or plastic package. The package not only protects the chip from external shocks, but also makes the whole device easier to handle. These packages come in a variety of shapes and sizes depending on the die itself and the application in which it will be used.
Figure 1.17 Wire Bonding Operation Products are then marked with a traceability code which is used by the manufacturer and the user to identify the function of the device (and its date of fabrication). At the end of the assembly process, the integrated circuit is tested by automated test equipment. Only the integrated circuits that passed the tests will be packed and shipped to their final destination.
Figure 1.18 Different Kinds of Plastic Packages 1.10 Basic CMOS Technology Complementary metaloxidesemiconductor (CMOS) (pronounced "seemoss), is a major class of integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. Frank Wanlass got a patent on CMOS in 1967 (US Patent 3,356,858).
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CMOS is also sometimes referred to as complementary-symmetry metal oxidesemiconductor. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices. CMOS also allows a high density of logic functions on a chip. The four main CMOS technologies are; n-well process. p-well process. twin-tub process. Silicon on insulator. 1.10.1 A Basic n-well CMOS Process The basic process steps for pattern transfer through lithography, and having gone through the fabrication procedure of a single n-type MOS transistor, the generalized fabrication sequence of n-well CMOS integrated circuits, as shown in figure. 1.12 In the following figures, some of the important process steps involved in the fabrication of a CMOS inverter will be shown by a top view of the lithographic masks and a cross-sectional view of the relevant areas. The n-well CMOS process starts with a moderately doped (with impurity concentration typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide.
Figure 1.19 Once the n-well is created, the active areas of the nMOS and pMOS transistors can be defined. Figures 1.20 through 1.18 illustrate the significant milestones that occur during the fabrication process of a CMOS inverter. Following the creation of the n-well region, a thick field oxide is grown in the areas surrounding the transistor active regions, and a thin gate oxide is grown on
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top of the active regions. The thickness and the quality of the gate oxide are two of the most critical fabrication parameters, since they strongly affect the operational characteristics of the MOS transistor, as well as its long-term reliability.
Polysilicon Gate Connections Figure 1.20 The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry (plasma) etching. CVD Chemical Reactions SiH4(gas) + O2(gas) SiO2(solid) + 2H2 (gas) SiH4(gas) + H2(gas) +SiH2(gas) 2H2(gas) + PolySilicon (solid)
Figure 1.21
Isolation layer Figure 1.22
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The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step. Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respectively. Also, the ohmic contacts to the substrate and to the n-well are implanted in this process step.
Figure 1.23 An insulating silicon dioxide layer is deposited over the entire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows. These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step.
Figure 1.24 Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching.
Figure 1.25 Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability. The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections. The final step is to deposit the passivation
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layer (for protection) over the chip, except for wire-bonding pad areas. The patterning process by the use of a succession of masks and process steps is conceptually summarized in Figure. 1.26. It is seen that a series of masking steps must be sequentially performed for the desired patterns to be created on the wafer surface. An example of the end result of this sequence is shown as a cross-section on the right.
Figure 1.26 1.10.2 A Basic p-well CMOS Process N-well processes have emerged in popularity in recent years. Prior to this p-well process was one of the most commonly available forms of CMOS. Typical p-well fabrication steps are similar to an n-well process, except that a p-well is implemented rather than an n-well. The first masking step defines the p-well regions. This is followed by a low-dose boron implant driven in by a hightemperature step for the formation of the p-well. The well depth is optimized to ensure against n-substrate to n+ diffusion breakdown, without compromising pwell to p+ separation. The next steps are to define the devices and other; to grow field oxide; contact cuts; and metallization. A p-well mask is used to define the p-channel transistors and Vss contacts. Alternatively, an n-plus mask to define the n-channel transistors, because the masks usually are the complement of each other. P-well process are preferred in circumstances where the characteristics of the n- and ptransistors are required to be more balanced than that achievable in an n-well process. Because the transistor that resides in the native substrate tends to have better characteristics, the p-well process has better p devices than an n-well process. Because p-devices inherently have lower gain than n-devices, the n-well
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process exacerbates this difference while a p-well process moderates the difference. 1.10.3 Twin-Tub (Twin-Well) CMOS Process Twin-tub technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed.
Figure 1.27 Twin-well CMOS process cross section Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics. The aim of epitaxy is to grow high-purity silicon layers of controlled thickness with accurately determined dopant concentration distributed homogenously throughout the layer. The electrical properties of this layer are determined by the dopant and its concentration in the silicon. The process sequence, which is similar to the n-well process apart from the tub formation where both p-well and n-well are utilized, entails the following steps, Tub formation. Thin-oxide construction. Source and drain implantations. Contact cut definition. Metallization.
In the conventional n-well CMOS process, the doping density of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics. The twin-tub process (figure 1.20) also avoids this problem. 1.10.4 Silicon On Insulator (SOI) Process Silicon on insulator technology (SOI) refers to the use of a layered siliconinsulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improve performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an
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electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application. The first implementation of SOI was announced by IBM in August 1998. Rather than using silicon as the substrate, the technologies have sought to use an insulating substrate to improve process characteristics such as latchup and speed. Hence the emergence of Silicon On Insulator (SOI) technologies. SOI CMOS processes have several potential advantages over the traditional CMOS technologies. These include closer packing of p- and n- transistors, absence of latchup problems, and lower parasitics substrate capacitances. In the SOI process a thin layer of single-crystal silicon film is epitaxially grown on an insulator such as sapphire or magnesium aluminium spinal. Alternatively, the silicon may be grown on SiO2 that has been in turn grown on silicon. This option has proved more popular in recent years due to the compatibility of the starting material with conventional silicon CMOS fabrication. Various masking and doping techniques (figure 1.27) are then used to form p-channel and n-channel devices. Unlike the more conventional CMOS approaches, the extra steps in well formation do not exist in the technology. The steps used in typical SOI CMOS process are as follows. A thin film (7-8 m) of very lightly doped n-type Si is grown over an insulator, Sapphire or SiO2 is commonly used insulator (figure 1.28 a). An anisotropic etch is used away the Si except where a diffusion area (n or p) will be needed. The etch must be anisotropic since the thickness of the Si is much greater than the spacing desired between the Si islands: (figure 1.28 b, c). The p-islands are formed next by masking the n-islands with a photoresist. A p-type dopant, boron, for example is then implanted. It is masked by the photoresist, but forms p-islands at the unmasked islands. The p-islands will become the n-channel devices (figure 1.28 d). The p-islands are then covered with a photoresist and an n-type dopantphosphorus, for example is implanted to form the n-islands. The n-islands will become the p-channel devices (figure 1.28 e). A thin gate oxide (around 100-250 A) is grown over all of the Si structures, this is normally done by thermal oxidation. A polysilicon film is deposited over the oxide. Often the polysilicon is doped with phosphorus to reduce its resistivity (figure 1.28f). The polysilicon is then patterned by photomasking and is etched. This defines the polysilicon layer in the structure (figure 1.28 g). The next step is to form the n-doped source and drain of the n-channel devices in the p-islands. The n-islands are covered with a photoresist and an n-type dopant, normally phosphorus is implanted. The dopant and an n-type dopant, normally phosphorus is implanted. The dopant will be blocked at the n-islands by the photoresist, and it will be blocked from the gate region of the p-islands by the polysilicon. After this step the n-channel devices are complete (figure 1.28 h).
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The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant such as boron. The polysilicon over the gate of the nisland will block the dopant from the gate, thus forming the p-channel devices (figure 1.28 i).
Figure 1.28 SOI Process Flow A layer of phosphorus glass or some other insulator such as silicon dioxide is then deposited over the entire structure. The glass is etched as contact cut locations. The metallization layer is formed next by evaporating aluminum over the entire surface and etching it to leave only the desired metal wires. The aluminium will flow through the contact cuts to make contact with the diffusion or polysilicon regions (figure 1.28 j). A final passivation layer of phosphorus glass is deposited and etched over bonding pad locations (not shown in figure). Because the diffusion regions extend to the insulating substrate, only sidewall areas associated with source and drain diffusion contribute to the parasitic
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junction capacitance. Since sapphire and SiO2 are extremely good insulators, leakage currents between transistors and substrate and adjacent devices are almost eliminated. In order to improve the yield, some processes use preferential etch in which he island edges are tapered. Thus aluminium or poly runners can enter and leave the islands with a minimum step height. This is contrasted to fully anisotropic etch in which the undercut is brought to zero, as shown in figure 1.29.An isotropic etch is also shown in the same diagram for the comparison. The advantages of SOI technology are as follows, Due to absence of wells, transistor structures denser than bulk silicon are feasible. Also direct n-to-p connections may be made. Lower substrate capacitances provide the possibility for faster circuits. No field-inversion problems exist( insulating substrate) There is no latchup because of the isolation of the n-and p-transistors by the insulating substrate. Because there is no conducting substrate, there are no body-effect problems. However the absence of a backside substrate contact could lead to odd device characteristic such as the kink effect in which the drain current increases abruptly at around 2 to 3 volts. Some of the disadvantages are, Due to absence of substrate diodes, the inputs are somewhat more difficult to protect. Because device gains are lower, I/O structures have to be larger. Single crystal sapphire, spinel substrate, and silicon SiO2 are considerably more expensive than silicon substrate and their processing techniques tend to be less developed than bulk silicon techniques.
Figure 1.29 Classification of Etching processes
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VLSI DESIGN UNIT 1

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

UNIT-1 1.1 NMOS ENHANCEMENT TRANSISTOR

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

the the the the

1.2 PMOS ENHANCEMENT TRANSISTOR

Figure 1.4 Physical structure of a pMOS transistor

1.3 THRESHOLD VOLTAGE

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

is the oxide capacitance

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

and T is the temperature (K). For an n+ poly gate on an n-substrate

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

1.4 BODY EFFECT

Figure 1.5 The effect of substrate bias on series-connected n-transistors

1.5 MOS DEVICE DESIGN EQUATIONS

The nonsaturation, linear or triode region:

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

(1.5b) The saturation region: Ids=(/2)(Vgs-Vt)2 (1.5c)

Figure 1.6 Geometric terms in the MOS device equation

Figure 1.7 VI characteristics for n- and p-transistors

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

1.6 MOS MODELS

Units Volt A/V2 V0.5

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

Oxide thickness Substrate doping density

1.7 SMALL SIGNAL AC CHARACTERISTICS

Figure 1.8 Small signal model for an MOS transistor

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

1.9 AN OVERVIEW OF SILICON SEMICONDUCTOR TECHNOLOGY

The flow chart is shown in figure 1.9.

Figure 1.9 Manufacturing Flow Chart of an Integrated Circuit

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

Figure 1.13 Etching Process

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MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY