CMOS Timing Characteristics

Rise and Fall Times

VLSI Design Dr. Bassel Soudan 1

CMOS Transient Response

Vin

Vout

VDD

0.9 VDD
tf = 10ps

tpdf = 12ps tpdr = 15ps

tr = 16ps
0.1 VDD

0.0

0.0 50p 100p 150p 200p

t(s)

VLSI Design Dr. Bassel Soudan 2

 tf – Fall Time
• Assuming a step-up change on the input of a
CMOS inverter, the output is expected to
transition down over a period of time.
Vin
VOH = VDD

Vout

VOH = VDD
90% VOH

10% VOH

tf

VLSI Design Dr. Bassel Soudan 3

tf – Fall Time
• The fall time depends on the discharging of the load
capacitance CL connected to the output of the inverter.
– When the output is high, CL is charged. Then as the output
switches to low, CL has to discharge through the NMOS
transistor of the driving gate.
• Since there is a step change on the
input, the PMOS transistor will VDD
instantaneously turn off.
– Therefore, ID,P = 0.
IC
• The discharge current for CL is Vin
ID,N
given by:
CL
dV
I D, N = − I C = −C out
dt

VLSI Design Dr. Bassel Soudan 4

 tf – Fall Time
• Rearranging the current equation we get:
dVout
dt = −C
I D, N
• The time required for any voltage change can be found by
integrating over the range of voltage change:
V2 dVout
∆t = −C ∫V
1 I D, N
• We notice that the NMOS transistor will go through two
modes of operation during this transition, saturation and
linear mode.
– Therefore, we have to separate this integral into the two
ranges.
V DD −VTN dVout V dVout
∆t = −CL ∫V − CL ∫V
2

1 I D , N ( Sat ) DD −VTN I D , N ( Lin)

VLSI Design Dr. Bassel Soudan 5

tf – Fall Time
• Substitute the current equations, Vin = VDD, take
the integrals and evaluate using the limits, we
get:
2CL (VTN + V1 − VDD ) CL ⎛ 2V − 2VTN − V2 ⎞
∆t = + ln⎜⎜ DD ⎟⎟
k N (VDD − VTN ) 2
k N (VDD − VTN ) ⎝ V2 ⎠

• It can be seen from the above equation that the

transition time depends directly on the load
capacitance and inversely on the dimensions of
the NMOS transistor.

VLSI Design Dr. Bassel Soudan 6

 tf – Fall Time
• Fall time is defined as the time it takes Vout to
drop from V1 = 0.9 VOH down to V2 = 0.1 VOH.
– Substituting in the above equation, we get:

2CL (VTN − 0.1VDD ) CL ⎛ 1.9VDD − 2VTN ⎞

tf = + ln⎜⎜ ⎟⎟
k N (VDD − VTN ) 2
k N (VDD − VTN ) ⎝ 0.1VDD ⎠

VLSI Design Dr. Bassel Soudan 7

tr – Rise Time
• Assuming a step-down change on the input of
the inverter, the output is expected to transition
up over a period of time.
Vin
VOH = VDD

Vout

VOH = VDD
90% VOH

10% VOH

tr

VLSI Design Dr. Bassel Soudan 8

 tr – Rise Time
• When the output is low, CL is discharged. Then as the
output switches to high, CL has to charge through the
PMOS transistor of the driving gate.
• Since there is a step change on the input, the NMOS
transistor will instantaneously turn off.
– Therefore, ID,N = 0. VDD

ID,P
• The charging current for CL is Vin
IC

given by:
CL
dVout
I D, P = IC = C
dt

VLSI Design Dr. Bassel Soudan 9

tr – Rise Time
• Rearranging the current equation we get:
dVout
dt = C
I D, P
• The time required for any voltage change can be found by
integrating over the range of voltage change:
V4 dVout
∆t = C ∫V
3 I D, P
• The PMOS transistor will go through two modes of
operation during this transition, saturation and linear
mode.
– Therefore, we have to separate this integral into the two
ranges.
−VTP dVout V dVout
∆t = CL ∫V + CL ∫−V
4

3 I D , P ( Sat ) I D , P ( Lin)
TP

VLSI Design Dr. Bassel Soudan 10

 tr – Rise Time
• Substitute the current equations, take the
integrals and evaluate using the limits, we get:

− 2CL (VTP + V3 ) CL ⎛ V + 2VTP + V4 ⎞

∆t = + ln⎜⎜ DD ⎟⎟
k P (VDD + VTP ) 2
k P (VDD + VTP ) ⎝ VDD − V4 ⎠

• It can be seen from the above equation that the

transition time depends directly on the load
capacitance and inversely on the dimensions of
the PMOS transistor.

VLSI Design Dr. Bassel Soudan 11

tr – Rise Time
• Rise time is defined as the time it takes Vout to
rise from V3 = 0.1 VOH to V4 = 0.9 VOH.
– Substituting in the above equation, we get:

− 2CL (VTP + 0.1VDD ) CL ⎛ 1.9VDD + 2VTP ⎞

tr = + ln⎜⎜ ⎟⎟
k P (VDD + VTP ) 2
k P (VDD + VTP ) ⎝ 0.1VDD ⎠

– It can be seen from the equations for tr and tf that

if the inverter is symmetric, then the rise and fall
times become equal.

VLSI Design Dr. Bassel Soudan 12

 Example
• Calculate tf, tr, for the following symmetric CMOS
inverter. Use a CL of 0.1pF
– VDD = 5V
– k’N = 40 µA/V2 WN = 4µm VTN = 1 V
– k’P = 16 µA/V2 VTP= – 1V
– LN = LP = 2µm

– Given the above values, kN = kP = 80 µ A/V2

2(0.1 p )(1 − 0.1(5)) 0.1 p ⎛ 1.9(5) − 2(1) ⎞
tf = + ln⎜ ⎟ = 924 ps
(80 µ )(5 − 1) 2
(80 µ )(5 − 1) ⎝ 0.1(5) ⎠

− 2(0.1 p)(−1 + 0.1(5)) 0.1 p ⎛ 1.9(5) + 2(−1) ⎞

tr = + ln⎜ ⎟ = 924 ps
(80µ )(5 + (−1)) 2
(80µ )(5 + (−1)) ⎝ 0.1(5) ⎠

VLSI Design Dr. Bassel Soudan 13

Example – Contd.
• If we keep everything the same but increase VDD
to 10V, we find:
– tf = tr = 394 ps.

• What if the inverter is not symmetric?

– If we assume a minimum sized inverter, we get:
• tf = 924 ps
• tr = 2.31 ns

VLSI Design Dr. Bassel Soudan 14