A 0.2V-1.

2V Converter for Power Harvesting Applications

Anna Richelli, Luigi Colalongo, Silvia Tonoli and Zsolt Kovacs
Dept. of Electronics University of Brescia Brescia, Italy 25123 Email: anna.richelli@ing.unibs.it

Abstract A DC/DC boost converter to power integrated circuits is presented. It can boost extremely low voltages, starting from about 150mV. The converter is based on a new hybrid inductive and capacitive architecture and it is suitable for power harvesting applications. A test chip was designed and fabricated using a UMC 180nm low threshold CMOS process. Measurements on the chip conrm the validity of the design.

I. I NTRODUCTION Nowadays, autonomous devices self-powered over a full lifetime by harvesting the energy coming from the surrounding environment (solar energy, temperature gradients, vibrations and so on) are very attractive for many applications as, for instance, smart sensors, ambient intelligence and smart cards active security [1]-[4]. On the other hand, energy harvesting exploits the external environment as a source of energy, and thus, due to its row quality (low voltages, low currents, or both), it is often unsuitable for supply standard integrated devices. By the way of example, thermopiles, which are very attractive for a wide range of applications, when exposed to low temperature gradients can deliver high currents at low voltages, much lower than the threshold of standard electronic devices. In this paper we present a DC/DC boost converter designed in the UMC 180nm CMOS process that can supply 1.2V converting an input voltage of 200mV delivered, in our prototype, by a thermopile of 127 miniaturized Peltier cells exposed to a temperature gradient of 5o C. In section 2 the state-of-art charge pumps will be shortly outlined, in section 3 the basic idea of the hybrid inductivecapacitive converter is introduced, in section 4 the measurement results are provided. II. S TATE - OF - ART The classical charge pump proposed by Dickson [5] is based on a diode-connected MOS as charge transfer device and it provides approximately an output voltage: VOU T = (N +1)(VDD VT ) where N is the number of stages, VDD is the supply voltage and VT is the threshold voltage of the diodeconnected MOS. Unfortunately, as the voltage is increased by charge pumping, the threshold voltage of the MOS transistors increases due to the body effect, the voltage step VDD VT of each stage is reduced and the overall efciency decreases. Moreover, since the threshold voltage cannot be scaled as

much as the scaling trend of the supply voltage, the impact of the threshold voltage becomes more and more appreciable as the technology scales down. Therefore, several attempts were made to reduce the threshold voltage loss [6]-[7],[8]-[12] and a lot of work was devoted to investigate the power consumption of charge pumps [13]. The great effort to improve the performances of charge pumps has produced many efcient architectures. Unfortunately, due to the extremely low voltages, these architectures are unsuitable for power harvesting applications, as, for example, thermopile power sources. The main limitations come from from the threshold voltages of diodes and pass-transistors and from the low transistor channel conductivity due to low supply voltages. Furthermore, capacitive converters exhibit an intrinsic drawback when they are used in ultra-low voltage applications: a large number of pumping stages are required to boost very low supply voltages and the overall efciency decreases drammatically. On the other hand, DC/DC converters based on inductive components are widely used in power electronics and recently they were integrated in a CMOS standard process too [14]. The main limitations of a fully integrated inductive converter come from its low power efciency at very low input voltages. In order to reach a reasonably large output voltage, these converters should be driven by almost ideal clock signals, large currents and almost lossless devices. It is worth adding that several DC/DC converter ICs are fabricated in fully depleted SOI (Silicon On Insulator) technology to enable ultra-low voltage operations [15]. These circuits show good overall performances, thanks to the low leakage currents, but the technology is still expensive compared to the standard CMOS technologies. III. DC/DC CONVERTER A RCHITECTURE In this section a new DC/DC converter compatible with ultra-low voltage power harvesting applications will be described. It is based on a hybrid inductive and capacitive architecture and may be fabricated in standard low voltage low threshold CMOS processes. In Fig. 1 the block diagram of the overall DC/DC converter architecture is shown. It is driven by an internal low voltage clock generator directly connected to the 200mV input voltage source. Two inductive step-up converters are used to boost the

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Fig. 3.

Schematic of the proposed converter

Fig. 1.

Block diagram of the hybride inductive-capacitive converter

Fig. 2.

Basic inductive step-up converter

low voltage clock signal followed by a 2-stage CMOS charge pump which recties and multiplies the boosted clock. In order to better understand the circuit behavior, rst the basic operation of an inductive step-up circuit will be explained. As shown in Fig. 2, a typical step-up is formed by a switch, an inductor and a diode connected MOS. When the MOS switch is on, the current ows from the power supply through the inductor and energy is stored in the inductor itself. In this rst

phase, the diode is reverse biased, the output stage is isolated and the output current is supplied by the charge stored in the load capacitor. When the MOS switch is abruptly turned off, since the current in the inductor cannot change instantaneously, an inductive voltage spike appears across the inductor, forcing the bottom end of the inductor (D) to a high positive voltage larger than the supply. The diode is forward biased and the current, initially owing from the inductor through the MOS to ground, starts owing through the diode to the load capacitor. In order to reach large voltage spikes the step-up converter usually operates in discontinuous conduction mode. The voltage spikes are strictly related to the inductance of the inductor, to the duty-cycle, to the conductivity of the MOS switches and to the clock edges. The larger the inductance and the current through the inductor, the larger the voltage spikes. In the proposed overall architecture, two step-up converters driven by two non-overlapping clock signals are exploited to boost the low voltage clock produced by a ring oscillator powered directly by the 200mV voltage supply. After this stage, depending on the device sizing, the clock is boosted three or four times and can drive the following charge pump stages, pushing up the bottom plate voltages of the capacitors. The inductors were sized to optimize the voltage spikes at the operating frequency, that in turn depends on the maximum frequency achievable by the clock generator. The clock generator is a simple 9 stage CMOS ring oscillator followed by a 75% duty-cycle generator and by a buffer chain that drives the large capacitive load of the MOS inductor switches. Circuit simulations have shown that the operating frequency of the clock generator is in the range of several MHz, and that reasonable inductances are in the range of 33-47H. It is worth noting that the two inductors (33H) of our prototype are external SMD components whose physical dimensions are

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Fig. 4. stage

Clock signal and boosted clock signal generated by the rst step-up

Fig. 5. Clock signal and boosted clock signal generated by the second step-up stage

comparable with the IC size and much smaller if compared to the thermopile itself (it ranges from 1cm X 1cm X 0.2cm to 4cm X 4cm X 0.2cm). Furthermore, the two MOS switches were sized as a tradeoff between conductance and parasitic capacitance: larger devices are desirable in order to force high currents on the inductors, on the other hand the drain capacitance grows linearly with the device width, clamping the voltage spikes of the inductor. In order to achieve large inductor voltages, the duty cycle Ton /Ts of the switches is an important parameter as well: large duty cycle forces a large current through the inductors and leads to large output voltages. On the other hand, more current through the switches leads to high power consumption; a tradeoff between maximum current and power consumption has to be reached. After an optimization process a dutycycle of 75% was adopted. The duty-cycle generator has been designed using a ip-op chain and logic gates. Hence, the overall clock generator is based on a simple 9-stage ring oscillator, followed by a 75% duty-cycle generator and by a buffer that drives the high capacitive load of the MOS switches. The switches, as in the conventional step-up converters, are used to generate large voltage spikes when the inductors current is abruptly turned off. In the classical step-up converters, however, the inductor current is rectied by a diode which is directly connected to the output load. In our converter, the voltage spikes generated by the two inductors are used as the clock to push up the bottom plate voltage of the charge pump capacitors. In Figs. 4 and 5 the 75%-duty-cycle clock signals are plotted along with the inductorsboosted clock signals. It is worth stressing that in the proposed converter the inductive step-ups generate two non-overlapping boosted clock signals exploited by the following charge pump. The charge pump is based on a 2-stages modied Favrat architecture similar to that of [12] and suitable for very low voltage applications. In particular, only NMOS transistors are used as pass-transistors due to their low VT compared to that of the PMOS ones: the NMOS threshold of the UMC process is slightly less than 100mV, depending both on the biasing conditions and on the transistor channel lenght. Therefore, the PMOS pass-transistors of [12] are replaced by diode-

Fig. 6.

Schematic of the 2-stage charge pump

connected NMOS devices, as shown in Fig. 6. The rst stage of the charge pump is directly connected to the low voltage input source (through the transistors M0 and M2) while the bottom plate of the boost capacitors (of about 400pF) are biased by the 800mV rectangular clock waves generated by the inductive converters. After the initial transient, when Clock1 = 800mV , Clock2 = 0, M1 and M2 are on, while M0 and M3 are off; C1 is charged to V dd through M1, while C0 is discharged through M2 and the voltage at node A reaches the value of about 800mV +V dd. Similarly when Clock1 = 0, Clock2 = 800mV , M0 and M3 are on, M1 and M2 are off; C0 is charged to V dd through M0, while C1 is discharged through M3. Same considerations hold for the second stage as well and the output voltage Vout, neglecting the load current and the parasitics, may reach 2 800mV + V dd. The main features of the hybrid inductive-capacitive architecture comes both from the optimal use of the step-up converters, that drive only small capacitive loads, and from the large clock voltages that drive each stage of the charge pump. IV. M EASUREMENTS In order to test the validity of the proposed converter, a test chip was fabricated using a UMC 180nm CMOS process. The core area of the circuit is of about 900m X 450m. The measurement setup is based on a Peltier cell (which acts in reverse mode, as a thermopile), a heater and a heatsink which force a temperature gradient between the hot and the cold plate

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2 1.75 1.5

a voltage supply ranging from 100mV to 450mV, in the case of a capacitive load: the DC/DC converter can boost 140mV as well.

V. C ONCLUSIONS In this paper the feasibility of a DC/DC converter for very low voltage supplies is demonstrated, in the author knowledge, for the rst time. The converter, supplied by an input voltage of about 200mV, generates a boosted output in the range of the typical voltages that power current integrated circuits (1.2V-1.5V). It is based on an hybrid inductive-capacitive architecture, it can be fabricated in a standard CMOS process and it is suitable for power harvesting applications. A test chip was designed and fabricated. It can supply 1.2V converting the input voltage given by a thermopile exposed to a 5o C thermal gradient. ACKNOWLEDGMENT The authors wish thank Europractice for the prototyping service and Proff. V. Ferrari and D. Marioli for the interesting discussions about possible applications of the converter. R EFERENCES
[1] A. Paradiso et Al., Energy Scavanging for Mobil and Wireless Electronics, IEEE Pervasive Computing, Mar. 2005. [2] H. Lhermet et Al., Efcient Power Management Circuit: Thermal Energy Harvesting to Above-IC Microbattery Energy Storage, Proc. of ISSCC 2007, Feb. 2007. [3] P. D. Mitcheson et Al., Architectures for Vibration Driven Micropower Generators, IEEE JMEMS, vol. 13, Jun. 2004. [4] R. Amirtharajah et Al., Self-Powered Signal Processing Using VibrationBased Power Generation, IEEE JSSCC, vol. 33, May 1998. [5] J. Dickson et Al., On-chip High-voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique, IEEE JSSC, vol. 11, Jun. 1976. [6] R. Pelliconi et Al., Power Efciency Charge Pump in Deep Submicron Standard CMOS Technology, IEEE JSSC, vol. 38, Jun. 2003. [7] A. Richelli et Al, A 1.2 to 8V Charge Pump with Improved Power Efciency for Non-Volatile Memories, Proc. of ISSCC, Feb. 2007. [8] J. T. Wu et Al., Low Supply CMOS Charge Pump, Symp. VLSI Circuits Dig. Tech. Papers, 1997. [9] K. H. Cheng et Al., A CMOS Charge Pump for sub-2.0V Operation, Proc. of ISCAS, May 2003. [10] J. Shin et Al., A New Charge Pump without Degradation in Threshold Voltage due to Body Effect, IEEE JSSC, vol. 35, Aug. 2000. [11] L. Mensi et Al, A New Integrated Charge Pump Architecture using Dynamic Biasing of Pass-Transistors, Proc. of ESSCIRC 2005, Sep. 2005. [12] M. D. Ker et Al, Design of Charge Pump with Consideration of gateoxide reliability in low-voltage CMOS processes, IEEE JSSC, vol. 41, May 2006. [13] G. Palumbo et Al, A CMOS Charge Pump Circuits: Power Consumption Optimization, IEEE TCAS-I, vol. 49, Nov. 2002. [14] A. Richelli et Al, A Fully-Integrated Inductor Based 1.8V-6V Step-Up Converter, IEEE JSSC, vol. 39, Jan. 2004. [15] Seiko Instruments Inc., Ultra-Low Voltage Operation Charge Pump IC for Step-Up DC-DC Converter Startup, Datasheet S-882Z Series.

Vout(V)

1.25 1 0.75 0.5 0.25 15 30 45 60 75 Rload(KOhm) 90 105

Measurement results (Vdd=200mV) Simulation results (Vdd=200mV)

Fig. 7.

Comparison between Measurement results and Simulations

2.75 2.5 2.25 2

Vout(V)

1.75 1.5 1.25 1 0.75 0.5 0.25 100 150 200 250 300 Vdd (mV) 350 400 450
Measurement results

Fig. 8. Measurement results varying the Voltage Supply, in the case of capacitive load

of the Peltier cell and, eventually, a board with the converter itself. The thermopile size is about 3cm X 3cm X 0.2cm, while the integrated converter is a 28pin CSOIC standard package; the two external inductors are very small SMD devices. Several cycles of measurements on many chips were performed, using the nominal working conditions (0.2V voltage supply), with a resistive load ranging from 10K to 100 K. The output voltage is plotted in Fig. 7 and it is compared to the simulation results; a fair agreement between simulations and measurements is reported. The DC/DC converter can boost very low voltage supplies reaching about 1.2V output voltage at 10K resistive load. In order to investigate the converter behavior at very low input voltages and its suitability for power harvesting applications, measurements were performed reducing the voltage supply as low as 100mV. In Fig. 8 the output voltage is shown with

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