Pin Diagram of 8086

Gursharan Singh Tatla
professorgstatla@gmail.com
www.eazynotes.com 1 Gursharan Singh Tatla
Intel 8086
O 3tel 8086 was lau3ched
i3 1978.
O t was the first 16-bit
microprocessor.
O This microprocessor had
major improveme3t over
the executio3 speed of
8085.
O t is available as 40-pi3
Dual-3li3e-Package
(DP).
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Intel 8086
O t is available i3 three
versio3s:
R 8086 (5 MHz)
R 8086-2 (8 MHz)
R 8086-1 (10 MHz)
O t co3sists of 29,000
tra3sistors.
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Intel 8086
O t has a 16 li3e data
bus.
O A3d 20 li3e address
bus.
O t could address up to
1 MB of memory.
O t has more tha3
20,000 i3structio3s.
O t supports
multiplicatio3 a3d
divisio3.
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!n D,7,2 of Intel 8086
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D
0
- D
1
!n 16-2, 89 (B-d7eeton,l)
O These li3es are multiplexed bi-
directio3al address/data bus.
O Duri3g T
1
, they carry lower
order 16-bit address.
O 3 the remai3i3g clock cycles,
they carry 16-bit data.
O AD
0
-AD
7
carry lower order byte
of data.
O AD
8
-AD
15
carry higher order
byte of data.
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19
/S
6
,
18
/S
,
17
/S
4
,
16
/S
8
!n 8-88 (Und7eeton,l)
O These li3es are
multiplexed u3idirectio3al
address a3d status bus.
O Duri3g T
1
, they carry
higher order 4-bit address.
O 3 the remai3i3g clock
cycles, they carry status
sig3als.
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BHE / S
7
!n 84 (uutput)
O BHE sta3ds for Bus High
E3able.
O BHE sig3al is used to
i3dicate the tra3sfer of data
over higher order data bus
(D
8
- D
15
).
O 8-bit /O devices use this
sig3al.
O t is multiplexed with status
pi3 S
7
.
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#D (#e,d)
!n 82 (uutput)
O t is a read sig3al used for
read operatio3.
O t is a3 output sig3al.
O t is a3 active low sig3al.
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#EDY
!n 22 (Input)
O This is a3 ack3owledgeme3t
sig3al from slower /O
devices or memory.
O t is a3 active high sig3al.
O Whe3 high, it i3dicates that
the device is ready to
tra3sfer data.
O Whe3 low, the3
microprocessor is i3 wait
state.
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#ESET
!n 21 (Input)
O t is a system reset.
O Whe3 high,
microprocessor e3ters i3to
reset state a3d termi3ates
the curre3t activity.
O t must be active for at
least four clock cycles to
reset the microprocessor.
INT#
!n 18 (Input)
O t is a3 i3terrupt request
sig3al.
O t is active high.
O t is level triggered.
NHI
!n 17 (Input)
O t is a 3o3-maskable
i3terrupt sig3al.
O t is a3 active high.
O t is a3 edge triggered
i3terrupt.
TEST
!n 28 (Input)
O t is used to test the
status of math co-
processor 8087.
O The BUSY pi3 of 8087 is
co33ected to this pi3 of
8086.
O f low, executio3 co3ti3ues
else microprocessor is i3
wait state.
!n 19 (Input)
O This clock i3put provides
the basic timi3g for
processor operatio3.
O t is symmetric square
wave with 33% duty cycle.
O The ra3ge of freque3cy of
differe3t versio3s is 5
MHz, 8 MHz a3d 10 MHz.
'
,nd '
SS
!n 40 ,nd !n 20 (Input)
O '
is power supply sig3al.

O +5' D is supplied
through this pi3.
O '
SS
is grou3d sig3al.
HN / HX
!n 88 (Input)
O 8086 works i3 two modes:
R Mi3imum Mode
R Maximum Mode
O f MN/MX is high, it works
i3 mi3imum mode.
O f MN/MX is low, it works
i3 maximum mode.
HN / HX
!n 88 (Input)
O Pi3s 24 to 31 issue two
differe3t sets of sig3als.
O O3e set of sig3als is issued
whe3 PU operates i3
mi3imum mode.
O Other set of sig3als is
issued whe3 PU operates
i3 maximum mode.
!n Dese7pton fo7 Hn2u2
Hode
INT
!n 24 (uutput)
O This is a3 i3terrupt
ack3owledge sig3al.
O Whe3 microprocessor
receives NTR sig3al, it
ack3owledges the
i3terrupt by ge3erati3g
this sig3al.
E
!n 2 (uutput)
O This is a3 Address Latch
E3able sig3al.
O t i3dicates that valid
address is available o3 bus
AD
0
- AD
15
.
O t is a3 active high sig3al
a3d remai3s high duri3g T
1
state.
O t is co33ected to e3able pi3
of latch 8282.
DEN
!n 26 (uutput)
O This is a Data E3able
sig3al.
O This sig3al is used to
e3able the tra3sceiver
8286.
O Tra3sceiver is used to
separate the data from the
address/data bus.
DT / #
!n 27 (uutput)
O This is a Data
Tra3smit/Receive sig3al.
O t decides the directio3 of
data flow through the
tra3sceiver.
O Whe3 it is high, data is
tra3smitted out.
O Whe3 it is low, data is
received i3.
H / Iu
!n 28 (uutput)
O This sig3al is issued by the
microprocessor to
disti3guish memory access
from /O access.
O Whe3 it is high, memory is
accessed.
O Whe3 it is low, /O devices
are accessed.
#
!n 29 (uutput)
O t is a Write sig3al.
O t is used to write data i3
memory or output device
depe3di3g o3 the status of
M/O sig3al.
HD
!n 80 (uutput)
O t is a Hold Ack3owledge
sig3al.
O t is issued after receivi3g
the HOLD sig3al.
HuD
!n 81 (Input)
O Whe3 DMA co3troller
3eeds to use address/data
bus, it se3ds a request to
the PU through this pi3.
O Whe3 microprocessor
receives HOLD sig3al, it
issues HLDA sig3al to the
DMA co3troller.
!n Dese7pton fo7 H,2u2
Hode
"S
1
,nd "S
0
!n 24 ,nd 2 (uutput)
O These pi3s provide the
status of i3structio3
queue.
QS
1
QS
0
Status
0 0 No operatio3
0 1 1
st
byte of opcode from queue
1 0 Empty queue
1 1 Subseque3t byte from queue
S
0
, S
1
, S
2
!n 26, 27, 28 (uutput)
O These status sig3als
i3dicate the operatio3
bei3g do3e by the
microprocessor.
O This i3formatio3 is
required by the Bus
o3troller 8288.
O Bus co3troller 8288
ge3erates all memory a3d
/O co3trol sig3als.
S
0
, S
1
, S
2
!n 26, 27, 28 (uutput)
S
2
S
1
S
0
Status
0 0 0 3terrupt Ack3owledge
0 0 1 /O Read
0 1 0 /O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
u
!n 29 (uutput)
O This sig3al i3dicates that
other processors should 3ot
ask PU to reli3quish the
system bus.
O Whe3 it goes low, all
i3terrupts are masked a3d
HOLD request is 3ot
gra3ted.
O This pi3 is activated by usi3g
LO prefix o3 a3y
i3structio3.
#"/CT
1
,nd #"/CT
0
!n 80 ,nd 81 (B-d7eeton,l)
O These are Request/Gra3t
pi3s.
O Other processors request the
PU through these li3es to
release the system bus.
O After receivi3g the request,
PU se3ds ack3owledge
sig3al o3 the same li3es.
O RQ/GT
0
has higher priority
tha3 RQ/GT
1
.

Pin Diagram of 8086

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Gursharan Singh Tatla

is power supply sig3al.

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