Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment

Instruction Sheet
Department: C.S.E. Subject: Digital Electronics

Index
Sr. No
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Name/Title Of Experiments.
Study & verify truth table of digital IC & Logic gates. Study and verification of operation of Half & Full adder. Study and verification of operation of Half & Full Subs tractor. Study and Verification Of operation of code converter Study and Verification of operation of Multiplexer & De-multiplexer. Study and Verification of operation of comparator. Study and Verification of operation of ALU. Study and verification of operation of FLIP-FLOP. Study and verification of operation of Shift Registers. Study and verification of operation of Counters.

Page Nos.
2 to 5 6 to 9 10 to 14 15 to 18 19 to 22 23 to 26 27 to 29 30 to 35 36 to 38 39 to 42

Performed Dates

Staff Sign.

Remark

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Mr. Pankaj Katkar.

1

Approved by:

H.O.D. (Dept. of C.S.E.)

Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 1 Experiment Title: Study & verify truth table of digital IC & Logic gates. Aim: To study and verify the truth table of digital ICs & Logic gates. Apparatus: IC 7404, IC 7408, IC7432, IC7400, IC7486, IC CD4011, IC CD4001, Trainer Kit, Multimeter, connecting wires. Theory: Logical NOT Gate: The logic circuit or gate which performs NOT (complement) operation is known as NOT gate. It has only one input and only one output. Boolean Equitation of NOT operation : Logical AND Gate: The logic circuit or gate which perform AND operation is Known as AND gate. The AND gate has two or more inputs and one output. In the Boolean equation of AND gate (.) Dot represents logical multiplication. Boolean Equitation of AND operation: Logical OR Gate: The logical circuit OR gate which performs OR operation is known as OR gate. The OR gate has two or more inputs and one output. In Boolean equitation of OR gate represents plus (+) i.e logical addition. Boolean Equitation of OR operation: Logical NAND gate: The logical circuit or gate which performs NAND (NOT-AND) operation is known as NAND gate. This NAND gate has two or more than two inputs and one output. In Boolean equitation of NAND gate dot (.) represents logical multiplication and bar ( ) represents NOT operation. Boolean Equitation of NAND operation: Logical NOR Gate: The NOR operation is defined as, the output of NOR gate is 1 if and only if all the inputs are 0.when NOT gate is combined with OR gate, the result gate is NOR gate. Boolean Equitation of NOR operation:

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Logical EX-OR Gate: The logical circuit or gate which performs EX-OR operation is known as EXOR gate. The Exclusive-OR gate is abbreviated as EX-OR or sometimes XOR. In the Boolean expression symbol is (small circle with plus sign) represents. Boolean Equitation of EX-OR operation: Logical EX-NOR Gate: The logic or gate which performs Ex-NOR (NOT - Ex OR) operation is known as EX-NOR gate. It has two or more inputs and one output. In the Boolean expression EX-NOR symbol is (small circle with dot). Boolean equitation of EX-NOR operation: Procedure: 1. 2. 3. 4. 5. Place the IC on IC Trainer Kit. Connect Vcc and ground to respective pins of IC Trainer Kit. Connect the inputs to the input switches provided in the IC Trainer Kit. Connect the outputs to the switches of O/P LEDs. Apply various combinations of inputs according to the truth table and observe condition of LEDs. 6. Disconnect output from the LEDs and note-down the corresponding multimeter voltage readings for various combinations of inputs. FOR NOT GATE: NOT (Inverter) Gate IC:7404LS Truth Table for NOT gate: Sr No. 1 2 Input Output (A) (Y)

FOR AND GATE: 2-Inputs AND Gate IC:7408LS

Truth Table for AND gate

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FOR OR GATE: 2-Inputs OR Gate IC:7432LS

Truth Table for OR gate

FOR NAND GATE: 2-Input NAND gate IC:7400LS

Truth Table for NAND gate

FOR NOR GATE: 2-Input NOR gate IC:7402LS Truth Table for NOR gate

FOR EX-OR GATE: 2-Input NOR gate IC:7486LS

Truth Table for NOR gate

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FOR EX-NOR GATE: 2-Input NOR gate IC:74LS

Truth Table for NOR gate

LAB Work: Realize following expressions using gates and construct truth table:: 1) Sum Of Product (SOP): BD+AD

2)

Product Of Sum (POS): Y=(A+B)D

Conclusion: Hence, we have studied operations of different logic gates and verified their truth tables. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***
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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 2 Experiment Title: study and verification of operation of Half & Full adder. AIM: To study and verify the truth table of Half Adder & Full Adder circuits. APPARATUS REQUIRED: Sr.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Trainer Kit Range IC 7408 IC 7432 IC 7404 IC 7486 As required As required Quantity 1 1 1 1 1 As required As required

THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 102 The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. HALF ADDER: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augends and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.

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HALF ADDER CIRCUIT DIAGRAM:

TRUTH TABLE OF HALF ADDER: Sr.No 1. 2. 3. 4. INPUT A B 0 0 0 1 1 0 1 1 OUTPUT Sum

Carry

DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A + B Carry, C = A. B FULL ADDER CIRCUIT DIAGRAM:

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TRUTH TABLE OF FULL ADDER: S. No 1. 2. 3. 4. 5. 6. 7. 8. INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT SUM CARR Y

DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, SUM = ABC + ABC + ABC + ABC CARRY = ABC + ABC + ABC +ABC PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagrams. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for the half adder and full adder circuits.

LAB WORK: Construct and verify truth table for Half adder & Full adder by using NAND gates: Half Adder using NAND gates: Sr. No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Sum Carry

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Full Adder using NAND gates:

Sr. No 1. 2. 3. 4. 5. 6. 7. 8.

INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1

OUTPUT SUM CARR Y

Conclusion:

Hence, we have studied operations of Half Adder & Full Adder circuits and verified their truth tables for it. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***
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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 3 Experiment Title: study and verification of operation of Half & Full Subs tractor. AIM: To design and verify the truth table of the Half Substractor & Full Substractor circuits. APPARATUS REQUIRED: Sr.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7486 As required Quantity 1 1 1 1 1 As required

THEORY: The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely, 0-0=0 0 - 1 = 1 with 1 borrow 1-0=1 1-1=0 In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.

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HALF SUBTRACTOR DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF = A B Borrow, BORR = A. B CIRCUIT DIAGRAM:

TRUTH TABLE: Sr. No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT DIFF BORR

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FULL SUBTRACTOR TRUTH TABLE: Sr. No 1. 2. 3. 4. 5. 6. 7. 8. DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF= ABC + ABC + ABC + ABC Borrow, BORR = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, DIFFERENCE A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT DIFF BORR

DIFF = ABC + ABC + ABC + ABC = A

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BORROW

BORR = AB + AC + BC CIRCUIT DIAGRAM:

PROCEDURE: 1) Connections are given as per the circuit diagrams. 2) For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3) Apply the inputs and verify the truth table for the half Substractor and full Substractor circuits.

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LAB WORK: Fill the following truth table for Half & Full Substractor: Sr. No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Conclusion: INPUT B 0 0 0 0 1 1 1 1 0 1 OUTPUT DIFF BORR

A 1 1 1 1 0 0 0 0 0 1

C 1 0 1 0 1 0 1 0 1 0

Hence, we have studied operations of Half Substractor & Full Substractor circuits and verified their truth tables for it.

Date Of Practical performed

Date of Staff assessment

Sign of Staff

Remark

***

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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 4 Experiment Title: Study and Verification Of operation of code converter. Aim: Study and Verification Of operation of code converter To design and set up1) 4-bit Binary to Gray code converter circuits using gates. 2) 4-bit Gray to Binary code converter using gates.

APPARATUS REQUIRED: Sr.No 1. 2. 3. 4. Name of the Apparatus EX-OR Gate NAND Gate Connecting wires Trainer Kit Range IC 7486 IC 7400 As required Quantity 1 1 As required

Theory: Gray Code Gray code is non weighted code. The special feature of gray code is that, only one bit will change at a time from one code number to next. Binary system In binary number system three bit will change in binary equivalent of (3)10 and (4)10 . BINARY TO GRAY CONVERTER: Steps in Binary to Gray code conversion 1) Record the MSB bit as it is. 2) Add the binary MSB to the next bit. 3) Record the sum and neglect any carry. 4) Continue this process until LSB is reached. For Example: (3)10 = (0011)2 = (0010)gray (4)10 = (0100)2 = (0110)gray

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Circuit Diagram:

Fill the Truth table for binary to gray converter:

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GRAY TO BINARY CONVERTER Steps in Gray to Binary code conversion 5) Record the MSB bit as it is. 6) Add the binary MSB to the next bit of gray code. 7) Record the sum and neglect any carry. 8) Continue this process until LSB is reached. Circuit diagram:

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Fill the Truth table for gray to binary converter:

Conclusion:

Hence, we have studied, designed circuits for Binary to Gray and Gray to Binary Converter. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***
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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 5 Experiment Title: Verification of operation of Multiplexer & De-multiplexer. AIM: To design and verify the truth table of a 4X1 Multiplexer & 1X4 De-multiplexer. APPARATUS REQUIRED: Sr.No 1. 2. 3. 4. 5. THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is many into one and it provides the digital equivalent of an analog selector switch. De-multiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines. DESIGN 4 X 1 MULTIPLEXER: LOGIC SYMBOL: Name of the Apparatus Digital IC trainer kit OR gate NOT gate AND gate ( three input ) Connecting wires Range IC 7432 IC 7404 IC 7411 Quantity 1 1 1 1 As required

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TRUTH TABLE: Sr. No 1. 2. 3. 4. PIN DIAGRAM OF IC 7411: SELECTION INPUT S1 S2 0 0 0 1 1 0 1 1 OUTPU T Y

CIRCUIT DIAGRAM:

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DESIGN 1X4 DE-MULTIPLEXER: LOGIC SYMBOL:

TRUTH TABLE: Sr. No 1. 2. 3. 4. 5. 6. 7. 8. CIRCUIT DIAGRAM: INPUT S 2 0 0 1 1 0 0 1 1 OUTPUT Y Y 1 2

S 1 0 0 0 0 1 1 1 1

Di n 0 1 0 1 0 1 0 1

Y 0

Y 3

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PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagrams. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for the multiplexer & de-multiplexer.

Conclusion:

The design of the 4x1 Multiplexer and 1x4 De-multiplexer circuits was done and their truth tables were verified. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***

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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 6 Experiment Title: Study and Verification of operation of comparator. AIM: To Realize 1-bit digital comparators & 2-bit digital compotator with the following outputs (i) a > b (ii) a = b (iii) a < b APPARATUS REQUIRED: SR.No Name of the Apparatus 1. Digital IC trainer kit 2. AND gate 3. OR gate 4. Not gate 5. Ex-or gate 6. Magnitude comparator 7. Patch chords

Range 7408 7432 7404 7486 7485

Quantity 1 1 1 1 1 1

THEORY: A Magnitude comparator is a combinational circuit that compares two numbers, A and B , and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicates whether- A > B, A = B, A < B. 1-BIT COMARATOR Circuit diagram:

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Truth table of 1-bit comparator

2-BIT COMARATOR Circuit Diagram:

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Truth table of 2-Bit Comparator:

Boolean Equations for values A>B, A=B, A<B:

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Procedure: 1)Rig up the circuit for one bit &two bit comparator as shown in the figure using IC 7485 magnitude comparator and basic gates. 2)Verify the Table of values .the output obtained should match the required result.

Conclusion:

The design of 1-bit digital comparators & 2-bit digital compotator and their truth tables were verified. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***

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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 7 Experiment Title: Study and Verification of operation of ALU. Aim: Study of operation of ALU. SR.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit ALU Patch chords Range 74181 Quantity 1 1

THEORY: A very popular and widely used combinational circuit is ALU. This is capable of performing arithmetic as well as logical operations. The ALU as name indicates it is Arithmetic and Logic Unit of processor IC. It can able to process any arithmetic as well as logical data. It also able to control all data inputs and identifies the data type accordingly it does process on it. Procedure: 1. Connections are made as shown in the Circuit diagram. 2. Change the values of the inputs and verify at least 5 functions Given in the function table. Pin detail & Function table:IC 74181

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Fallow the procedure and verify following FUNCTION TABLE:

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Conclusion:

The design of 1-bit digital comparators & 2-bit digital compotator and their truth tables were verified. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***

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Mr. Pankaj Katkar.

29

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H.O.D. (Dept. of C.S.E.)

Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 8 Experiment Title: Study and verification of operation of FLIP-FLOP.

AIM: To verify the characteristic table of RS, D, JK, and T Flip flops . APPARATUS REQUIRED: Sr. No 1. 2. 3. 4. 5. 6. THEORY: A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states. RS FLIP FLOP: The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state. D FLIP FLOP: To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other. Name of the Apparatus Digital IC trainer kit NOR gate NOT gate AND gate ( three input ) NAND gate Connecting wires Range Quantity 1 IC 7402 IC 7404 IC 7411 IC 7400 As required

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JK FLIP FLOP: The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. T FLIP FLOP: This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop. LOGIC SYMBOL: RS FLIP FLOP

CIRCUIT DIAGRAM:

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CHARACTERISTIC TABLE: Fill The Table: CLOC INPUT K PULS S R E 1 0 0 2 0 0 3 0 1 4 0 1 5 1 0 6 1 0 7 1 1 8 1 1 D FLIP FLOP LOGIC SYMBOL:

PRESENT STATE (Q) 0 1 0 1 0 1 0 1

NEXT STATE(Q+1)

STATUS

CIRCUIT DIAGRAM:

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CHARACTERISTIC TABLE: Fill the following table: CLOC K INPUT PULS D E 1 0 2 0 3 1 4 1

PRESENT STATE (Q) 0 1 0 1

NEXT STATE(Q+1)

STATUS

JK FLIP FLOP LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CHARACTERISTIC TABLE: Fill the following table: CLOC K PULS E 1 2 3 4 5 6 7 8 INPUT J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 PRESENT STATE (Q) 0 1 0 1 0 1 0 1 NEXT STATE(Q+1) STATUS

T FLIP FLOP LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CHARACTERISTIC TABLE: Fill the following table: CLOC K PULS E 1 2 3 4

INPUT T 0 0 1 1

PRESENT STATE (Q) 0 1 0 1

NEXT STATE(Q+1)

STATUS

PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagrams. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and observe the status of all the flip flops.

Conclusion:

The design of The Characteristic tables of RS, D, JK, T flip flops and their truth tables were verified. Date Of Practical performed Date of Staff assessment Sign of Staff Remark

***
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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 9 Experiment Title: Study and verification of operation of Shift Registers. AIM: To implement and verify the truth table of a serial in serial out shift register. APPARATUS REQUIRED: Sr. Name of the Apparatus No 1. Digital IC trainer kit 2. D Flip Flop 3. Connecting wires THEORY: A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next. The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register. PIN DIAGRAM OF IC 7474:

Range IC 7474

Quantity 1 2 As required

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CIRCUIT DIAGRAM:

TRUTH TABLE: For a serial data input of 1101, Calculate All Outputs and fill the table: CLO CK PUL SE 1 2 3 4 5 6 7 8 INPUTS D1 1 1 0 1 X X X X D2 X 1 1 0 1 X X X D3 X X 1 1 0 1 X X D4 X X X 1 1 0 1 X Q1 OUTPUTS Q2 Q3 Q4

Sr.N O 1 2 3 4 5 6 7 8

PROCEDURE: 1. 2. Connections are given as per the circuit diagrams. Apply the input and verify the truth table of the counter.

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Conclusion:

The design and truth table of a serial in serial out left shift register was verified.

Date Of Practical performed

Date of Staff assessment

Sign of Staff

Remark

***

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Marathwada Shikshan Prasarak Mandals Deogiri Technical Campus for Engineering and Management Studies, Aurangabad Practical Experiment Instruction Sheet
Department: C.S.E. Subject: Digital Electronics Experiment No. : 10 Experiment Title: Study and verification of operation of Counters. AIM To study and realization of 3-bit counters as a sequential circuit. (7476) a) Asynchronous type b) Synchronous type APPARATUS REQUIRED: Sr. No 1. 2. 3. 4. 5. 6. 7. 8. 9. THEORY: A sequential circuit that gives through a prescribed sequence of states upon the application of input pluses is called counters. The straight binary sequence counter is the simple and most straight forward. An n-bit binary counter has n flip-flops and can count in binary from 0 to 2n -1. (A). ASYNCRONOUS COUNTERS A binary ripple (Asynchronous) counter consists of a series connections of T- flip-flops without any logic gates. Each FF is triggered by the output of its preceding FF goes from 1 to 0 (B) SYNCHRONOUS COUNTERS In Synchronous counters all FF are triggered simultaneously by the count pulse. The FF is complemented only if its T input is equal to 1 the advantage of synchronous counter is its speed, it takes only one propagation delay time for the correct binary count to appear the clock edge bits. Name of the Apparatus Range Quantity 1 1 1 1 1 1 As Required

JK flip flop NAND gate(3 pin) AND gate OR gate Decade Counter Decade Up/down Counter MOD 16 counter Patch chords Trainer Kit

7476 7408 7432 7490 74192 74193 As Required

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Mr. Pankaj Katkar.

39

Approved by:

H.O.D. (Dept. of C.S.E.)

Realization of 3-bit binary counters using IC7476(MOD-8)

PIN DIAGRAM :

UP COUNT (MOD-8)

WAVE FORMS

Prepared by:

Mr. Pankaj Katkar.

40

Approved by:

H.O.D. (Dept. of C.S.E.)

FILL THE TRUTH TABLE:

DOWN COUNT :

FILL THE TRUTH TABLE:

Prepared by:

Mr. Pankaj Katkar.

41

Approved by:

H.O.D. (Dept. of C.S.E.)

PROCEDURE: 3. 4. Connections are given as per the circuit diagrams. Apply the input and verify the truth table of the counter.

Conclusion:

The design and Realization of 3-bit binary counters using IC7476(MOD-8) was verified.

Date Of Practical performed

Date of Staff assessment

Sign of Staff

Remark

***

Prepared by:

Mr. Pankaj Katkar.

42

Approved by:

H.O.D. (Dept. of C.S.E.)