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Latches
Store (Hold) a logic value through feedback Break feedback path to Set the latch Clock is used to control Sampling or Holding
Samples on the active LEVEL Holds on the inactive Level
EE 287 notes Morris Jones
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Latch
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Asynchronous Not timed by clock Limits on how and when used in most ASIC design guides
System reset Timing tool problems with these
EE 287 notes Morris Jones
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Latch clocking
Active on a level Sample the entire time clock is active Output follows the input 2 inverter delays later When clock changes, latch Holds
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Flip Flops
Appear to sample on a clock edge
Rising or falling
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Master
Slave
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Master
Slave
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Setup time
Logic in latch/FF takes more time than clock signal
D input must be earlier than clock for latch to latch in value.
Signal must be stable and not change Clock usually defines time
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For the Latch to work, the D signal must get all the way around the inverter loop before the clock disables the D input
EE 287 notes Morris Jones
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The amount of time the input must be stable after the clock edge before the mux in the latch changes, and the input will not influence the output
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D Stable
EE 287 notes Morris Jones
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C to Q time
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Meta-Stable States
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Meta-Stable State
VM is Vin=Vout Two inverters in series (Most Latches)
Stable inflection point
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Q=CD*CQold Qold
/C
clk\ C
Din
CLK
/C
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Gated Clock
D D
SET
CLR
CK EN
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C EN
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Clock Timing
Latch Hold time Logic Delay Time
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