1. Draw the truth table oI SR F/F using (i) NAND gates (ii) NOR gates?

2. Draw the diagram oI clocked SR F/F where SR1 leads to illegal State. (Why does this condition lead to racing
condition?)
3. Draw the circuit diagram oI a key debouncing circuit using SR F/F.
4. What is meant by bouncing oI the switch?
5. Draw the circuit diagram oI a pulse transition detector which produces a pulse when negative edge occurs. What
determines the width oI the pulse?
6. Draw the circuit diagram oI a positive edge triggered F/F using SR F/F.
7. Draw the circuit diagram oI Master slave JK F/F built using SR F/F.
8. Show how D F/F is built using SR F/F. Write the truth table oI D F/F.
9. Draw the circuit diagram oI JK F/F and write the truth table.
10. How are the Iollowing F/Fs obtained Irom J/K F/F (i) D F/F (ii) T F/F.
11. Show how asynchronous clear and reset inputs can be included in the SR F/F.
12. Draw the circuit diagram oI the asynchronous counters with modulus oI (i)16 (ii) 12 (iii) 10.
13. Explain why glitches occur at the decoder used along with asynchronous counters.
14. List the transient (temporary) states visited by a 4 bit asynchronous counter when the counter state. changes Irom
state 1 1 1 1 to 1000
15. The clock to Q delay oI a F/F is 10ns. Find the time taken Ior the state oI an 8 bit asynchronous counter to change
Irom 1111 1111 to 0000 0000. II a 32 bit asynch. F/F is designed using the above F/F, what is the
maximum operating Irequency oI this counter?
16. Show how a square wave oI Irequency 100kHz can be obtained Irom a square wave oI Ireq.12MHZ using async.
Counter.
17. State anyone merit and demerit oI synchronous counter over async. Counter.
18. Draw the circuit diagram oI a mod 16 synchronous counter. A F/F has the Iollowing characteristics: Clock to Q
delay: l0 ns, set up time: 10ns, hold time: 0 ns. Find the maximum operating Irequency oI the counter Ior the
Iollowing modulus values (i) 16 (ii) 32.
19. DeIine the Iollowing parameters oI F/F: (i) Clock to Q delay (ii) Set up time (iii) Hold time.
20. Design a Mod 5 synchronous counter and draw the circuit diagram.
21. List the values oI JK inputs oI a Mod 3 counter which counters in the sequence 0, 3, 2, 0, 3, 2,.
22. Draw the circuit diagram oI 4 bit up down (i) synchronous (ii)asynchronous counters.
23. What is meant by a programmable modulus synchronous counter? How do you realize a Mod 100 counter using the
above counter.
24. Draw the block diagram oI a digital clock with 6 seven segment displays. Show how the seven segment decoder
required can be reduced to be 2.
25. What is the use oI the Iollowing input/output oI a synchronous counter. (i)LOAD (ii) CLR (iii) CTEN. (iv) RCO.
26. Show how a mod 100 counter can be realized using two (ii) Mod 10 async. Counters (iii) sync. Counter.
27. Draw the circuit diagram 8 bit parallel to serial converter using (i) Multiplexer (ii) shiIt register. Explain their
operation.
28. Draw the circuit diagram oI a universal shiIt register which shiIts either towards leIt or right depending upon the
control bit.
29. Draw the circuit diagram oI 4 bit (i)Johnson counter (ii) Ring counter. List the various states oI the counter when
diIIerent clock edges occur.
30. What is the number oI FFs required to realize a mod10 (i) ring counter (ii) Johnson counter
31. Explain any two methods Ior introducing delays to a signal.
32. Draw the waveIorm at the 3 outputs Q0,Q1,Q2 oI a 3 bit counter Ior 8 clock cycles iI the counter is (i) synchronous
(ii) asynchronous. Assume the clock period and clock to Q delay to be 100ns and 10ns respectively.
33. What should be the number to be loaded into the input oI a 8 bit programmable modulus synchronous counter to
realize a Mod 50 counter?
34. How does the value oI MAX/MIN output change as the counter counts up in (a) decade counter (b) 4 bit counter?
35. Explain what is meant static 1 hazard with an example. How is it prevented?
36. Explain what is meant static 0 hazard with an example. How is it prevented?
37. Explain what is meant dynamic hazard with an example. How is it prevented?
38. W.r.t. JK F/F explain the Iollowing: (i) Characteristic equation (ii) Next state table (iii) state transition diagram (iv)
Excitation table
39. Design a Mealy type FSM Ior serial adder
40. Design a Moore type FSM Ior serial adder