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Fujitsu Semiconductor Europe Factsheet IP & Cores
Fujitsu Semiconductor Europe
Factsheet
IP & Cores

As a leading global ASIC provider and total- solutions provider, Fujitsu delivers innovative solutions that enable customers to differentiate their products and maximise their time-to-market advantage. Together with skilled engineers, this has created the established environment required to develop and produce advanced ASIC designs.

Fujitsu Semiconductor Europe operates its ASIC Design Centres from Langen (Frankfurt) and Munich, Germany and is supported by design centres for ASIC and foundry services throughout the world. Support can therefore be delivered locally, which is increasingly important in today’s complex ASIC designs. By using third-party vendor tools and Fujitsu's own CAD tools, we ensure an innovative, mature design flow, providing customers at the same time with a global network for system development and support.

Fujitsu’s advanced technologies and products include high-end deep sub-micron process (40nm, 65nm, 90nm, 0.13μm, 0.18μm) and standard process technology (0.25μm, 0.35μm). Embedded memory with access time in the pico-second range helps to deliver the system performance required for today’s SoC designs.

The Fujitsu IP portfolio, in combination with our experienced application support, enables customers to achieve right-first-time design and shorter design cycle times.

Sample IP cores include:

Full range of ARM® cores incl. Cortex™

Memory controller: SRAM controller, DRAM controller, DDR1/2/3 controller

Connectivity IPs: USB 2.0/3.0, PCI, I 2 C, Ethernet, HDMI, PCI EXPRESS, SATA

Packaging support options range from small FBGA/QFP to high pin-count, enhanced- performance FCBGA solutions.

to high pin-count, enhanced- performance FCBGA solutions. Seamless Integration of IP Cores into System LSI Mobile

Seamless Integration of IP Cores into System LSI

solutions. Seamless Integration of IP Cores into System LSI Mobile PC Industrial Automotive Fujitsu’s SoC design
Mobile PC Industrial Automotive
Mobile
PC
Industrial
Automotive

Fujitsu’s SoC design methodology and solution platform provides seamless integration of IP cores into system LSI. The IP library consists of diverse sets of re-usable system building blocks

1000 FSL Fab (Fujitsu Semiconductor Ltd.) Outsourced Fab 180-nm (CS80A) 130-nm (CS90A) 90-nm (CS100A) 100
1000
FSL Fab
(Fujitsu Semiconductor Ltd.)
Outsourced Fab
180-nm
(CS80A)
130-nm
(CS90A)
90-nm
(CS100A)
100
65-nm
(CS200A)
40-nm
(CS350LP)
28-nm
(CS450LP)
22-nm
(CS500LP)
10
1999
2001
2003
2005
2007
2009
2011
2013
Gate Length (nm)

CMOS technology roadmap

Year

Factsheet Fujitsu IP & Cores

Selection from Fujitsu IP Portfolio

90nm

 

65nm

 

40nm

 

Standard Cells

 

Standard Cells

 

Standard Cells

 

-

Multiple Vth

-

Multiple Vth

-

Multiple Vth

Memory

 

Memory

 

Memory

 

- SRAM 1RW, 2RW

- SRAM 1RW, 2RW

- SRAM 1RW, 2RW

- RF 1R1W, 2R2W

- RF 1R1W, 2R2W

- RF 1R1W, 2R2W

- Mask ROM

- Mask ROM

- Mask ROM

- OTP

- OTP

- OTP

Standard I/Os

 

Standard I/Os

 

Standard I/Os

 

- 2.5V/3.3V / 5V tolerant

- 3.3V LVCMOS

- 3.3V LVCMOS

- 3.3V PCI

   

- Oscillator

- Oscillator

 

- Oscillator

 

- Analogue

- Analogue

- Analogue

High Speed I/O

 

High Speed I/O

 

High Speed I/O

 

- CDR Tx/Rx

- CDR Tx/Rx

 

- FPD Link Tx+Rx

- FPD Link Tx+Rx

 

- HDMI Tx 1.20Gbps

- HDMI Tx 2.25Gbps

 

- HDMI Tx 2.25Gbps

- HDMI Tx 1.5Gbps

 

- MIPI D-PHY Rx 650Mbps

- MIPI D-PHY Rx 1Gbps

- MIPI D-PHY Rx 1Gbps

- MIPI D-PHY Tx 650Mbps

- MIPI D-PHY Tx 1Gbps

- MIPI D-PHY Tx 1Gbps

- PCI Express 2.5Gbps PHY

- PCI Express 2.5Gbps PHY

 

- SATA 1.5G / 3.0G PHY

- SATA 1.5G / 3.0G PHY

- SATA 1.5G / 3.0G PHY

 

- SubLVDS Rx / Tx 650Mbps

- SubLVDS Rx+Tx 650Mbps

- SubLVDS Rx+Tx 650Mbps

 

- SubLVDS Rx+Tx 1Gbps

 

- LVDS

   

- MDDR, DDR2, DLL

- MDDR, DDR2, DDR3, DLL

 

- MDDR, DDR2, DDR3, DLL

 

- SSTL2, SSTL18

- SSTL2, SSTL18, SSTL15

- SSTL2, SSTL18, SSTL15

- USB2.0 PHY

- USB2.0, USB3.0 PHY

- USB2.0, USB3.0 PHY

APLLs

 

APLLs

 

APLLs

 

- Input frequency up to: 200MHz

- Input frequency up to: 200MHz

- Input frequency up to: 200MHz

- Output frequency: 50MHz

1.6GHz

- Output frequency: 50MHz

1.6GHz

- Output frequency: 400MHz

1.2GHz

- SSCG

- SSCG

- SSCG

- Low power, low jitter

- Low power, low jitter

- Low power, low jitter

ADC / DAC

 

ADC / DAC

 

ADC / DAC

 

- Resolution: 6 - 14-bit

- Resolution: 8 - 14-bit

- Resolution: 12-bit

- Sample rate up to: 1Gsps

- Sample rate up to: 200Msps

- Sample rate up to: 220Msps

Analogue

     

- POR, LDO

- Audio Codec

Cores

 

Cores

 

Cores

 

- ARM7TDMI-S

- ARM7TDMI-S

- ARM7TDMI-S

- ARM926EJ-S, ARM946E-S

- ARM926EJ-S, ARM946E-S

- ARM926EJ-S, ARM946E-S

- ARM1176JZF-S

- ARM1176JZF-S

- ARM1176JZF-S

- Cortex TM -M0, M4, A5, A15

- Cortex-M0, M4, A5, A15

- Cortex-M0, M4, A5, A15

- Cortex-M3, Cortex-R4F

- Cortex-M3, Cortex-R4F

- Cortex-M3, Cortex-R4F

- Cortex-A9

- Cortex-A9

- Cortex-A9

Cortex-R4F - Cortex-M3, Cortex-R4F - Cortex-M3, Cortex-R4F - Cortex-A9 - Cortex-A9 - Cortex-A9 Page 2 of

Page 2 of 4

ARM Processor Roadmap for ASIC/Foundry Service ARM C ore Line- u p ARM1176JZF-S Cortex-A9 Cortex-A15
ARM Processor Roadmap for ASIC/Foundry Service ARM C ore Line- u p ARM1176JZF-S Cortex-A9 Cortex-A15
ARM Processor Roadmap for ASIC/Foundry Service ARM C ore Line- u p ARM1176JZF-S Cortex-A9 Cortex-A15
ARM Processor Roadmap for ASIC/Foundry Service ARM C ore Line- u p ARM1176JZF-S Cortex-A9 Cortex-A15

ARM Processor Roadmap for ASIC/Foundry Service

ARM C ore Line- u p ARM1176JZF-S Cortex-A9 Cortex-A15 Applic ation ARM926EJ-S Cortex-A5 Cortex-R7 Re
ARM C ore Line- u p
ARM1176JZF-S
Cortex-A9
Cortex-A15
Applic ation
ARM926EJ-S
Cortex-A5
Cortex-R7
Re al-Time
ARM946E-S
Cortex-R4F
Cortex-R5
Cortex-M4
Microcontroller
ARM7TDMI-S
Cortex-M3
Cortex-MO
2010
2011
2012
2013
2014
F
u jits u ARM So C Prototyping (FASP)
Reference Design Roa dm a p
ARM1176
A9
A15
ARM926
A5
Available
ARM946
R4F
R5
Designing
ARM7
M3
M0
M4
Planning
2010
2011
2012
2013
2014
ARM926 A5 Available ARM946 R4F R5 Designing ARM7 M3 M0 M4 Planning 2010 2011 2012 2013

Factsheet Fujitsu IP & Cores

Factsheet Fujitsu IP & Cores
Factsheet Fujitsu IP & Cores
Factsheet Fujitsu IP & Cores
Factsheet Fujitsu IP & Cores
FASP-M3 reference design concept Trace TPIU ETM WI C JTAG/ SWJ-DP SWD C ortex-M3 C
FASP-M3 reference design concept
Trace
TPIU
ETM
WI C
JTAG/
SWJ-DP
SWD
C ortex-M3 C ore
HDMAC
C PU Block
Instr u ction
Da t a
System
AHB B u sMa trix
Ahb2Apb
SRAM
SRAM
SRAM
APB
MEMC
(I code)
(D code)
(work)
CRG
EXIU
GPIO
TIMER
UART
WDT
MRBC
External
Clock
FASP-M3 reference design block diagram
Memory
Reset

Fujitsu ARM SoC Prototyping (FASP)

Non application-specific base platform

- Only basic peripherals are implemented

Easy customisation, easy chip development

- By changing the configuration of

Cortex-M3

- By adding or removing peripherals, replace BusMatrix

- By changing interrupt signal assignment

All company and product trade marks and registered trade marks used throughout this literature are acknowledged as the property of their respective owners.

Deliverables

- Reference design of SoC (RTL)

- Simulation environment (Testbench, simulation script)

- Boot code (initialisation of Cortex-M3 and peripherals)

- Documents (Specifications, User Guide, Implementation Guide)

asic.fseu@de.fujitsu.com

http://emea.fujitsu.com/asic