Evm5509a Plus Techref

TMS320VC5509A EVM PLUS Technical Reference
2004
DSP Development Systems
507755-0001 Rev. A October 2004
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
Copyright 2004 Spectrum Digital, Inc.
Contents
Introduction to the TMS320VC5509A EVM PLUS Module . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320VC5509A EVM PLUS Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Boot Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply ......................................................... 1-8 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320VC5509A EVM PLUS. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview .................................................... 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register .............................................. 2-4 2.1.4 DC_REG Register .................................................. 2-4 2.1.5 Version Register .................................................. 2-5 2.1.6 MISC Register ..................................................... 2-5 2.1.7 Interrupt Register ................................................... 2-6 2.1.8 LCD0 Address0 Register ........................................... 2-7 2.2 AIC23 Codec ...................................................... 2-8 2.3 Sychronous DRAM ................................................. 2-9 2.4 Flash Memory .................................................... 2-9 2.5 LEDs and DIP Switches ............................................. 2-9 2.6 Core Power Control ................................................ 2-10 2.7 Current Shunts .................................................... 2-10 2.8 MMC Interface .................................................... 2-11 2.9 LCD Display/Keyboard Interface ...................................... 2-11 2.10 Daughter Card Interface ............................................. 2-12 3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320VC5509A EVM PLUS and its connectors. 3.1 Board Layout ........................................................ 3-2 3.2 Connector Index .................................................... 3-3 3.3 Expansion Connectors ................................................ 3-3 3.3.1 P1, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 P2, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 P3, National Instruments Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.3.1 Analog Probe Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.3.2 National Instruments Protype Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.5 J11, Keypad/display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
A B
3.3.6 J12, SD/MMC Interface ............................................. 3.4 Audio Connectors ..................................................... 3.4.1 J301, Microphone Connector ......................................... 3.4.2 J303, Audio Line In Connector ........................................ 3.4.3 J304, Audio Line Out Connector ...................................... 3.4.4 J302, Headphone Connector ......................................... 3.5 Power Connectors .................................................... 3.5.1 J5, +5V Main Power Connector ...................................... 3.5.2 J6, Optional Power Connector ........................................ 3.6. Miscellaneous Connectors ........................................... 3.6.1 J201, USB Port .................................................... 3.6.2 J7, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 JP1, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 User LEDs ......................................................... 3.8 System LEDs ....................................................... 3.9 User DIP Switch .................................................... 3.10 Reset Switch ....................................................... 3.11 Wake Up Switch ................................................... 3.12 Test Points ........................................................ Schematics .............................................................. Contains the schematics for the TMS320VC5509A EVM PLUS Mechanical Information .................................................. Contains the mechanical information about the TMS320VC5509A EVM PLUS
3-8 3-9 3-9 3-9 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12 3-13 3-13 3-13 3-13 3-14 3-14 3-15 A-1 B-1
About This Manual This document describes the board level operations of the TMS320VC5509A Evaluation Module (EVM PLUS). The EVM PLUS is based on the Texas Instruments TMS320VC5509A Digital Signal Processor. The TMS320VC5509A EVM PLUS is a table top card to allow engineers and software developers to evaluate certain characteristics of the TMS320VC5509A DSP to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways. Notational Conventions
This document uses the following conventions. The TMS320VC5509A will sometimes be referred to as the C55XX. The TMS320VC5509A EVM PLUS will sometimes be referred to as the EVM PLUS. Program listings, program examples, and interactive displays are shown is a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320VC55XX DSP CPU Reference Guide Texas Instruments TMS320VC55XX DSP Peripherals Reference Guide
Table 1: Hardware History Revision A Alpha Release History
Table 2: Manual History Revision A Alpha Release History
Chapter 1 Introduction to the TMS320VC5509A EVM PLUS
Chapter One provides a description of the TMS320VC5509A EVM PLUS along with the key features and a block diagram of the circuit board.
Topic
1.1 1.2 1.3 1.4 1.5 1.6 Key Features Functional Overview Basic Operation Memory Map Boot Mode Settings Power Supply
Page
1-2 1-3 1-4 1-5 1-6 1-8
1-1
Spectrum Digital, Inc

1.0 Key Features The 5509A EVM PLUS is a low-cost standalone development platform that enables users to evaluate and develop applications for the TI C55XX DSP family. The EVM PLUS also serves as a hardware reference design for the TMS320VC5509A DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
LINE OUT HP OUT LINE IN MIC IN
LCD Dis play
AIC23 Codec
1.6V 3.3V
McBSPs
I2C
Memory Exp EMIF

16 16 16
SDRAM
JTAG
5509A DSP
Voltage Reg
5V
Embedded JTAG
1 2 3 4
Peripheral Exp
S3 0123 0123
PWR
USB
GPIO0 GPIO1 GPIO2 GPIO3
MMC
Figure 1-1, Block Diagram VC5509A EVM PLUS The EVM PLUS comes with a full compliment of on-board devices that suit a wide variety of application environments. Key features include: A Texas Instruments TMS320VC5509A-GHH DSP Selectable core voltages (1.2V, 1.4V, 1.6V) Power test points and current shunts An AIC23B stereo codec 8 Mbytes of synchronous DRAM 512 Kbytes of non-volatile Flash memory 4 user accessible LEDs and DIP switches User USB port via VC5509A Software board configuration through registers implemented in CPLD Switch selectable boot options
1-2
USB
Code Composer Debug
5509A on-chip USB
LED
DIP
NI DAQ
CPLD
Flash

128 x 64 display and position keypad Standard expansion connectors for daughter card use National Instruments interface JTAG emulation through on-board JTAG emulator with USB host interface or external emulator MMC card interface Single voltage power supply (+5V) 1.2 Functional Overview of the TMS320VC5509A EVM PLUS The DSP interfaces to external SDRAM, Flash memory and an expansion memory interface connector through its 16-bit External Memory Interface (EMIF). The SDRAM accesses are in 16-bit mode in chip enable 0 memory space. The EMIF provides the necessary refresh signals. The Flash accesses are in 16-bit asynchronous mode in the bottom half of chip enable 1 space. The EMIF signals are brought out to the daughter card expansion connectors which use chip enables 2 and 3. An on-board AIC23B codec allows the DSP to transmit and receive analog signals. I2C is used for the codec control interface and McBSP0 is used for data. Analog I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP2 interfaces to a MultiMedia card. This allows the DSP a way to store off data for video and audio applications. McBSP1 and McBSP2 are routed to the expansion connectors via software configuration registers in the CPLD A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside in the upper half of chip enable 1. The EVM PLUS includes 4 LEDs and 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. A wake-up push button allows the DSP to be interrupted, to wake up the DSP when it is in sleep or idle mode. An included 5V external power supply is used to power the board. On-board voltage regulators provide the 1.6V to 1.2V DSP core voltage, 3.3V digital and 3.3V analog voltages. A voltage supervisor monitors the internally generated voltage, and will hold the board in reset until the supplies are within operating specifications and the reset button is released. 1-3

Code Composer communicates with the EVM PLUS through an embedded JTAG emulator with a USB host interface. The EVM PLUS can also be used with an external emulator through the external JTAG connector. 1.3 Basic Operation The EVM PLUS is designed to work with TIs Code Composer Studio (CCS) development environment. Code Composer communicates with the board through the on-board JTAG emulator, or an external emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. After the install is complete, follow these steps to run Code Composer. The EVM PLUS must be fully connected to launch Code Composer Studio. 1) Connect the included power supply to the EVM PLUS. 2) Connect the EVM PLUS to your PC with a mini USB cable (also included). 3) Set up Code Composer Studio 4) Launch Code Composer from its icon on your desktop. Detailed information about the CCS including a tutorial, examples and reference material is available in the EVM PLUSs help file. You can access the help file through Code Composers help menu.
1-4

1.4 Memory Map The C55x family of DSPs has a unified program and data space with a separate distinct I/O space dedicated to on-chip peripheral registers. For a number of reasons (historical and technical) though, program code is addressable in 8-bit bytes while data is addressable in 16-bit words. Both programs and data can reside anywhere in the unified memory space. The address reach of the 5509A is 24 bits for a total of 16 megabytes (8 bits/byte) or alternatively 8 megawords (16 bits/word). The external memory interface controller (EMIF) divides the address space into 4 equally sized chip enable (CE) spaces when dealing with external memory. The lower 21 address bits are driven on the EMIF as address lines while the top 3 are decoded and driven as the chip enable for that particular region. Word C55x Family Memory Type Address 0x000000 Memory Mapped Registers 0x000030 Internal Memory (DARAM) 0x008000 0x028000 External CE0 0x200000 External CE1 0x400000 0x600000 External CE2 External CE3 Internal Memory (SARAM)
5509A EVM MMR
Internal Memory 0x028000 0x200000 0x3F0000
SDRAM Flash CPLD Daughter Card
Figure 1-2, Memory Map, VC5509A EVM PLUS The figure above shows a generic memory space map for a C55x family processor and a second map specific to the components on a 5509A EVM PLUS. The SDRAM occupies chip enable 0. The Flash and memory mapped registers of the CPLD share CE1 with the Flash in the lower section and the CPLD in the upper section of memory. Internal memory on the 5509A starts at address 0 and takes precedence over any external memory. The DSPs memory mapped registers occupy the first few bytes of the address space, followed by internal DARAM and a larger amount of internal SARAM. DARAM stands for Dual-Access RAM and is differentiated from SARAM (Single-Access RAM) in that two concurrent memory operations can be performed on the same block rather than one. 1-5

Internal memory is divided into blocks, each capable of supporting independent operations. Performance can be optimized by placing code and data so that instructions have their operands spread to different blocks so no stalls are introduced due to contention for one specific block. DARAM blocks are the most precious because their dual-ported nature allows a higher rate of operation. There are 32K words of DARAM and 96K words of SARAM on a 5509A for a total of 128K words of internal memory.
1.5 Boot Mode Settings The 5509A EVM PLUS has 4 position switch that define the DSPs boot configuration at reset. The figure below shows this switch. GP0 GP1 GP2 1 Figure 1-3, JP4, DSP Boot Configuration - Default Setting The switches drive signals that directly correspond to the input on one of the DSPs GP[3-0] configuration pins. If the switch is on, the signal is driven to a logic 0. If the switch is off, the signal is driven to a logic 1. The 5509A can boot from asynchronous memory mapped in CE1 (Flash on the 5509A EVM PLUS board), serial EEPROMs connected to McBSP0 or a standard serial port on McBSP0. To boot from a particular device you must pack the object code into a C55x bootloader formatted table and store it in the device. When you set the appropriate BOOTM jumpers and power cycle the board, the 5509A will parse the bootloader table, load the code into memory and begin execution at the entry point specified in the bootloader table. The bootloader functionality is contained in on-chip ROM. At reset, the 5509A usually begins execution from the ROM and runs the appropriate bootloader based on the BOOTM pins. In the special case where BOOTM[3:0] are all 0, the internal ROM is not active and execution will begin from external memory at the reset vector (0xFFFF00). 1-6 GP3

Table 1: VC5509A EVM PLUS Boot Load Options
GPIO0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GPIO1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 GPIO2 0 0 1 1 0 0 1 1 0 GPIO3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Reserved Serial SPI EPROM boot (24 bit address) via McBSP0 USB I2C EEPROM (7 bit address) Reserved HPI - multiplexed mode HPI - non multiplexed mode Reserved Execute from 16-bit wide asychronous memory (on CE1- space) Serial SPI EPROM boot (16 bit address) via McBSP0 8-bit wide asychronous memory (on CE1- space) 16-bit wide asychronous memory (on CE1- space) Reserved Reserved Standard serial boot from McBSP0 (16-bit data) Standard serial boot from McBSP0 (8-bit data) BOOT MODE PROCESS SUPPORTED ON EVM No No Yes No No No No No Yes Yes No Yes * No No No No
* default on EVM
1-7

1.6 Power Supply The EVM PLUS operates from a single +5V external power supply connected to the main power input (J5). Internally, the +5V input is converted into +1.6V and +3.3V. The +1.6V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The power connector is a 2.5mm. barrel-type plug. The core voltage on the EVM PLUS is selectable based on the output of GPIO5 and GPIO6 or CPLD control registers. If GPIO5 and GPIO6 are high or configured as an input the core voltage will remain at +1.6V. If GPIO5 and GPIO6 are driven low the voltage will drop to +1.2V. The table below shows the 3 core voltage levels available on the VC5509 EVM PLUS. Table 2: Core Voltage Level Select GPIO6 0 0 1 1 GPIO5 0 1 0 1 Core Voltage Selected 1.2V 1.4V 1.4V 1.6V
There are three power test points on the EVM PLUS at JP2, JP3 and JP6. All board current passes through JP2 (the +5V supply). All DSP core current passes through JP3. JP6 allows measurement of DSP I/O pins. To measure the current passing connect the pins with a voltage measuring device. A current shunt is also supplied to amplify this voltage. This allows voltage meters to more accurately track current changes. The EVM PLUS also provides +3.3V for the daughter card. It is also possible to provide the daughter card with +12V and -12V when the external power connector is used.
1-8
Chapter 2 Board Components
This chapter describes the operation of the major board components on the TMS320VC5509A EVM PLUS.
Topic
2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 CPLD (Programmable Logic) CPLD Overview CPLD Registers USER_REG Register DC_REG Register Version Register MISC Register Interrupt Register LCD0 Address0 Register AIC23 Codec Sychronous DRAM Flash Memory LEDs and DIP Switches Core Power Control Current Shunts MMC Interface LCD Display/Keyboard Interface Daughter Card Interface
Page
2-2 2-2 2-3 2-4 2-4 2-5 2-5 2-6 2-7 2-8 2-9 2-9 2-9 2-10 2-10 2-11 2-11 2-12
2-1

2.1 CPLD (Programmable Logic) The C5509A EVM PLUS uses an Altera EPM3128TC100-10 Complex Programmable Logic Device (CPLD) device to implement: 11 Memory-mapped control/status registers that allow software control of various board features. Address decode and memory access logic. Control of the daughter card interface and signals. Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview The CPLD logic is used to implement functionality specific to the 5509A EVM PLUS. Your own hardware designs will likely implement a completely different set of functions or take advantage of the DSPs high level of integration for system design and avoid the use of external logic completely. The EMIF on the 5509A can support several heterogeneous memory types with a glueless interface. However, to reserve CE2 and CE3 for potential daughter-card use on the 5509A EVM PLUS, CE1 is split to include the Flash in its bottom half and the CPLD memory-mapped registers in its top half. The address decode logic is used to implement the split. The CPLD implements simple random logic functions that eliminate the need for additional discrete devices. In particular, the CPLD aggregates the various reset signals coming from the reset button and power supervisors and generates a global reset. The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the 5509A EVM PLUS). The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and are included with the 5509A EVM PLUS on the installation CD-ROM.
2-2

2.1.2 CPLD Registers There are 11 DSP CPLD registers mapped into the DSPs lower CE1 address space starting at address 0x3F0000. Since the CPLD decoder only uses part of the address for decoding, the registers will be mirrored within the space. The table below shows the bit definitions for the 11 registers in CPLD. Table 1: CPLD Register Definitions
Addr LSB A4-A1
0000
Name
USER_REG
Bit 7
USR_SW3 R DC_DET R
Bit 6
USR_SW2 R 0
Bit 5
USR_SW1 R DC_STAT1 R
Bit 4
USR_SW0 R DC_STAT0 R
Bit 3
USR_LED3 R/W 0(Off) DC_RST R 0(No reset)
Bit 2
USR_LED2 R/W 0(Off) 0
Bit 1
USR_LED1 R/W 0(Off) DC_CNTL1 R/W 0(Low)
Bit 0
USR_LED0 R/W 0(Off) DC_CNTL0 R/W 0(Low)
0001
DC_REG
0010 0011 0100 0101 0110
Reserved Reserved VERSION Reserved MISC VCORE_CTL 1 VCORE_CTL 0 Reserved VCORE_SEL CPLD REGISTERS 0 GPIO 1 BIT 6 & 7 THIS REG Reserved SHIFT DATA4 SHIFT DATA4 Reserved R Reserved TIN0 IN/OUT R/W (0 INPUT) McBSP2 ON/OFF Board R/W 0 (Onboard) WAKUP INT1 SHIFT DATA1 SHIFT DATA1 Reserved R McBSP0 SROM/ AIC23 Board R/W 0 (SROM) WAKEUP INT0 SHIFT DATA0 SHIFT DATA0 Reserved R CPLD_VER[3.0] R 0 BOARD VERSION[2.0] R
0111 1000 1001 1010
INT REG LCD0 Address0 LCD1 Address0 5502EVM Misc
Reserved SHIFT DATA7 SHIFT DATA7 LCD BUSY R 1 BUSY
Reserved SHIFT DATA6 SHIFT DATA6 LCD_RESET R/W 0
Reserved SHIFT DATA5 SHIFT DATA5 Reserved R
WAKEUP INT3 SHIFT DATA3 SHIFT DATA3 Reserved R
Reserved SHIFT DATA2 SHIFT DATA2 Reserved R
2-3

2.1.3 USER_REG Register USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or off to allow the user to interact with the 5509A EVM PLUS. The DIP switches are read by reading the top 4 bits of the register and the LEDs are set by writing to the low 4 bits. Table 2: CPLD USER_REG Register
Bit 7 6 5 4 3 2 1 0 Name USER_SW3 USER_SW2 USER_SW1 USER_SW0 USER_LED3 USER_LED2 USER_LED1 USER_LED0 R/W R R R R R/W R/W R/W R/W Description User DIP Switch 3(1 = Off, 0 = On) User DIP Switch 2(1 = Off, 0 = On) User DIP Switch 1(1 = Off, 0 = On) User DIP Switch 0(1 = Off, 0 = On) User-defined LED 3 Control (0 = Off, 1 = On) User-defined LED 2 Control (0 = Off, 1 = On) User-defined LED 1 Control (0 = Off, 1 = On) User-defined LED 0 Control (0 = Off, 1 = On)
2.1.4 DC_REG Register DC_REG is used to monitor and control the daughter card interface. DC_DET detects the presence of a daughter card. DC_STAT and DC_CNTL provide simple communications with the daughter card through readable status lines and writable control lines. The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset. Table 3: DC_REG Register
Bit 7 6 5 4 3 2 1 0 Name DC_DET 0 DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0 R/W R R R R R/W R R/W R/W Description Daughter Card Detect (1= Board detected) Always 0 Daughter Card Status 1 (0=Low, 1 = High) Daughter Card Status 0 (0=Low, 1 = High) Daughter Card Reset (0=No Reset, 1 = Reset) Always zero Daughter Card Control 1(0 = Low, 1 = High) Daughter Card Control 0(0 = Low, 1 = High)
2-4

2.1.5 VERSION Register The VERSION register contains two read only fields that indicate the BOARD and CPLD versions. This register will allow your software to differentiate between production releases of the 5509A EVM PLUS and account for any variances. This register is not expected to change often, if at all. Table 4: Version Register Bit Definitions
Bit # 7 6 5 4 3 2 1 0 Name CPLD_VER3 CPLD_VER2 CPLD_VER1 CPLD_VER0 0 5509A EVM PLUS_VER2 5509A EVM PLUS_VER1 5509A EVM PLUS_VER0 R/W R R R R R R R R Description Most Significant CPLD Version Bit CPLD Version Bit CPLD Version Bit Least Significant CPLD Version Bit Always 0 Most Significant 5509A EVM PLUS Board Version Bit 5509A EVM PLUS Board Version Bit Least Significant 5509A EVM PLUS Board Version Bit
2.1.6 MISC Register The MISC register is used to provide software control for miscellaneous board functions. On the 5509A EVM PLUS, the MISC register controls how auxiliary signals are brought out to the daughter-card connectors. The TIN0 bit is used to select whether the DSPs TIN0 (timer) signal is connected to the peripheral expansion connector as inputs or outputs. The expansion connector has separate pins for inputs and outputs so each signal must be routed to one of two physical pins. A 0 indicates that the signal should be connected to the input pin on the expansion connector. A 1 indicates that it should be connected to the output pin.
2-5

McBSP0SEL and McBSP2SEL control the McBSP0 and McBSP2. Since McBSP0 is used for Serial Boot loading the McBSP.dr pin is routed to the serial ROM at power up. When McBSP0 is used for AIC23B operation this bit must be set to a 1. McBSP2 is used for MMC operation at power up. Setting this bit to a 1 the McBSP2 is routed to the daughter card connector. The power-on state of these bits (both 0s) represents that situation. Setting the corresponding bit for McBSP2 to 1 enables the McBSP to the expansion daughter-card instead interface. Table 5: MISC Register
Bit 7 6 5 4 3 2 1 0 Name VCORE_CTL1 VCORE_CTL0 Reserved VCORE_SEL Reserved TINSEL0 MCBSP2SEL MCBSP0SEL R/W R/W R/W R R/W R R/W R/W R/W TIN0 in/out on daughter card (0 = input, 1 = output) McBSP2 on/off board (0 = on-board, 1 = off-board) McBSP0 on/off board (0 = SROM, 1 = AIC23B) 0 = GPIO, 1= CPLD Reg bits 6 & 7 Description Selects Voltage Control 1 Selects Voltage Control 0
2.1.7 Interrupt Register The EVM allows interrupts to be generated from the Wake Up switch, S4. These interrupts can be routed to various pins on the VC5509A DSP. The interrupt register does this routing. When the corresponding bit is set to a 1 the DSP will be interrupted by the Wake Up switch. The interrupts to choose from are DSP interrupts 0, 1, or 3 as shown in the table below. Table 6: Interrupt Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Wakeup Int3 Reserved Wakeup Int1 Wakeup Int0
2-6

2.1.8 LCD0 Address0 Register The Liquid Crystal Display (LCD) is a write only interface. It is interfaced via an 8-bit shift register. Two locations are used when interfacing the LCD panel. Allowing the address bit of the interface to be directly programmed. The shift clock frequency is 3 megahertz. Writing register LCD0 sets the LCD address line A0 to 0. Writing register LCD1 sets the LCD address line A0 to 1. The write operation to either of these locations starts an internal shift register serializing the data into an 8-bit sequence to the displays. The table below shows the relationship of the DSP data bits to the LCD data bits. Table 7: LCD Interface D7 LCD D7 D6 LCD D6 D5 LCD D5 D4 LCD D4 D3 LCD D3 D2 LCD D2 D1 LCD D1 D0 LCD D0
The figure below shows the LCD data transfer timing. the CPLD automatically generates this timing.
LCDCLK LCD Address LCD Data D7 D6 D5 D4 D3 D2 D1 D0
Figure 2-3, LCD Data Transfer Timing After any write operations the CPLD sets the LCD BUSY bit in the EVM interface Register as the output is being serialized. The user should check this bit prior to starting another write operation. When LCD BUSY is high, the LCD shift register is busy, when is low the shift register is ready.
2-7

2.2 AIC23 Codec The 5509A EVM PLUS uses a Texas Instruments AIC23B (part #TLV320AIC23B) stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line and headphone outputs so the user can hear the output. The codec communicates using I2C and a McBSPs. The I2C controls the codecs internal configuration registers. The McBSP is used to send and receive digital audio samples. The control channel is typically only used when configuring the codec, it is generally idle when audio data is being transmitted, McBSP0 is used as the bi-directional data channel. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The 5509A EVM PLUS examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The preferred serial format is DSP mode which is designed specifically to operate with the McBSP ports on TI DSPs. The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB sample rate mode, named because many USB systems use a 12MHz clock and can use the same clock for both the codec and USB controller. The internal sample rate generate subdivides the 12MHz clock to generate common frequencies such as 48KHz, 44.1KHz and 8KHz. The sample rate is set by the codecs SAMPLERATE register. The figure below shows the Coded interface on the VC5509A EVM PLUS.
AIC23 Codec
0 1 2 3 4 5 6 7 8 9 15 LEFTINVOL RIGHTINVOL LEFTHPVOL RIGHTHPVOL ANAPATH DIGPATH POWERDOWN DIGIF SAMPLERATE DIGACT RESET
I2C
SCL0 SDA0 Control I2 C Format Digital SCLK SDIN
Control Registers
MIC IN
LINE IN
Analog LINE OUT MIC IN LINE IN
DR0 FSX0 CLKR0 CLKX0 FSR0 DX0
McBSP0
DSP Format
DOUT LRCOUT BCLK LRCIN DIN
ADC
DAC
LINE OUT HP OUT HP OUT
Figure 2-1, TMS320VC5509A EVM PLUS CODEC INTERFACE
2-8

2.3 Synchronous DRAM The 5509A EVM PLUS uses an industry standard 32 megabit Synchronous SDRAM. It uses a 16-bit interface and is used with a 100MHz external memory clock. Since the DSP runs at 200MHz, the EMIF must be programmed to use the SDRAM at half the core clock rate. The SDRAM occupies both chip enable 0 and 1. It appears on both chip enables because it is twice the size of a single chip enable space. Since the Flash and CPLD use chip enable 1, the 5509A EVM PLUS examples configure CE1 as asynchronous memory for their use and the SDRAM on CE1 is invisible. SDRAM must be constantly refreshed to maintain the integrity of its contents. This SDRAM must update one row every 15.6 microseconds to meet its minimum requirements. The EMIF can be programmed to automatically generate refresh signals based on this time period.
2.4 Flash Memory The 5509A EVM PLUS provides 256K x 16-bit words of external Flash memory. The board itself is pinned out to allow expansion to 1M x 16 parts. The Flash is mapped into CE1 space because that is where the 16-bit asychronous bootloader looks for a boot image when booting from the Flash. The space is shared by the CPLD, but the CPLD timings are subsetted by the Flash so the Flash is the critical factor in configuring CE1. The Flash itself is a 70ns device but some additional delays are incurred in the CPLD logic that separates the Flash and CPLD registers. Because of this, the EMIF should be programmed for an access time of at least 100ns.
2.5 LEDs and DIP Switches The 5509A EVM PLUS includes 4 software accessible LEDs (DS1-DS4) and DIP switches (S2) that provide the user a simple form of input/output. Both are accessed through the CPLD USER_REG register.
2-9

2.6 Core Power Control The C5509A EVM PLUS uses two transistors to modify the feedback to the TPS62000 regulator used to supply the DSPs core voltage. These two transistors form a voltage divider on the feedback to allow the core voltage to switch from 1.6 volts to 1.4 volts to 1.2 volts. Control of the feedback can be done in 2 ways. The default mechanism is with GPIO5 and GPIO6 of the DSP. The alternative method is to use the 2 bits VCORE_CTL1 and VCORE_CTL0 in the CPLD MISC register. VCORE_SEL in the MISC register determines which mode is used. At power up the register is set to 0 for GPIO mode when VCORE_SEL is set to a 1 the bits 6 and 7 control the voltage control.
2.7 Current Shunts The C5509A EVM PLUS has 3 shunt devices to convert the small currents of the core, I/O and board currents to voltages. These voltages are then driven into an op-amp which directly interfaces to the National Instruments I/O connector. The shunt resistance, shunt gain, and op-amp gain are shown in the table below. Table 8: Current Shunts
Shunt Resistance DSP Core DSP I/O EVM 0.1 0.1 0.025 Shunt Output Resistance 50K 100K 100K Op-Amp Gain 3 3 3 Total Gain 150 300 300 Volts per MA .03 volts .03 volts .0075 volts Typical Current 150 MA 5 MA 400 MA Typical Output
To determine the formula for output voltage to the input current we calculate the value in stages. An example is shown below. The voltage going into the shunt resistor is derived from:
V = IR
So for the core current of 1 MA. we have:

V = .001 amp x .1 ohm = .0001
The internal resistance of the shunt current device is 1K ohm. The output is basically a constant current source with a load resistance of 100K(see table above), with this value gain is 100 regardless of the input shunt resistance. So for 1 MA. we have .001 x .1 x 100 at the output of the current shunt amplifier. This is driven into a non-inverting output amplifier with a gain of 3 so we have .001 x .1 x 100 x 3 for .03 volts per milliampere.
2-10

2.8 MMC Interface The VC5509A EVM PLUS supports a multi media card on McBSP2. This port can also be routed to the expansion connector. When bit 1 in register 5 (MISC Reg) is 0 (default) McBSP2 is used for the MMC Interface. When bit 1 register 5 (MISC Reg) is 1 McBSP2 is routed to the expansion daughter connector.
2.9 LCD Display/Keyboard Interface The C5509A EVM Interface Register implements specific logic for the C5509A EVM. The bits used in this register and their function are described in the table below. Table 9: C5509A EVM PLUS Interface
Bit 7 6 5 4 3 2 1 0 Name LCD Busy LCD Reset Reserved Reserved Reserved Reserved Reserved Reserved R/W R R/W R R R R R R Description 0 = busy, not ready, 1 = not busy, ready 0 = removes reset from LCD, 1 = forces LCD into reset
LCD Busy indicates the status of the CPLD implemented shift register which interfaces to the LCD panel. A 1 logic level indicates the shift register is busy, A 0 logic level indicates the shift register is ready. LCD Reset allows the LCD Reset bit to be toggled under software control. A 1 logic level forces the LCD panel into reset. A 0 logic level removes the LCD reset to normal state.
2-11

2.10 Daughter Card Interface The 5509A EVM PLUS provides three expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their 5509A EVM PLUS platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for memory and peripherals. The memory connector provides access to the DSPs asynchronous EMIF signals to interface with memories and memory mapped devices. It supports byte addressing. The peripheral connector brings out the DSPs peripheral signals like McBSPs, timers, and clocks. Both connectors provide power and ground to the daughter card Most of the expansion connector signals are buffered so that the daughter card cannot directly influence the operation of the 5509A EVM PLUS board. The use of TI low voltage, 5V tolerant buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be used on the daughter card. Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET and DC_DET exist and are accessible through the CPLD DC_REG register. The 5509A EVM PLUS also multiplexes the McBSP2 for on-board or external use. This function is controlled through the CPLD MISC register. The timer signals on the peripheral expansion connector have connections for both inputs and outputs. since the VC5509A does not have separate timer inputs and outputs, the CPLD is used to select whether the input or output pin should be connected to the timer. This selection is also controlled through the CPLD MISC register.
2-12
Chapter 3 Physical Description
This chapter describes the physical layout of the TMS320VC5509A EVM PLUS and its connectors.
Topic
3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.3.1 3.3.3.2 3.3.4 3.3.5 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8 3.9 3.10 3.11 3.12 Board Layout Connector Index Expansion Connectors P1, Memory Expansion Connector P2, Peripheral Expansion Connector P3, National Instruments Interface Analog Probe Connector National Instruments Prototype Header J11, Keypad/Display Interface J12, SD/MMC Interface Audio Connectors J301, Microphone Connector J303, Audio Line In Connector J304, Audio Line Out Connector J302, Headphone Connector Power Connectors J5, +5 Volt Connector J6, Optional Power Connector Miscellaneous Connectors J201, Mini USB Connector J7, External JTAG Connector JP1, PLD Programming Connector User LEDs System LEDs User DIP Switch Reset Switch Wake Up Switch Test Points
Page
3-2 3-3 3-3 3-4 3-5 3-6 3-7 3-7 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12 3-13 3-13 3-13 3-13 3-14 3-14 3-15
3-1

3.1 Board Layout The VC5509A EVM PLUS is a 8.25 x 4.5 inch (210 x 115 mm.) multi-layer board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the VC5509A EVM PLUS.
J301
J303
J304
J302
J11
P1
P2
JP3
J8
JP2
JP4-8
P3
J6
J5
J201
DS5 S1 J12,J13
S4 DS6
J7
DS1-4
S2
J10
JP9
Figure 3-1, TMS320VC5509A EVM PLUS
3-2

3.2 Connector Index The TMS320VC5509A EVM PLUS has many connectors which provide the user access to the various signals on the DSK. Table 1: TMS320VC5509A EVM PLUS Connectors
Connector P1 P2 P3 J301 J303 J304 J302 J5 J6 * J7 J8 J11 J12 J201 JP1 5 10 # Pins 80 80 68 2 2 2 2 2 4 14 24 16 Memory Peripheral National Instruments Interface Microphone Line In Line Out Headphone +5 Volt Optional Power Connector External JTAG National Instruments Prototype Header Keypad/Display Interface MultiMedia Card USB Port CPLD Programming Function
Note: * Not populated 3.3 Expansion Connectors The TMS320VC5509A EVM PLUS supports two expansion connectors that follow the Texas Instruments interconnection guidelines. The expansion connector pinouts are described in the following two sections. The two expansion connectors are all 80 pin 0.050 x 0.050 inches low profile connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors are designed for high speed interconnections because they have low propagation delay, capacitance, and cross talk. The connectors present a small foot print on the DSK. Each connector includes multiple ground, +5V, and +3.3V power signals so that the daughter card can obtain power directly from the DSK. The peripheral expansion connector additionally provides both +12V and -12V to the daughter card. The recommended mating connector, whose part number is TFM-140-32-S-D-LC, is a surface mount connector that provides a 0.465 mated height. Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin
3-3

3.3.1 P1, Memory Expansion Connector Table 2: P1, Memory Expansion Connector
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 Signal Name +5 Volts A20 A18 A16 A14 GND A12 A10 A8 A6 +5 Volts A4 A2 Reserved BE1n GND Reserved Reserved Reserved Reserved +3.3 Volts Reserved Reserved Reserved Reserved GND D15 D13 D11 D9 GND D7 D5 D3 D1 GND REn OEn CE3n GND O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z O O O O O O O O O I/O/Z O O O O O O O O O O O O O Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 Signal Name +5 volts A19 A17 A15 A13 GND A11 A9 A7 A5 +5 Volts A3 A1 Reserved BE0n GND Reserved Reserved Reserved Reserved +3.3 Volts Reserved Reserved Reserved Reserved GND D14 D12 D10 D8 GND D6 D4 D2 D0 GND WEn RDYn CE2n GND O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z O O O I O O O O O I/O/Z O O O O O O O O O O O O O
3-4

3.3.2 P2, Peripheral Expansion Connector Table 3: P2, Peripheral Expansion Connector
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 GND INT1n RESERVED RESERVED RESETn GND DC_CNTL1 DC_STAT1 INT3n RESERVED RESERVED RESERVED DETECTn GND GND I O O O O O I I O I Signal Name +12 Volts * GND +5 Volts GND +5 Volts RESERVED RESERVED RESERVED RESERVED +3.3 Volts CLKX1 FSX1 GND CLKR1 FSR1 GND CLKX2 FSX2 GND CLKR2 FSR2 GND TOUT0 INT0n O I/O/Z I/O/Z O I/O/Z I/O/Z O I/O/Z I/O/Z O I/O/Z I/O/Z O Z I I/O/Z O O O O O Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 INT4n RESERVED GND DC_CNTL0 DC_STAT0 RESERVED RESERVED RESERVED RESERVED GND CLKOUT GND O O O O O I I GND O DX2 GND RESERVED DR2 GND TIN0 INT2n Z O I I O/Z O Signal Name -12 Volts * GND +5 Volts GND +5 Volts RESERVED RESERVED RESERVED RESERVED +3.3 Volts RESERVED DX1 GND RESERVED DR1 GND I O O/Z O O I/O/Z O O O O O
3-5

3.3.3 P3, National Instruments Interface The VC5509A EVM PLUS provides a direct connection to the National Instruments series of instrumentation products. Only a limited selection of the available inputs and outputs are used by the EVM at this time. Some of the spare signals are routed to the test headers for prototyping use. Note that it is important to realize that the voltages for the National Instruments products and the EVM products often require level translation. Do not connect signals to this interface prior to familiarizing yourself with these requirements. The table below shows the signals on this interface. Table 4: P3, National Instruments Interface
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name FREQ_OUT GPCTR0_OUT PFI9/GPCTR0_GATE DGND PFI6/WFTRIG PFI5/UPDATE DGND +5 v DGND PFI1/TRIG2 PFI0/TRIG1 DGND DGND +5 V DGND DIO6 DIO1 DGND DIO4 EXTREF DAC1OUT DAC0OUT ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACG8 I/O/Z EVM Function Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal Name DGND DGND PFI8/GPCTR0_SOURCE PFI7/STARTSCAN DGND GPCTR1_OUT PFI4/GPCTR1_GATE PFI3/GPCTR1_SOURCE PFI2/CONVERT DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 I/O/Z EVM Function
3-6

3.3.3.1 Analog Probe Connectors Four connectors are available from the National Instruments connector for analog probing. The two inputs and two outputs are shown in the table below. The signal names on each pin are shown in the table below. Table 5: Analog Probe Connectors
Connector JP4, Pin 1 JP4, Pin 2 JP5, Pin 1 JP5, Pin 2 JP6, Pin 1 JP6, Pin 2 JP7, Pin 1 JP7, Pin 2 Signal Name P3 Analog Out 0 Ground P3 Analog Out 1 Ground P3 Analog In 6 Ground P3 Analog In 7 Ground
3.3.3.2 National Instruments Prototype Header The National Instruments Prototype Header is 2 x 12 double row header. This allows users to prototype signals to be feedback into the National Instruments interface. The signal names on each pin are shown in the table below. Table 6: National Instruments Prototype Header
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 Signal Name P3 Pin 1 P3 Pin 37 P3 Pin 38 P3 Pin 40 P3 Pin 42 P3 Pin 10 P3 Pin 45 P3 Pin 47 P3 Pin 49 P3 Pin 51 P3 Pin 60 P3 Pin 28 I/O/Z Pin # 2 4 6 8 10 12 14 16 18 20 22 24 Signal Name P3 Pin 2 P3 Pin 3 P3 Pin 5 P3 Pin 6 P3 Pin 41 P3 Pin 43 P3 Pin 11 P3 Pin 46 P3 Pin 48 P3 Pin 16 P3 Pin 19 P3 Pin _____ I/O/Z
3-7

3.3.4 J11, Keypad/Display Interface Connector J11 is a 16 pin interface to the Spectrum Digital keypad/display module. The signals on this connector are shown in the table below. Table 7: J11, Keypad/Display Interface
Pin # 1 3 5 7 9 11 13 15 Signal Name +3.3 volts Analog In 0 LCD_Data LCD_Reset Ground I2C Data I2C CLK +3.3 Volts I/O/Z Pin # 2 4 6 8 10 12 14 16 Signal Name +3.3 Volts Analog In 1 LCD_Address LCD_CLK Ground Ground Ground +3.3 Volts I/O/Z
The display is interfaced via the CPLD in an SPI type format. The switches and potentiometers are connected to I2C analog to digital converters and also supplied as analog voltages to the VC5509As analog inputs. For more information on the display please reference the Universal Display Technical Reference Manual.
3.3.5 J12, SD/MMC Interface Connector J12 is a 12 pin interface to MMC module. The signals on this connector are shown in the table below. Table 8: J12, SD/MMC Interface
Pin # 1 3 5 7 9 11 Signal Name MMC.DAT3 Ground MMC.CLK MMC.DAT0 MMC.DAT2 Ground I/O/Z Pin # 2 4 6 8 10 12 Signal Name MMC.CMD +3.3 Volts Ground MMC.DAT1 Write protect - N/C Media Present - N/C I/O/Z
3-8

3.4 Audio Connectors The VC5509A EVM PLUS has 4 audio connectors. They are described in the following sections. 3.4.1 J301, Microphone Connector The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below.
Ground Microphone In Microphone Bias Figure 3-2, Microphone Stereo Jack
3.4.2 J303, Audio Line In Connector The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 3-3, Audio Line In Stereo Jack
3-9

3.4.3 J304, Audio Line Out Connector The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line Out Left Line Out Figure 3-4, Audio Line Out Stereo Jack
3.4.4 J302, Headphone Connector Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below .
Ground Right Headphone Left Headphone Figure 3-5, Headphone Jack
3-10

3.5 Power Connectors The VC5509A EVM PLUS has 2 power connectors. They are described in the following sections.
3.5.1 J5, +5 Volt Connector Power (+5 volts) is brought onto the TMS320VC5509A EVM PLUS via the J5 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The A diagram of J5 is shown below. +5V J5 Ground PC Board Front View Figure 3-6, TMS320VC5509A EVM PLUS Power Connector 3.5.2 J6, Optional Power Connector Connector J6 is an optional power connector. It will operate with the standard personal computer power supply. To populate this connector use a Molex #15109-0410 or Tyco #174552-1. The table below shows the voltages on the respective pins. Table 9: J6, Optional Power Connector
Pin # 1 2 3 4 Voltage Level +12 Volts -12 Volts Ground +5 Volts
WARNING ! Do not plug into J5 and J6 at the same time.
3-11

3.6 Miscellaneous Connectors The VC5509A EVM PLUS has 3 additional connectors to aid the user in developing with this product. They are described in the following sections.
3.6.1 J201, Mini USB Connector Connector J201 provides a Universal Serial Bus (USB) Interface to the embedded JTAG emulation logic on the DSK. This allows for code development and debug without the use of an external emulator. The signals on this connector are shown in the below. Table 10: J201, USB Connector
Pin # 1 2 3 4 5 6 USB Signal Name USBVdd D+ DUSB Vss Shield Shield
3.6.2 J7, External JTAG Connector The TMS320VC5509A EVM PLUS is supplied with a 14 pin header interface, J7. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown figure 3-6 below.
TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0
1 3 5 7 9 11 13
2 4 6 8 10 12 14
TRSTGND no pin (key) GND GND GND EMU1
Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal
Figure 3-7, JTAG INTERFACE
3-12

3.6.3 JP1, PLD Programming Connector This connector interfaces to the Altera CPLD, U2. It is used in the in the factory for the programming of the CPLD. This connector is not intended to be used outside the factory.
3.7 User LEDs The VC5509A EVM PLUS provides 4 LEDs which show selftest status at power up and are available for application programs or demonstrations. The LEDs are accessed via the user register of the CPLD. For more information on the control of the LEDs refer to the user register section of the CPLD.
3.8 System LEDs TheTMS320VC5509A EVM PLUS has three system light emitting diodes (LEDs). These LEDs indicate various conditions on the DSK. These function of each LED is shown in the table below. Table 11: System LEDs
Reference Designator DS6 DS5 DS201 Color Green Orange Green Function USB Emulation in use. When External JTAG Emulator is used this LED is off. RESET Active USB Active, Blinks during USB data transfer On Signal State 1 1 1
3.9 User DIP Switch S2 is a 4 position DIP switch to be used by application and demonstration programs. The switch is mapped into the CPLD and can be accessed via the User register. For more details see the section on CPLD register 2, User register.
3-13

3.10 Reset Switch There are three resets on the TMS320VC5509A EVM PLUS. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320VC5509A. External sources which control the reset are push button S1, and the on board embedded USB JTAG emulator.
3.11 Wake Up Switch S4 is a Wake Up switch to the DSP. When the DSP is in idle mode the switch can generate an interrupt to wake up the DSP. See the section on the CPLD Interrupt register to enable interrupts for the Wake Up switch
3-14

3.10 Test Points The VC5509A EVM PLUS has thirteen (13) test points. Their position is shown in the diagram below. TP8 TP5,TP4,TP1 TP13,TP3 TP12 TP11 TP6,TP7
TP9,TP10 Figure 3-x, TMS320VC5509A EVM PLUS Test Points The table below shows the signals present on each test point. Table 12: TMS320VC5509A EVM Plus Test Points
Test Point # TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 +5 Volt Current Shunt Output +3.3 Volt Current Shunt Output DSP Core Current Shunt Output Signal Ground Ground DSP Core Voltage +3.3 Volts +5 Volts DIGIO0 DIGIO1 CPLD Spare Ground
TP2
3-15
3-16
Appendix A Schematics
This appendix contains the schematics for the TMS320VC5509A EVM PLUS. Board components with designators over 200 (e.g. DS210, R211) are part of Spectrum Digitals embedded JTAG emulator and are not included in these schematics.
A-1
A-2
REVISIONS REV DESCRIPTION DATE APPROVED
D C B
REVISION STATUS OF SHEETS
DWN CHK DATE ENGR ENGR-MGR A QA 17 MFG A RLSE 7

4
DATE
DATE DATE DATE DATE DATE
REV A 18 A 8 9 10 APPLICATION A A NEXT ASSY USED ON 19 A
SPECTRUM DIGITAL
Title TMS320VC5509A EVM PL US Size B Date:
3 2
SH
11
12
13
14
15
16
REV
Document Number 507752 Tuesday, July 27, 2004 Sheet

1
Rev A 1 of 23
SH
(3,17) DSP_12MHZ_CLKIN 1 R103 Y2 CS10_12.0000MAB J C122 0.01uF C124 2 VSS_USBPLL USB_VCC DSP_IOVCC DSP_AVCC R62 33 DSP_RTC_IOVCC 10pF 10uF C123 RN21 10
C120
10pF
L12
DSP_CVCC FB30 A[0..20]
DSP_CLKOUT (8) A[0..20] (3,4,7)
C121
39pF
Y3
32.768KHZ
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15 16
A0 A1 A2 A3 A4 A5 A6 A7
C125
39pF
F2
F1
C12 A14 A13 B13
C14 F10 D2
E6 A4 A8 F13 P14 P13 K10 P8 J2 H2 D9 H10 M12 N13 N6 E3 G11
A6 B7 M11 N8 J5 G1 B8 J11 C10 L14 M4 B2 N7 L1 J10 L7
R98 NO-POP X1 F5 RCVDD AVDD ADVDD DVDD16 DVDD15 DVDD14 DVDD13 DVDD12 DVDD11 DVDD10 DVDD9 DVDD8 DVDD7 DVDD6 DVDD5 DVDD4 DVDD3 DVDD2 DVDD1 CVDD12 CVDD11 CVDD10 CVDD9 CVDD8 CVDD7 CVDD6 CVDD5 CVDD4 CVDD3 CVDD2 CVDD1 RVDD3 RVDD2 RVDD1 A0/A14
3.3V
1 2 3 4 5 6 7 8
RPACK8-33 RN22 16 15 14 13 12 11 10 9 RPACK8-33 RN23
RDVDD3 RDVDD2 RDVDD1
R2 B12 A12 RTCINX2 RTCINX1
R3
10K
10K
CVDD_PLL
C112 NO-POP
X2/CLKIN
USBVDD
CLKOUT
A8 A9 A10 A11 A12 A13 A14 A15
A16 A17 A18 A19 A20 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RPACK8-33 AOEn AWEn AREn (3,4,7) (3,4,7) (3,7)
C
(16) DSP_TRST# (16) DSP_TCK (16) DSP_TDI (16) DSP_TDO (16) DSP_TMS (16) DSP_EMU0 (16) DSP_EMU1 TRST TCK TDI TDO TMS EMU0 EMU1/OFF
J12 J13 K14 K13 J14 K11 K12
U1
(15) USB_POWERDET (3,5) GP6 (3,5) GP5 (4,5) GP4 (5) GP3 (5) GP2 (5) GP1 (5) GP0 RPACK4-33 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
D1 C4 D5 A3 B3 E2 E1 F3
TMS320VC5509A-GHH
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 G2 G4 G5
H11 M7 K7 K6 P6 M6 L6 N5 L5 P4 N4 L4 P3 N3 K9 M8 P7 P5 K1 H3 G3
OE WE GPIO.IO8/RE RDY CLKMEM SDA10/GPIO13 SDRAS/GPIO12 SDCAS SDWE CE0/GPIO9 CE1/GPIO10 CE2 CE3/GPIO11 BE0 BE1
4 3 2 1 5 RN25 6 7 8 D10 B10 A11 C9 A10 A9 MMC2.DAT3/FSX2 MMC2.DAT0/CLKX2 MMC2.CLK/DX2 MMC2.DAT2/FSR2 MMC2.DAT1/DR2 MMC2.CMD/CLKR2
5 RN24 6 7 8
H1 L2 M2 M1 K3 L3
DSP_RDY
(7) DSP_CLKMEM (4) SDA10 SDRASn SDCASn SDWEn H4 H5 J1 J3 J4 K2 4 3 2 1 RN8 R78 R76 5 6 7 8 RPACK4-33 33 33 CE0n CE1n CE2n CE3n (4) (3) (3,7) (3,7) DSP_BE0n (4,7) DSP_BE1n (4,7) (4) (4) (4) (4)
B
(8) DSP_BFSX2 (8) DSP_BCLKX2 (8) DSP_BDX2 (8) DSP_BFSR2 (8) DSP_BDR2 (8) DSP_BCLKR2
RPACK4-33
4 3 2 1
R77 RN2 4 3 2 1
33 RPACK4-33 SDA10 5 SDARASn 6 SDACASn 7 SDAWEn 8
RPACK4-33
(8) DSP_BFSX1 (8) DSP_BCLKX1 (8) DSP_BDX1 (8) DSP_BFSR1 (8) DSP_BDR1 (8) DSP_BCLKR1 (4,19) CLKX_R_0 5 RN26 6 7 8 MMC1.DAT3/FSX1 MMC1.DAT0/CLKX1 MMC1.CLK/DX1 MMC1.DAT2/FSR1 MMC1.DAT1/DR1 MMC1.CMD/CLKR1 B5 D6 A5 C6 E7 B6 CLKR0 DR0 FSR0 CLKX0 DX0 FSX0 TOUT SDA (I2C) SCL (I2C) RESET INT0 INT1 INT2 INT3 INT4 B4 H13 H14 H12 G14 G13 G10 F14 F12
4 3 2 1
E8 C8 E9 A7 D8 D7
(4,17) (19)
DR0 FSR0
R104
(4,19) (19)
DX0 FSX0
(3) DSP_TOUT
1 2 3 4 5 6 7 8 RPACK8-33
16 15 14 13 12 11 10 9 RN27
(15,19) (15,19)
SDA SCL
(3) DSP_RSTn
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 ADVSS AVSS1 AVSS2 DVSS
DN (USB) PU (USB) DP (USB)
(3) (3) (8) (3) (8)
INT0n INT1n INT2n INT3n INT4n
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E11 AIN3 D12 AIN2 D13 AIN1 D14 AIN0 D3 C1 D4 E14 XF
L13 L12 L11 M14 N12 P12 L10 N11 P11 M10 P10 L9 M9 P9 K8 L8
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D[0..15] (3,4,6)

A
16 15 14 13 12 11 10 9
RN1 RPACK8-10K L13 FB30 1 1 VSS_USBPLL TP9 TestPoint

4
B1 C2 E4 F4 N2 P2 M3 M5 N14 M13 D11 C11 B11 B9 K4 K5 N1 P1 N9 N10 F11 E13 C7 C5 E5 A2 E12 C13 B14 G12
Spectrum Digital Incorporated

Title TMS320VC5509A EVM PL US TP10 TestPoint
3
3.3V
1 2 3 4 5 6 7 8
DSP_XF DP_USB PU_USB DN_USB A0IN A1IN
(12) (15) (15) (15) (15) (15)
Size B Date:
2

1
Rev A 2 of 23
A-3
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
39 91
U2 VCCINT1 VCCINT2 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6
CE3n AREn AOEn CE1n CE2n A18 A17 52 54 55 56 57 58 PIN52 PIN54 PIN55 PIN56 PIN57 PIN58 PIN1 PIN2 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 1 2 5 6 7 8 9 10
3 18 34 51 66 82
GNDINT1 GNDINT2
GNDIO1 GNDIO2 GNDIO3 GNDIO4 GNDIO5 GNDIO6 GNDIO7 GNDIO8 GNDIO9 GNDIO10
38 86
11 26 33 43 53 59 65 74 78 95
A-4
3.3V 3.3V JP1 C1 R105 0.1uF FLASH_RSTn R8 1K DSP_RSTn R9 1K XDATA_T/Rn R83 10K FLASH_CEn (4) XCTL_OEn XDATA_T/Rn XDATA_OEn XCTL_OEn (7) XDATA_T/Rn (6) XDATA_OEn (6) (12) DIGIO_0 (12) DIGIO_1 3.3V
PULLUP/DOWN TO KEEP LOGIC IN RESET WHEN THE CPLD IS NOT PROGRAMMED.
3.3V 3.3V C2 0.1uF XCTL_OEn R7 10K 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C3 C4 C5 C6 C7 C8
RN28
1 2 3 4 NO POP 1 3 5 7 9 XDATA_OEn R73 10K 2 4 6 8 10
8 7 6 5
ISR_TCK ISR_TDO ISR_TMS
ISR_TDI
RPACK4-10K
SMT FEMALE HEADER 5X2
3.3V
3.3V
RN31
RPACK8-10K
AWEn
USER_LED4 (5) USER_LED3 (5) USER_LED2 (5) PON3.3VRSn (13) USER_LED1 (5) PONCOREn (14) CORE_V_CTL0 (14) CORE_V_CTL1 (14) INT1n INT3n (2) (2)
(10) DC_DETECTn (10) DC_STAT1 (10) DC_STAT0 (10) X_RESETn (10) DC_CNTL1 (10) DC_CNTL0 (15) LCD_RSn PIN60 PIN61 PIN63 PIN64 PIN67 PIN68 PIN69
60 61 63 64 67 68 69
DSP_RSTn
USB_DSP_RST# USER_SW3
(15) LCD_SI (15) LCD_A0 (15) LCD_SCK (10) X_TIN0 (10) X_TOUT0 (17) USB_DSP_RST# (5) USER_SW3 PIN70 PIN71 PIN72 PIN75 PIN76 PIN77 PIN79 D7 D6 D5 D4 D3 D2 D1 D0 PIN30 PIN31 PIN32 PIN35 PIN36 PIN37 30 31 32 35 36 37 CE3n AREn AOEn CE1n CE2n (10) DC_PORSTn USB_EMU_PONRSn
70 71 72 75 76 77 79
PIN12 PIN13 PIN14 PIN16 PIN17 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN28 PIN29
12 13 14 16 17 19 20 21 22 23 24 25 27 28 29
INT0n (2) DSP_TOUT (2) FLASH_RSTn (4) DSP_RST_LEDn (5) DSP_RSTn (2) CPLD_MMC_MCBS P2n (8) CPLD_EXP_MCBSP2n (8) CPLD_ONBD_AIC23n (17)
PBSW_RSTn USER_SW2 USER_SW1 USER_SW0
(10) X_INT3n (10) X_INT1n (10) X_INT0n (5) PBSW_RSTn (2,5) GP6 (2,5) GP5 (5) USER_SW2 (5) USER_SW1 (5) USER_SW0 (5) WAKE_UP TP8 (2,17) DSP_12MHZ_CLKIN (2,4,7) AWEn AWEn ISR_TCK ISR_TMS ISR_TDI 62 15 4 TCK TMS TDI IN/OE1 IN/GCLR IN/GCLK1 IN/OE2/GCLK2 88 89 87 90 PIN40 PIN41 PIN42 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 TDO
80 81 83 84 85 92 93 94 96 97 98 99 100 PIN80 PIN81 PIN83 PIN84 PIN85 PIN92 PIN93 PIN94 PIN96 PIN97 PIN98 PIN99 PIN100 40 41 42 44 45 46 47 48 49 50 73
CE3n
(2,7)
D[0..15]
(2,4,6)
A20 A19 A3 A2 A1 A4 ISR_TDO
AREn AOEn CE1n CE2n
(2,7) (2,4,7) (2) (2,7)
A[0..20]
A[0..20]
(2,4,7)
CONTROL & CPLD

EPM3128A TC100 Title TMS320VC5509A EVM PL US Size B Date: Document Number 507752 Tuesday, July 27, 2004 Sheet 3 of 23 Rev A
(2,3,6) D[0..15] 3.3V A[0..20] 3.3V U24
D[0..15]
(2,3,7) A[0..20]
C10 .1uF
C11 .1uF
C12 .1uF
C13 .1uF
C14 .1uF U4 VCC 37 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 (2) 3.3V A11 A12 A13 35 20 21 38 37 DSP_CLKMEM R80 15 (2) (2) (2) (2) SDWEn SDCASn SDRASn DSP_BE0n DSP_BE1n (2,7) DSP_BE0n (2,7) DSP_BE1n CE0n SDWEn SDCASn SDRASn 10K A11 BA0 BA1 CLK CKE SDA10 23 24 25 26 29 30 31 32 33 34 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 2 4 5 7 8 10 11 13
VDDQ4 VDDQ3 VDDQ2 VDDQ1 VDD3 VDD2 VDD1
49 43 9 3 27 14 1
1 2 3 4 5 6 7 8 RPACK8-33
RN29 16 15 14 13 12 11 10 9
D0 D1 D2 D3 D4 D5 D6 D7
3.3V
3.3V
R10 RY/BY R11 47 26 28 11 12 BYTE CE OE WE RESET NC1 NC2 NC3 10 13 14 VSS VSS AM29LV400B FLAS H 27 46 10K
DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 (2) DSP_CLKMEM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 19 16 17 18 15 39 CS WE CAS RAS DQML DQMH VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS1 VSS2 VSS3
45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 42 44 45 47 48 50 51 53 6 12 46 52 28 41 54
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 RPACK8-33
RN30 16 15 14 13 12 11 10 9
D8 D9 D10 D11 D12 D13 D14 D15

C
10K
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
(3) FLASH_CEn (2,3,7) AOEn (2,3,7) AWEn (3) FLASH_RSTn
MT48LC4M16A2TG-8EL
3.3V U41 GP4 CS SO WP SCLK SIN 5 GND CAT25C128 6 HOLD 7 C126 0.1uF VCC 3.3V R106 2 3 R107 4 33 33 1 8
(2,5)
(2,17)
DR0
(2,19) CLKX_R_0
(2,19)
DX0

4 3 2
SPI Boot Memory
MEMORY FLASH/SDRAM

1
Rev A 4 of 23
A-5
WAKE UP
C127
make sure switch lines up with on/off
8 7 6 5
A AA
B BB
R109 2 WAKE_UP (3) 33 SN74AHC1G14 C128 1uF 3 4
U42
S4
1 2 3 4
A AA
B BB
R82 2 33 SN74AHC1G14 3 C102 1uF 4 PBSW_RSTn PBSW_RSTn (3)
U30
A-6
4 3 2 1
3.3V
USER LEDS
RN12
3.3V
R16 150 RPACK8-2.2K DS1 GREEN DS2 GREEN DS3 GREEN DS4 GREEN DS5 YELLOW
R17 150
R14 150 GP4 GP5 GP6 (2,4) (2,3) (2,3)
R15 150
R13 150
1 2 3 4 5 6 7 8
D
16 15 14 13 12 11 10 9
(3) USER_LED1 RN13 GP0 GP1 GP2 GP3 S3
USER_LED1
(3) USER_LED2
USER_LED2
(3) USER_LED3
USER_LED3
(3) USER_LED4 RPACK4-1K SW DIP-4
USER_LED4
4 3 2 1
5 6 7 8
1 2 3 4
8 7 6 5
GP0 GP1 GP2 GP3
(2) (2) (2) (2)
(3) DSP_RST_LEDn
DSP_RST_LEDn
3.3V
RN11 (3) (3) (3) (3) RPACK4-10K 3.3V 3.3V USER_SW0 USER_SW1 USER_SW2 USER_SW3 1 2 3 4 8 7 6 5
S2 SW DIP-4
R108 10K 0.1uF
PUSHBUTTON SW
3.3V 3.3V
PUSHBUTTON RESET
R24 10K C117 0.1uF
S1
PUSHBUTTON SW

Title TMS320VC5509A EVM PL US
LEDS/SWITCHES
4 3 2
Size B Date:

1
Rev A 5 of 23
X_D[0..15] X_D[0..15] (10)
(2,3,4) D[0..15] 3.3V 3.3V
42 31 Vcc Vcc Vcc Vcc
U8 7 18
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1OE 1DIR 2OE 2DIR GND GND GND GND SN74LVTH16245 A GND GND GND GND 28 34 39 45 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 48 1 25 24 4 10 15 21 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
X_D0 X_D1 X_D2 X_D3 X_D4 X_D5 X_D6 X_D7 X_D8 X_D9 X_D10 X_D11 X_D12 X_D13 X_D14 X_D15
(3) XDATA_OEn (3) XDATA_T/Rn
3.3V
C52 .1uF .1uF .1uF .1uF
C53
C54
C55

Title
EXPANSION DATA BUFFERS

4 3 2
TMS320VC5509A EVM PL US Size B Date: Document Number 507752 Tuesday, July 27, 2004 Sheet
1
Rev A 6 of 23
A-7
(10) X_ARDY (2,3) (2,3) (2,3) (2,3,4) (2,3,4) (2,4) DSP_BE1n (2,4) DSP_BE0n A17 A18 A19 A20 X_A17 X_A18 X_A19 X_A20 X_BE1n X_BE0n (10) (10) CE3n CE2n AREn AWEn AOEn 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 X_CE3n X_CE2n X_REn X_WEn X_OEn (10) (10) (10) (10) (10) 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 X_ARDY 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 DSP_RDY (2) 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 DSP_RDY 1OE 1DIR 2OE 2DIR GND GND GND GND XCTL_OEn SN74LVTH16245 A 4 10 15 21 GND GND GND GND GND GND GND GND 28 34 39 45 SN74LVTH16245 A GND GND GND GND 28 34 39 45 3.3V 48 1 25 24 1OE 1DIR 2OE 2DIR 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 48 1 25 24 4 10 15 21 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 X_A1 X_A2 X_A3 X_A4 X_A5 X_A6 X_A7 X_A8 X_A9 X_A10 X_A11 X_A12 X_A13 X_A14 X_A15 X_A16 XCTL_OEn
X_A[1..20]
A-8
X_A[1..20] X_A[1..20] (10) 3.3V A[0..20] 3.3V 3.3V R72 2.2K 42 31 Vcc Vcc 42 31 Vcc Vcc Vcc Vcc Vcc Vcc U10 7 18 U11 7 18 3.3V 3.3V
D C
(2,3,4) A[0..20]
(3) XCTL_OEn
3.3V
3.3V
C56 C62 .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF
C57
C58
C59
C60
C61
C63

4 3 2
EXPANSION ADDR, CONTROL BUFFERS

1
Rev A 7 of 23
McBSP0 BUFFER
4.1V C64 .1uF C65 .1uF U12 Vcc 3 4 7 8 11 1A1 1A2 1A3 1A4 1A5 1OE 15 16 19 20 23 X_DX1 X_INT2n (10) X_INT4n (10) X_CLKOUT (10) 3.3V
ADD RESISTOR TO THIS PATH
4.1V
U14 24 Vcc X_CLKR1 X_DR1 X_FSR1 X_CLKX1 X_FSX1 1A1 1A2 1A3 1A4 1A5 1OE 15 16 19 20 23 2A1 2A2 2A3 2A4 2A5 13 12 R48 R86 10K 360 2OE GND SN74CBT3384 2B1 2B2 2B3 2B4 2B5 R47 360 X_DX2 (10) 1B1 1B2 1B3 1B4 1B5 1 (10) (10) (10) (10) (10) (2) DSP_BCLKR2 (2) DSP_BDR2 (2) DSP_BFSR2 (2) DSP_BCLKX2 (2) DSP_BFSX2 3 4 7 8 11 2 5 6 9 10 2 5 6 9 10 24 X_CLKR2 X_DR2 X_FSR2 X_CLKX2 X_FSX2 (10) (10) (10) (10) (10)
(2) DSP_BCLKR1 (2) DSP_BDR1 (2) DSP_BFSR1 (2) DSP_BCLKX1 (2) DSP_BFSX1 1B1 1B2 1B3 1B4 1B5 1
(2) DSP_BDX1 2A1 2A2 2A3 2A4 2A5 2OE GND SN74CBT3384 2B1 2B2 2B3 2B4 2B5
(2) INT2n (2) INT4n (2) DSP_CLKOUT 13 R46 12 360
14 17 18 21 22 (10) (2) DSP_BDX2
14 17 18 21 22
(3) CPLD_EXP_MCBS P2n
McBSP1 BUFFER
McBSP2 BUFFER
4.1V
C68 U15 Vcc 24 .1uF
(2) DSP_BFSX2 (2) DSP_BCLKX2 (2) DSP_BDX2 (2) DSP_BFSR2 (2) DSP_BDR2
3 4 7 8 11 1
1A1 1A2 1A3 1A4 1A5 1OE (2) DSP_BCLKR2 3.3V 14 17 18 21 22 13 12 R111 10K R112 360 2A1 2A2 2A3 2A4 2A5 2OE GND
1B1 1B2 1B3 1B4 1B5
2 5 6 9 10
MMC2.DAT3 (9) MMC2.DAT0 (9) MMC2.CLK (9) MMC2.DAT2 (9) MMC2.DAT1 (9)
2B1 2B2 2B3 2B4 2B5
15 16 19 20 23 R110 360 SN74CBT3384
MMC2.CMD (9)
(3) CPLD_MMC_MCBS P2n

Title
SERIAL PORT BUFFER

4 3 2
1
Rev A 8 of 23
A-9
A-10
4 3 2 1
3.3V
MMC and ALT Media Connectors

MEDIA_PWR C155 0.1uF C156 0.1uF
R166 0
J12 MMC2.DAT2 MMC2.DAT3 MMC2.CMD 10 11 12

MULTI-MEDIA CARD
(8) MMC2.DAT2 (8) MMC2.DAT3 (8) MMC2.CMD MMC2.CLK MMC2.DAT0 MMC2.DAT1 MMC/SD_CARD C157 NO POP R167 R168 R169 R170 R171 R172 NO NO NO NO NO NO POP POP POP POP POP POP NO POP NO POP NO POP NO POP NO POP C158 C159 C160 C161 C162
(8) MMC2.CLK
(8) MMC2.DAT0 (8) MMC2.DAT1
9 1 2 3 4 5 6 7 8 DAT2 WP DAT3 COM CMD INS VSS1 VDD CLK VSS2 DAT0 DAT1
DAT2 DAT3 CMD CLK DAT0 DAT1 HIGH HIGH HIGH HIGH HIGH HIGH
MEDIA_PWR R173 R174 R175 R176 R177 R178 10K 10K 10K 10K 10K 10K
MEDIA_PWR J13 MMC2.DAT3 MMC2.DAT0 MMC2.DAT2 MMC2.DAT1 MMC2.CLK

ALT MEDIA DAT2 DAT3 CMD CLK DAT0 DAT1 HIGH LOW HIGH LOW LOW HIGH
1 2 3 4 5 6 7 8 9 10
VSS1 BS VCC1 SDIO RSV XINS RSVD SCLK VCC2 VSS2 NO POP
NO COMMAND PRESENT

4 3 2

1
Rev A 9 of 23
MEMORY INTERFACE
EXPANSION BUS CE2
PERIPHERAL INTERFACE
MIN_12V 5V 3.3V_DB P2B 3.3V_DB
D
(7) X_A[1..20] POS_12V 5V 5V 3.3V_DB 5V 5V 5V 5V P1B 3.3V_DB 5V P2A
P1A
5V 5V
X_A20 X_A18 X_A16 X_A14 3.3V_DB 3.3V_DB X_A11 X_A9 X_A7 X_A5 5V X_A3 X_A1 X_CLKR1 X_FSR1 X_CLKX2 X_FSX2 X_CLKR2 X_FSR2 X_INT0n X_INT1n X_TOUT0 X_INT0n X_INT1n (8) (8) (8) (8) (8) (8) (3) (3) (3) X_RESETn (3) DC_STAT1 X_INT3n DC_CNTL1 (3) DC_STAT1 (3) X_INT3n (3) X_BE0n (7) R53 10K X_CLKX1 X_FSX1 (8) (8) X_A19 X_A17 X_A15 X_A13 X_A12 X_A10 X_A8 X_A6 5V X_A4 X_A2 X_BE1n (7) R59 10K
X_DX1 X_DR1 X_DX2 X_DR2 X_INT2n X_TIN0 X_INT2n
(8) (8) (8) (8)

C
(3) (8)
X_D15 X_D13 X_D11 X_D9 X_D7 X_D5 X_D3 X_D1 X_D6 X_D4 X_D2 X_D0
X_D14 X_D12 X_D10 X_D8
X_INT4n
X_INT4n
(8)
DC_STAT0
DC_CNTL0 (3) DC_STAT0 (3)
DC_DETECTn
DC_DETECTn (3)
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 X_REn X_OEn X_CE3n (7) (7) (7) X_WEn X_ARDY X_CE2n (7) (7) (7) SFM-140-L2-S-D-LC SFM-140-L2-S-D-LC 3.3V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
X_CLKOUT (8)
SFM-140-L2-S-D-LC
SFM-140-L2-S-D-LC
3.3V
B
RN17 R67 10K 5V U16 6 7 IN1 IN2 ENn GND NC1 NC2 (3) DC_DETECTn 4 8 5 3 OUT1 OUT2 RESET/PG FB NC3 NC4 14 13 16 15 17 18 X_INT0n X_INT1n X_INT2n X_INT3n DC_PORSTn (3) 3.3V_DB 4 3 2 1
(6) X_D[0..15]
RPACK4-10K 5 6 7 8 R75 X_ARDY 10K
HS/GND1 HS/GND2 HS/GND3 HS/GND4 HS/GND5 HS/GND6 HS/GND7 HS/GND8 PWRPAD
C66 .1uF
C107 10uF TPS76733QPWP
DC_STAT0 DC_STAT1 DC_DETECTn X_INT4n
RN18 4 3 2 1
RPACK4-10K 5 6 7 8
A
1 2 9 10 11 12 19 20 21

Title TMS320VC5509A EVM PL US Size B Document Number 507752 Rev A
DB MEMORY/PERIPERAL INTERFACES
4 3 2
Date:
Tuesday, July 27, 2004
Sheet
1
10
of
23
A-11
1 2
4 Vin- Vin+ R134 10K 1% C132 0.01uF INA139
+5 GND -12 +12 3 R133 100K 1% C133 0.1uF
4 3 2 1
NO-POP 4-pin Molex
A-12
4 3 2 1
EXTERNAL POWER PLUG

5V 3.3VA R191 5V_IN HEADER 2x1 R52 5V 0.025 3.3VA
D
3.3V 20K 1%
POWER INPUT
JP2
J5
CENTER SHUNT SLEEVE 3.3VA C129 0.01uF C130 0.1uF
2.5 MM JACK RASM712
SWITCHCRAFT RAPC712 PLUG
1 C131 1uF U43A

NI
TP11 TestPoint
MIN_12V U44 1 OPA2356 -3.3VA R131 5

NI
POS_12V 2 + 1 2 R132 3 1K 1% VCC OUT GND
J6
75 1%
V_SHUNT_BD (12)
ALTERNATE EXTERNAL POWER

NI NI
(DO NOT POPULATE)

U43B 6 + OPA2356
NI
NI
INPUT POWER
3.3V D2 1 MMBD4148 MMBD4148 3 1 3 D3 1
DSP CORE & I/O DIFFERENTIAL VOLTAGE PROTECTION

DSP_CVCC D4 3 MMBD4148 1 MMBD4148 R63 NO POP D5
B
TP1
TP2
TP3
TP4 TP5
DSP_CVCC 3.3V M1 125_PH M2 125_PH 5V M3 125_PH
DAUGHTERCARD STANDOFF GROUNDING

M4 125_PH KEEP TRACES A MINIMUM OF 0.070 INCHES FROM THESE HOLES.
A
GROUND TEST POINTS

4 3 2

1
Rev A 11 of 23
3.3V JP4 R184 JP7 1 2 R126 NO-POP HEADER 2x1

NI
R182 1 2 ANALOG_IN6 NO-POP HEADER 2x1 R125 3.3K

NI
ANALOG_OUT0 R183 10K 1% 10K 1% 3.3K R185 10K 1%
10K 1%
DIG_IO0
NI NI
R129 R127 R124 1K 1K R128 1K
1K
DIGIO_0 DIGIO_1
(3) (3)
DIG_IO1 JP8 1 2
R186 JP5 1 2 NO-POP HEADER 2x1

NI
R188 ANALOG_IN7 10K 1% NO-POP HEADER 2x1

NI
ANALOG_OUT1 R187 10K 1% R130 10K 1%
10K 1%
1
NI NI
TP6 TestPoint TP7 TestPoint
J8 P3 NI_PIN1 NI_PIN2 NI_PIN3 NI_PIN37 NI_PIN38 NI_PIN40 NI_PIN41 NI_PIN42 NI_PIN43 NI_PIN5 NI_PIN6 NI_PIN2 NI_PIN3 NI_PIN5 NI_PIN6 NI_PIN41 NI_PIN43 NI_PIN11 NI_PIN46 NI_PIN48 NI_PIN16 NI_PIN19 NI_PIN30 NI_PIN10 NI_PIN11 NI_PIN45 NI_PIN46 DIG_IO3 DIG_IO7 DIG_IO2 DIG_IO5 DIG_IO0 NI_PIN47 NI_PIN48 NI_PIN49 NI_PIN51 1 3 5 7 9 11 13 15 17 19 21 23 NO-POP HEADER 12X2 NI_PIN16 NI_PIN19 ANALOG_OUT0 ANALOG_OUT1 AIN_GND AIN_GND ANALOG_IN5 AIN_GND AIN_GND ANALOG_IN2 AIN_GND ANALOG_IN0 NI_PIN60 ANALOG_IN6 AIN_GND NI_PIN28 NI_PIN30 AIN_GND (13) V_SHUNT_IO AIN_GND ANALOG_IN1 ANALOG_IN3 ANALOG_IN4 DIG_IO4 DIG_IO6 DIG_IO1 2 4 6 8 10 12 14 16 18 20 22 24
NI_PIN1 NI_PIN37 NI_PIN38 NI_PIN40 NI_PIN42 NI_PIN10 NI_PIN45 NI_PIN47 NI_PIN49 NI_PIN51 NI_PIN60 NI_PIN28
ANALOG_IN7
V_SHUNT_BD (11) V_SHUNT_CORE (14) (2) DSP_XF JP9 1 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
CONN RCPT 68 R123 0

NI
NO-POP HEADER 2x1
NI

4 3 2

1
Rev A 12 of 23
A-13
C136 1uF 8 U40A

NI
2 1
L14 4 Vin- Vin+ R138 10K 1% DSP_IOVCC

NI NI
BEAD 3 R137 100K 1% INA139 C137 22uF C140 0.1uF 0.1 OHM
+
R139
CFLY+
CFLY-
C143 TPS610400 4 1uF L16 BEAD 1uF
GND
A-14
3.3V R61 3.3V 10K U25 C105 C70 2 10uF 0.1uF 1 GND TPS76733QD 3.3VA RESET 8 R189 20K 1% EN C103 NO POP
+ +
5V PON3.3VRSn (3) Vout Vout SENSE C74 10uF 5 6 7
3 4 Vin Vin
C104 47uF
C71
0.1uF
3.3VA JP6 HEADER 2x1 1 TP12 TestPoint
C134 0.01uF C135 0.1uF
U45 1 OPA2356 5 VCC OUT + GND 2

NI
2 1 R136 3 1K 1%
SMOOTHING FILTER FOR POWER MEASUREMENT
R135 -3.3VA
75 1%
V_SHUNT_IO (12)
C
3.3V
C138 0.01uF
C139 0.1uF
NI +
C141 22uF
C142
1uF U46 L15 1 R140 10

A
3.3V BEAD -3.3VA 2 IN OUT
C144
C145

Title TMS320VC5509A EVM PL US Size B Document Number 507752 Date: Tuesday, July 27, 2004
3 2
1uF
Rev A Sheet
1
NI
13
of
23

4
TP13 TestPoint R190 20K 1%
JP3 HEADER 2x1 U40B 3.3VA 2 1 3.3V GND 4 Vin- Vin+ INA139
SMOOTHING FILTER FOR POWER MEASUREMENT NI NI
U47 5 VCC OUT 2 3 1 R142 R143 100K 1% 10K 1%
6 5
7 OPA2356 R144 10K 1%
R141
75 1%
V_SHUNT_CORE (12)
R81 10K R97 PONCOREn (3) L11 BEAD 1K C108 NO POP C119 22uF
+
R51 C118 0.1uF 0.1
5V U26 L10 L C99 47pF R55

+
10uH 3.3V
DSP_CVCC
1 IN ILIM EN FB R145 221K 1% R57 60.4K, 1% 10 SYNC FC PowerG Q1 BSS138 GND PGND TPS62000 Q2 BSS138 5 R60 FBVCC2 R56 100K 10K 221K 1% C100 47uF 6.3V R54 100K, 1%
LX2
+
+C98
10uF 6.3V PWM/MIX
C106 22uF
7 2 4
C101
0.1uF
C111 0.1uF
3.3V R146 100K
Selectable core voltage option enable
R147 10K
C146 0.1uF
(3) CORE_V_CTL0 (3) CORE_V_CTL1

A

4 3 2

1
Rev A 14 of 23
A-15
33 R149 1M 24 1% 24 1% C149 NO POP Optional C150 0.1uF USBVIN 2 U49 1 TLV2721 A0IN (2) VCC_ALOG 5 USB_D+ USB_DR150 R151
L17 .01uF D8 6.2V 1M R155 680K 3.3V 3.3V R156 1.5K 1% BEAD
33 R154 5
A-16
VCC_ALOG C147 0.1uF
Optional C148
(2)
PU_USB
R148 1 A1IN (2) TLV2721 A1INKYD 3

+
4
-
U48
D
NO POP
(2) (2)
DP_USB DN_USB
R152 300K A0INKYD 3

+
R153
4
-
C151
J10
5 R157 USB_POWERDET USB_POWERDET (2) R159 2K R160 2K R161 1M R163 R164 33 33 1M R162 0
USBVDD SHEILD D+ SHEILD D-
3 2
USBVSS
L18
BEAD
CONN_USB
R158
1M
J11
C152 (2,19) (2,19) SDA SCL
A0INKYD LCD_SI_OUT LCD_RSn_OUT
A1INKYD LCD_A0_OUT LCD_SCK_OUT
0.1uF
1 3 5 7 9 11 13 15
2 4 6 8 10 12 14 16 HEADER 8X2 2MM
RN34 (3) LCD_SI (3) LCD_A0 (3) LCD_SCK (3) LCD_RSn RPACK4-33 1 2 3 4 8 7 6 5 LCD_SI_OUT LCD_A0_OUT LCD_SCK_OUT LCD_RSn_OUT
3.3V R165 10 VCC_ALOG

+
A
C153 1uF
C154 0.1uF

Title TMS320VC5509A EVM PL US Size B Date: Document Number 507752 Tuesday, July 27, 2004
3 2
Rev A Sheet
1
15
of
23

4
3.3V 3.3V C116 0.1uF J7 2 4 U29 DS6 4 Green 3 2 XDS_EMU1 4.1V SN74AHC1G14 5 8 10 12 14 XDS_TRST# R64 1K
3.3V R68 150
DSP JTAG HEADER

3.3V
3.3V TSW-107-14-G-D-0 06
XDS_TMS XDS_TDI XDS_TVD XDS_TDO XDS_TCK_RTN XDS_TCK XDS_EMU0 1 3 5 7 9 11 13
USB EMBEDDED EMU
JTAG MULTIPLEXERS
0.1uF R100 U20 XDS_TDO XDS_TDI XDS_TCK XDS_TMS 4A GND 8 12 DSP_TMS (2) 3A 9 2A 7 DSP_TDI (2) 1 1A 4 DSP_TDO (2) 5 VCC 16 NO POP 10K
C75
R99
R101
3.3V C113 NO POP C115 0.1uF U28 4 2 SN74LVC1G32 3 R65 33 DSP_TCK (2)
C
10K
T_TDO
T_TDI
T_TCK
T_TMS 1 15 S OE SN74CBT3257
2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
T_TCK_RET
3.3V 4.1V C114 0.1uF 5 0.1uF U21 XDS_EMU0 XDS_EMU1 XDS_TRST# XDS_TCK_RTN EMU_STS 3 VCC 1A 2A 3A 4A 1 15 S OE GND SN74CBT3257 16 4 7 9 12 8 DSP_EMU0 (2) DSP_EMU1 (2) DSP_TRST# (2)
B
C76 1
U27 4 2 SN74LVC1G32 R66 33
T_EMU0
T_EMU1
T_TRSTn
2 3 5 6 11 10 14 13
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
CBT VOLTAGE DIVIDER

5V R69 1 1.6K 4.1V
D7 LM4040DCIM3-4. 1
JTAG INTERFACE
2 Title TMS320VC5509A EVM PL US Size B Date: Document Number 506202 Tuesday, July 27, 2004 Sheet 16 of 23 Rev B
A-17
3.3V 3.3V 5V USB/Emulation 5 U22 R70 3.3V 3.3V SN74LVC1G32 3 (3) USB_EMU_PONRSn PONRSn 33 T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1 T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1 (16) (16) (16) (16) (16) (16) (16)
D
THESE GATES NEED TO BE PLACED CLOSE TO USB CLOCK SOURCE
(2,4)
DR0
3 1
A-18
CLK12MHZ 1 4 2 AIC23CLKIN (19) AIC23CLKIN 10K R92 5V 5V 3.3V T_TCK_RET CLK_12MHZ CLK_24MHZ GND (3) USB_DSP_RST# USB_DSP_RST# T_TCK_RET (16) U23 R71 4 2 33 SN74LVC1G32 USB/Emulation DSP_12MHZ_CLKIN (2,3) CLK24MHZ CLK24MHZ CLK12MHZ CLK12MHZ 1
C
CLK12MHZ
Analog (19) AIC23CLKIN CODEC_SYSCLK 3.3V
(2,4,19) CLKX_R_0 (2,19) FSX0 (2,4,19) DX0 AIC3.3V FSR0 DATA_BCLK DATA_SYNCIN DATA_DIN DATA_DOUT DATA_SYNCOUT CTL_DATA CTL_CLK CTL_CS GND Analog 3.3V R102 0
(2,19)
(2,15,19) SDA (2,15,19) SCL
U50 SN74LVC1G125DCKR 3.3V
(3) CPLD_ONBD_AIC23n C163 .1uF .1uF .1uF C72 C73
Hierarcharical Blocks
A

4 3 2

1
Rev A 17 of 23
3.3V U51 TPS71501DCK R179 0 C164 R180 .01uF Supercap .01uF 4 Vin NC G FB 1
+C165 .33F
DSP_RTC_IOVCC MURS120T3 D9 5
DSP_CVCC OUT
3 C79
+
C166
C167 .01uF
C168 .01uF
C77 C95 2 22uF R181 .01uF .01uF .01uF .01uF .01uF .01uF .01uF
.01uF
+ C109
+ C110
10uF
10uF
1M,1%,0603
3.3V
324K1%,0603
C81
C83
C85
C87
C89
C91
DSP_IOVCC USB_VCC FB C169 .01uF NO POP .01uF .01uF .01uF C170 C171 C172
DSP_AVCC
L19 FB
DSP_IOVCC L20
3.3V
L21
DSP_IOVCC
C78 .01uF .01uF .01uF .01uF .01uF
C80
C82
C84
C86
C88
C90 .01uF
C92 .01uF
C93 .01uF
C94
+ C96
A
.01uF
.01uF
10uF

Title TMS320VC5509A EVM PL US Size B Document Number 507752 Rev A
DECOUPLING CAPS
4 3 2
Date:
Tuesday, July 27, 2004
Sheet
1
18
of
23
A-19
A-20
(17) CODEC_SYSCLK R325 2.2K AIC3.3VA C315 R326 4.7K
+ +
L301 HZ0805E601R
J301
4 2 1 10uF C318 NO POP 1uF R328 NO POP C321 3 J302 47pF

+
Microphone I n C319 L302 BLM21P22 1SN C317 NO POP

D
C316 NO POP C323220uF
R327 0 C322 0.1uF 10uF C326 0.1uF

+
C320 NO POP C325 C324220uF
4 2 1 Head Phone Out
C329 NO POP C330 NO POP R334 4.7K U307

PW Package
10uF C332 0.1uF 14 8 16 AVdd HPVdd VMID XTI/MCLK XTO CLKOUT RHPOUT LHPOUT 13 12 LLINE_OUT 6 AIC3.3V R339 C341 0.1uF RPACK-4 10K R341 47K 0.1uF 10uF L307 BLM21P22 1SN R342 47K C344 NO POP C345 NO POP C342 + C343 R340 100 100 C339 NO POP RLINE_OUT C337 470nF C338 470nF L306 BLM21P22 1SN 10 9 25 26 2 AGND HPGND 15 11 R332 47K R333 47K
C331
C327 NO POP
L303 BLM21P22 1SN C328 NO POP R331 0
L304 BLM21P22 1SN C333 470nF R335 4.7K C334 470nF R336 4.7K 23 24 22 SDIN SCLK MODE RLINE_OUT LLINE_OUT DOUT AIC23LRCIN R337 4.7K 17 18 20 19 MIC_BIAS MIC_IN LLINE_IN RLINE_IN
J303
4 2 1
Line In
R338 0
L305 BLM21P22 1SN
C335 C336 NO POP NO POP
AIC3.3V RN314 AIC23CS 21 CS TLV320AIC23BPW 1 2 3 4 8 7 6 5 BVdd DVdd DGND 1 27 28
4 5 7 3 DIN LRCIN LRCOUT BCLK
C340 NO POP 3 4 2 1 Line Out J304
(2,15) CTL_DATA
(2,15) CTL_CLK
(17)
Control Port
CTL_CS
R343 0
AIC3.3V RN315 AIC3.3V AIC3.3V L308 AIC3.3VA BLM21P22 1SN R344 2.2 AIC3.3V
+ +
1 2 3 4 RPACK4 10K RN316 GND L309
8 7 6 5
C346 BLM21P22 1SN 10uF
C347 10uF
(2) DATA_DIN (2) DATA_SYNCIN (2) DATA_BCLK (17) DATA_DOUT RPACK-4 33 R345 33
1 2 3 4
8 7 6 5
R312 0
(2) DATA_SYNCOUT

Title
AUDIO
4 3 2
1
Rev A 19 of 23
Appendix B Mechanical Information
This appendix contains the mechanical information about the TMS320VC5509A EVM PLUS produced by Spectrum Digital.
B-1
B-2
THIS DRAWING IS NOT TO SCALE
Printed in U.S.A., October 2004 507755-0001 Rev.A

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TMS320VC5509A EVM PLUS Technical Reference

DSP Development Systems

TMS320VC5509A EVM PLUS Technical Reference

507755-0001 Rev. A October 2004

Copyright 2004 Spectrum Digital, Inc.

Table 1: Hardware History Revision A Alpha Release History

Table 2: Manual History Revision A Alpha Release History

Chapter 1 Introduction to the TMS320VC5509A EVM PLUS

Spectrum Digital, Inc

LCD Dis play

Memory Exp EMIF

GPIO0 GPIO1 GPIO2 GPIO3

TMS320VC5509A EVM PLUS Technical Reference

Code Composer Debug

5509A on-chip USB

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

5509A EVM MMR

Internal Memory 0x028000 0x200000 0x3F0000

SDRAM Flash CPLD Daughter Card

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Chapter 2 Board Components

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

0010 0011 0100 0101 0110

0111 1000 1001 1010

INT REG LCD0 Address0 LCD1 Address0 5502EVM Misc

Reserved SHIFT DATA7 SHIFT DATA7 LCD BUSY R 1 BUSY

Reserved SHIFT DATA6 SHIFT DATA6 LCD_RESET R/W 0

Reserved SHIFT DATA5 SHIFT DATA5 Reserved R

WAKEUP INT3 SHIFT DATA3 SHIFT DATA3 Reserved R

Reserved SHIFT DATA2 SHIFT DATA2 Reserved R

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

LCDCLK LCD Address LCD Data D7 D6 D5 D4 D3 D2 D1 D0

Spectrum Digital, Inc

Analog LINE OUT MIC IN LINE IN

DR0 FSX0 CLKR0 CLKX0 FSR0 DX0

DOUT LRCOUT BCLK LRCIN DIN

LINE OUT HP OUT HP OUT

Figure 2-1, TMS320VC5509A EVM PLUS CODEC INTERFACE

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

So for the core current of 1 MA. we have:

TMS320VC5509A EVM PLUS Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5509A EVM PLUS Technical Reference

Chapter 3 Physical Description

Spectrum Digital, Inc

Figure 3-1, TMS320VC5509A EVM PLUS