Part I.

Introduction to the XILINX_64 Circuit Board

In this section the instructor showed and explained the components and functions of the XILINX_64 circuit board that we will be using for the EEE64 lab experiments. No data was obtained from this part of the lab.

Part II. Introduction to the 7400 Series TTL Gates

This part contains information about the 7400-series TTL gates that we will be use for this experiment and for most of our lab experiments for this course. The integrated circuits used for this class are the 7400, 7404, 7432 and the 7408. Each integrated circuit (chip) has 14 pins and the pin configuration can be recognized by the little notch on the top of the component. For this integrated circuits, pin 7 will always goes to ground and pin 14 is always connected to the supplied voltage (which is +5v for the XILINX_64 board). A. 7408 AND gate Gate model number on lab kit: SN74LS08N Notation Verilog F=x&y Truth Table y F 0 0 1 0 0 0 1 1

Standard Notation F=xy=xy

*Where F is the output; x and y are inputs.

Verilog Structural Model and g1(F, x, y)

x 0 0 1 1

IC Pin Configuration

B. 7432 OR gate Gate model number on lab kit: DM74L32N Notation Verilog F=x|y Truth Table y F 0 0 1 1 0 1 1 1

Standard Notation F=x+y

*Where F is the output; x and y are inputs.

Verilog Structural Model or g1(F, x, y)

x 0 0 1 1

IC Pin Configuration

C. 7400 NAND gate Gate model number on lab kit: SN74ALS00 Notation Verilog F=~(x&y) Truth Table y F 0 1 1 1 0 1 1 0

Standard Notation F=xy

*Where F is the output; x and y are inputs.

Verilog Structural Model nand g1(F, x, y)

x 0 0 1 1

IC Pin Configuration

D. 7404 NOT gate Gate model number on lab kit: SN7404N Notation Verilog F=~x Truth Table F 1 1 0 0

Standard Notation F=x=x=|x

*Where F is the output; x is the input.

Verilog Structural Model not g1(F, x)

x 0 0 1 1

IC Pin Configuration

Part III. Testing the TTL Gate Integrated Circuits

In this part we set the gates on a breadboard for functioning testing as this is the first time we are using these components. For each IC gate we connected pin 7 to ground and pin 14 to 5v source which can be wired directly from the XILINX_64 board. The XILINX_64 board also has sets of LEDs that can be used to test for output voltages and 5v sources with switches that can be used to easily produce 1 or 0 signals. Next, we proceeded to test each gate (AND, OR, NAND chips have 4 gates each while the NOT gate has 6 gates) by plugging the inputs to the source voltage with switches and the output to one of the LEDs.

We could verify that the integrated circuit gates worked correctly by comparing the output values to the Truth Tables listed above. Part III: Bonus For the bonus we connected the four integrated circuits to the same 2 input signals, while the output of each gate was connected to an LED. The bonus consisted in being able to predict the LED pattern by knowing which inputs would affect the output of the gate connected to the LEDs we want to change. Bonus Circuit Schematic

x 0 0 1 1

y 0 1 0 1

LED Pattern Observed F1(AND) F2(NAND) F3(OR) 0 1 0 0 0 1 0 0 1 1 0 1

F1(NOT) 1 1 0 0

Part IV. Using Verilog to Program Gates

In this section we used Verilog to logically reprogram the logical functions of the processing unit on the XILINX_64 board. In order to input our code, compile and download the file into the board we are using Xilinx ISE tool. For this experiment, we were asked to program a simple AND gate, and NOT, OR and NAND gates individually as an introduction to Xilinx ISE. The programming description was included in the Lab

Manual (page 9). The program could be tested once downloaded to the board since the board has fixed switches for the inputs and LEDs for the outputs. Part IV: Bonus There was the option of creating a single module with the four gates, keeping the two inputs but having 4 outputs instead (Basically the same model as in Part III-Bonus but logically programmed rather than physically built). The description used to successfully program that module was:
module lab1bonus4(in1,in2,out1,out2,out3,out4); input in1,in2; output out1,out2,out3,out4; wire in1,in2,outA,outB,outC,outD; and g1(outA,in1,in2); or g2(outB,in1,in2); nand g3(outC,in1,in2); not g4(outD,in1); not not not not endmodule g5(out1,outA); g6(out2,outB); g7(out3,outC); g8(out4,outD); //Defines inputs //Defines outputs //Defines inputs & //outputs to processor //AND gate //OR gate //NAND gate //NOT gate //LED //LED //LED //LED output output output output inverter inverter inverter inverter

Part V: Preparing an Exclusive-OR gate with Basic Gates

In this section we proved that we can represent an Exclusive OR gate (XOR) in terms of the gates mentioned above. These two representations, given by the lab manual (page 10) are:

F (X Y ) (X Y ) F X X Y X X Y
The first representation required 2 NOT gates, 2 AND gates and 1 OR gate while the second representation only used 4 NAND gates. The following simulations prove that our two representations are valid if we compare with the ExclusiveOR truth table. Exclusive-OR Truth Table x y F 0 0 0 0 1 1 1 0 1 1 1 0

F (X Y ) (X Y )
Simulation 1: x=0, y=0, F=0

Simulation 2: x=0, y=1, F=1

Simulation 3: x=1, y=0, F=1

Simulation 4: x=1, y=1, F=0

F X X Y X X Y
Simulation 1: x=0, y=0, F=0

Simulation 2: x=0, y=1, F=1

Simulation 3: x=1, y=0, F=1

Simulation 4: x=1, y=1, F=0

Where the components used were the following: Referencial Designator U1 U2 U3 U4 Gate NOT AND OR NAND Part # 7404 7408 7432 7400

Part VI. Simplifying an Equation In this section we were given an equation for a circuit with four inputs and one output. Our objective was to prove that using Boolean Algebra It is possible to prove that logical equations can be reduced and still give us the same answers or outputs. As a first step we built the circuit using 3 NOT gates, 3 OR gates and 1 NAND gate. Then we ran a simulation and recorded the data values for different outputs to build the following truth table for the equation:

F (C D) (A B D)

U3

Referencial Designator U1 U2 U3

Gate NOT OR NAND

Part # 7404 7432 7400

Then we used Boolean Algebra to reduce the given equation to a simpler form:
F (C D) (A B D) (C D) (A B D) C D A (B D) C D A (B D) F C D A (B D) C D A B D D (C A B)
This new circuit was verified through a simulation and gave us the same truth table as shown above for the original function. This new function only requires 2 AND gates, 1 OR gate and 1 NOT gate, which is less than the number of components required originally.

Referencial Designator U1 U2 U3

Gate NOT AND OR

Part # 7404 7408 7432

Verilog description:

Module equation2(A,B,C,D,F); input a, b, c, d; output f; wire a,b,c,d, b2, outand, outor,outand2; not g1(b2,b); and g2(outand, a,b2); or g3(outor,c,outand); and g4(outand2,d,outor); endmodule;

Part VII. Using a Truth Table to Design Logical Equations

In this section we were given a 4 input Truth Table with two different outputs. Our objective was to use the data in the table and the different logical analysis techniques to create a logical equation that would allow us to build a circuit able to recreate the values in the given truth table.

Location 0 1 2 3 4 5 6 7 8 9 A B C D E F

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Inputs B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Output F1 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0

F2 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0

Using the values on the table we built a K-Map to obtain the logical functions for F1 and F2. Next we reduced the functions according to the number of gates that we have available (4 ANDs, 4 ORs, 4 NANDs and 6 NOTs) F1

F2

F 1 C D A B C C D A (B C ) C D A (B C ) F 2 A B C D C D B C A B C (D B) C D A B C (D B) C D
The equation for F1 uses 2 AND gates, 2 OR gate, 2 NOT gate. The equation F2 uses 2 OR gates, 3 AND gates, 3 NOT gates and 1 NAND gate (for ~(D&B)). Since we only have 4 AND gates available, but both F1 and F2 use the C&D output, we can share it for both F1 and F2. Finally, using this equations we built our circuit and demonstrated it to the instructor to verify its validity (see cover sheet).

Conclusion
As a conclusion, the basic gates that were provided in the lab kit (AND, OR, NOT, NAND) are enough to produce complex logical equations which can also be manipulated by using Boolean Algebra. We also proved that K-Mapping allows us to use the results of the Truth Tables to find the logical equations back from its results.