Cadence Design Manual

Revision 1.0 By Yu Pu Prof.dr.Jose Pineda de Gyvez

September, 2008 Electronics Systems Group, Faculty of Electrical Engineering Eindhoven University of Technology (TU/e)

Chapter 1 Introduction
This manual describes how to use Cadence Analog IC design tool kits to implement a digital inverter.

1.1 Overview of Design Flow

Before starting design, we suggest you understand of the analog IC design flow. The general designg flow through the various tools which you will be using during the design exercise is shown in Fig. 1.

Fig. 1. General design flow The design flow starts with inputting schematics using the Cadence's schematic capture tool -Composer. Devices or cells from the libraries are used to construct your circuit. When you have finished designing a component in schematic view you will then have to simulate it to ensure that it works as expected. We shall be using the Cadence Spectre simulator during this design exercise. It will be unlikely that your component will work

as what you expect at first time so you have to iterate round the capture-simulate-debug loop until the component does work. If your design is hierarchical, this must be done for each component of your design and then for the top level design. After the components and top level of your design have been designed and simulated, you are then ready to start the physical design. The physical design starts with the cells or devices placement. Once the cells have been placed, routing can be carried out. Routing adds connectivity between the cells of the design. After place and route has been performed, then you need to do Design Rule Check (DRC) to ensure that all design rules are satisfied. The next step is to perform Layout-versus-Schematic (LVS) check to make sure all connectivity in your layout are correct. Once the LVS is done, you need to do post layout simulation to see whether your circuit meet the constrains set in your design specification. If everything is fine, the next stage is GDSII/CIF Generation. This generates the file which describes the low level geometry of your chip. This file is in a format which is suitable for the silicon vendor to create the masks required for fabrication of the chip, and therefore essentially provides the interface between the designer and the silicon house.

1.2 Getting Start with Cadence

It's recommended to create a directory named "cadence" under your own home directory to store all your cadence files. Under UNIX prompt type cd ~ to go to your home directory, then type mkdir cadence to create this directory. You can start Cadence by : icfb & ---- to start Analog Artist front end to back end The workstation will now start-up the Cadence system, after a few moments a new window will be displayed on your screen. This is known as the Command Input Window or CIW. Cadence will then finish its initialisation and leave you with the CIW. Do not iconise CIW and try to keep it in view whenever you are using Cadence. Error messages and output from some of the tools is sent to the CIW. If something doesn't appear to be working always check the CIW for error messages. In addition, the CIW allows the user great control over Cadence by interpreting skill commands which are typed into it.

Chapter 2 Schematic capture

After Cadence is running successfully, the following steps will show you how to enter the schematic designs.

2.1 Create you design library

Before starting your own schematic designs, you should first create a library where you will store all your designs. You only need to do this once for your design team for the whole design exercise. In the CIW window, choose Tools -> Library Manager to start the Library Manager. Then in Library Manager window, choose File -> New -> Library. A New Library window pops out. You give a name to your library and attach your lib to a technology file. For the example illustrated by the figures, the library is named manual_test (Fig. 2.1), and is attached to an existing techfile (Fig. 2.2), which, in this case, is tsmc13lg (Fig. 2.3).

Fig. 2.1 Create a new library Now you should be able to see a new library manual_test in the Library column of the Library Manager window (Fig. 2.4).

Fig. 2.2 Attach to a technology

Fig. 2.3 Attach to tsmc13lg technology

Fig. 2.4 Library manager

2.2 Create your first design

You can have all kinds of designs in your library. Here we start from a very simple example a digital inverter. To create a new schematic, first choose the manual_test library by clicking it in the Library column. Then choose File -> New -> Cellview and a Create New File window pops out, which asks for the cell name. Here we name the new cell inverter (Fig. 2.5).

Fig. 2.5 Create a new design Now you can edit the schematic in the blank window that pops out. The schematic editing environment in Cadence is called Virtuoso. In Virtuoso, you can add, delete and manipulate all kinds of components, wires and pins. You can find all the operations and their hot keys by exploring through the menu bar. (Fig. 2.6)

2.2.1 Add components

For our simple inverter, two transistors are needed: one PMOS and one NMOS. To add the PMOS transistor, choose Add -> Instance or by using the hot key i, the Add Instance window will pop out. Click Browse and select Library -> tsmc13lg, Cell pmos1v and View -> Symbol (Fig. 2.7). For the CDF Parameter listed in the lower portion of the Object Properties window, optionally change the Fingers to 2, and keep others to the default (Fig. 2.8). The object parameter window can later be called out by selecting the object by clicking it and then pressing the hot key q. You can then modify the properties.

Fig. 2.6 Schematic editing in Virtuoso

Fig. 2.7 Add a pmos1v instance

Fig. 2.8 Set the properties of the instance Similarly, the NMOS transistor and the ground (GND) and power supply (VDD) can be added (Fig. 2.9). Table 2.1 lists the properties of these component instances. Table 2.1 Add into the components Cell View Others pmos1v symbol Length = 130nm, Finger Width = 600nm, Fingers = 1 NMOS tsmc131g nmos1v symbol Length = 130nm, Finger Width = 300nm, Fingers = 1 GND analogLib gnd symbol VDD analogLib vdd symbol PMOS Library tsmc131g

2.2.2 Add pins

In Virtuoso main window, select Add -> Pin and specify the name and direction (input output, or inout) of the pin that you are to add. For the input pin, we name it IN and give its direction to be input. And the output pin is OUT, and its direction is output. See Fig. 2.10.

Fig. 2.9 Add into the components

Fig. 2.10 Add into the pins

2.2.3 Add wires

Now we can use wires to connect all the transistors and pins. Select Add -> Wire or use hot key w, and then you can click and drag your mouse to add wires. When wiring is done, press Esc with your cursor in the schematic window to cancel wiring. We connect our components to get an inverter (Fig. 2.11).

Fig. 2.11 Connect the components

2.2.4 Save your design

Select Design -> Check and Save. This will first check your design to ensure that it is correct (Fig. 2.12). Then the design will be saved. You can observe all the information in the CIW window.

Fig. 2.12 Check and save the design

2.2.5 Symbol Creation

In the schematic window, select Design Create Cellview From Cellview The Cellview From Cellview form appears. Click OK in the Cellview From Cellview form. The Symbol Generation Form appears. In the Symbol Generation Options window, you can specify your pins. In this case, the tools, by default, place your IN pin on the left and OUT pin on the right (Fig. 2.13). Click

OK. You get a new window which displays an automatically generated symbol. (Fig. 2.14)

Fig. 2.13 Pin specifications

Fig. 2.14 Automatically enerated symbol If you dont like what it looks like now, you can edit the symbol for your inverter. You may first delete the rectangles, and draw a triangle instead by selecting Add -> Shape -> Polygon. Similarly, you add a circle (Fig. 2.15).

Fig. 2.15 Add a symbol shape By adjusting the polygons and moving the pins, we have a symbol like the one shown in Fig. 2.16.

Fig. 2.16 A symbol for inverter

2.4 Builing test circuit

We can build a test circuitry so that later we can evaluate the performance of our inverter. In the Library Manager window, change to the manual_test library and select File -> New -> Cellview. Fill in the name, for example, inverter_test, and click OK. In the Virtuoso window, refer to Table 2.2 to add into an inverter, a capacitor (cap) and a DC power source (vdc) and a signal source (vpulse). We connect them together to obtain a test circuitry as shown in Fig. 2.18.

Fig. 2.17 Create the test circuitry

Table 2.2 Add cells to the test circuitry Library Name manual_test analogLib analogLib analogLib analogLib analogLib Cell name inverter cap vdd gnd vdc vpulse Properties

DC voltage = 1.2V Voltage 1 = 0.0V, Voltage 2 = 1.2V, Delay time = 1ns, Rise time = 1ns

Fig. 2.18 Test circuitry for the inverter

Chapter 3 Pre-layout simulation

Open the inverter_test schematic in your library.

3.1 Start simulation environment

In the Virtuoso window, select Tools -> Analog Environment and you now get a Virtuoso Analog Design Environment window (Fig. 3.1).

3.2 Set the model path

In the Virtuoso Analog Design Environment window, select Setup -> Model Libraries. In the new window, specify the path of the model files (Fig.3.2). Click OK when done.

Fig. 3.1 The Analog Design Environment

Fig. 3.2 Set the model file path

3.3 Choose the desired analysis

In the Virtuoso Analog Design Environment window, select Analyses -> Choose and you get a list of analysis options (Fig. 3.3).

Fig. 3.3 Choose the desired analysis

3.3.1 DC analysis
For example, you may choose dc if you wan to obtain the Vin-Vout curve of the inverter, i.e., the transfer characteristic. To get the transfer characteristic, we have to sweep the inverter input voltage between 0 and VDD (1.2V in this case). Hence, in the Sweep Variable, choose Component Parameter, select the component by clicking the DC power source (vdc) in the schematic window and choose the parameter to be dc. Also, in the Sweep Range, specify the Start and Stop to be 0 and 1.2, respectively. See Fig. 3.4.

Fig. 3.4 Set the dc analysis options

3.3.2 Transient analysis

Choose transient analysis if you want to know about the dynamic behavior of the circuit. For example, we now want to see the waveform of the output voltage when the input voltage rises from 0 to VDD. Specify the Stop Time to be 10ns (Fig. 3.5). Click OK. Then we can simulate the circuit in the time interval between 0 and 5ns.

Fig. 3.5 Set the transient analysis options

3.4 Plot the simulation result

After the simulation is done, the result can be plotted to give a visual presentation. In the Virtuoso Analog Design Environment window, select Outputs -> To Be Plotted -> Select On Schematic. Now you can choose to plot the voltage or/and current values by clicking the corresponding wires and pins. Press ESC when done. Now you can start simulation and plot the result by click the Simulation -> Netlist and Run.

3.4.1 DC analysis
To get the transfer characteristic, we have to plot both input voltage and output voltage of the inverter (Fig. 3.6). Then click Netlist and Run to run the simulation and get the plot. Fig. 3.7 shows the resulting transfer characteristic.

Fig. 3.6 Choose the signals to be plot

Fig. 3.7 Plotting the result of dc analysis

3.4.2 Transient analysis

To do transient analysis, set the input voltage to rise from 0V to 1.2V. Refer to Fig. 3.8 to set the various parameters. Set the Stop Time to be 5ns, and plot the input and output voltage of the inverter. See Fig. 3.9.

Fig. 3.8 Set the input voltage to rise from 0 to VDD

Fig. 3.9 Plotting the result of transient analysis

Chapter 4 Physical Layout

If you have completed pre-layout simulation, now it is time to layout your design! Please refer to the physical design manual provided by the silicon house. This manual usually contains hundred pages of information, such as contrains on layer size, inter and intra layer distances and etc.

4.1 Generate a layout with components not placed

Open the inverter schematic. In the Virtuoso window, select Tools -> Design Synthesis -> Layout XL (Fig. 4.1).

Fig. 4.1 Open layoutXL Choose Create New in Startup Option window (Fig. 4.2).

Fig. 4.2 Create new layout cellview Assume the default names as shown in Create New File window (Fig. 4.3).

Fig. 4.4 Name the layout cellview In the Virtuoso XL Layout Editing window, select Design -> Gen From Source (Fig. 4.5).

Fig. 4.5 Generate layout from source

In the Layout Generation Options window, specify the layer value of I/O pins Layer/Master to be METAL1/dg and assume default values for others (Fig. 4.6). Click OK, and you will see two windows pop out. One is LSW, which stands for Layout Select Window, and the other one is Virtuoso Layout Editing window (Fig. 4.7). In the Virtuoso window, you can see device equivalent of pins and transistors symbols are automatically generated. Besides, the square box is called design boundary. (Fig. 4.8).

Fig. 4.6 Layout generation options

Fig. 4.7 LSW window and layout editing window

Fig. 4.8 Design boundary and components not placed

4.2 Place the components

Now you can manually move and place all the components inside the design boundary (Fig. 4.9).The hot key for moving an object is m.

Fig. 4.9 Place the components inside the boudary

4.3 Connecting the components

Now we have to connect all the components to make a layout equivalent of the schematic. To show the nets that we have to route, select Connectivity -> Show Incomplete Nets, and a new window comes out to list all incomplete nets (Fig. 4.10). Choose Select All and click OK, and you will see all the flight lines in the Virtuoso window (Fig. 4.11). First, we choose POLYG/drw in the LSW window by clicking it. Once it is chosen, it will be highlighted. Then, select Create -> Rectangle to draw the connection between the gate of PMOS and the gate of NMOS.

In the LSW window, select METAL1/drw to draw other connections. That is, from the drain of PMOS to the drain of NMOS, from the source of PMOS to the VDD and the source of NMOS to the GND. Secondly, connect to the IN and OUT pins. When connecting to IN pin, a METAL1-toPOLYG contact is needed. Finally, connect the PMOS body to VDD and the NMOS body to GND. The completed layout of the inverter may look like the one shown in Fig. 4.12.

Fig. 4.10 Show incomplete nets

Fig. 4.11 The flight lines

Fig. 4.12 A layout for the inverter

You have just finished the design of your inverter layout. You need to save it by selecting Design Save.