2nd Electronic Circuits and Systems Conference ECS’99, 1

6-8th September 1999, Bratislava, Slovakia

An Ultra-Low-Power Switched-Current
2-Quadrant Multiplier
A. Graupner and R. Schüffny
University of Technology Dresden, Department of Electrical Engineering,
Mommsenstraße 13, 01062 Dresden, Germany,
graupner@iee.et.tu-dresden.de

Abstract. This paper presents a switched current multiplier, dedicated

for the use in highly parallel computation arrays or neural networks. It is
designed for 3V supply voltage, performing 50k multiplications per second
with a power dissipation of 100nW and an accuracy better than 1.5% consid-
ering the presence of possible device-mismatch.

I Introduction
Analog multipliers are fundamental functional blocks in many circuits and systems. A
lot of different approaches to build analog multipliers has been investigated, one of them is the
application of the translinear principle [1]. Originally formulated for bipolar devices, the trans-
linear principle is based on the exponential voltage-to-current-transfer-characteristics of its
comprising elements. Not only bipolar transistors show the required exponential behavior but
MOS-transistors operating below threshold, too. Consequently, translinear circuits can be
designed with a standard CMOS technology [2].
Unfortunately, translinear circuits comprising subthreshold MOS transistors are very
vulnerable to device mismatch. This problem is often reported and analyzed [3] but simple
solutions for this problem have not been reported yet. Alsam-Sidqui et al. [4] have proposed to
use floating-gates to correct for errors caused by device mismatch. We suggest a dynamic prin-
ciple to reduce the influence of device mismatch on the accuracy of a frequently used translin-
ear multiplier circuit. Our analog multiplier cell is dedicated for the use in massive parallel
computation arrays or in analog neural networks.
In section 2 a conventional translinear multiplier and the problems associated with it
when implementing it in a standard CMOS-technology are reviewed. Furthermore, the general
principle of our switched current multiplier is introduced. Section 3 deals with the actual
implementation of the multiplier circuit and provides some simulation results.

II Translinear Multipliers
A typical translinear multiplier-circuit is depicted in Fig 1a. With the subthreshold trans-
fer characteristics I = I D0 exp ( ( V GS – V T ) ⁄ nU T ) of a transistor in saturation, where ID0 is a
current constant, VGS the gate-source-voltage, VT the threshold voltage, n the subthreshold
slope factor and UT the thermal voltage, the analysis of the translinear loop yields:
I1 ⋅ I3 = I2 ⋅ I4 . (1)
As one can see a multiplication or division of several unipolar currents can easily be performed
using this circuit.
Employing differential signals this circuit is suitable for a two-quadrant operation as
well. The first input signal then is the difference of the currents I 1 – I 4 and the output signal is
represented by the current-difference I 2 – I 3 . Using some basic algebra equation (1) can be
2nd Electronic Circuits and Systems Conference ECS’99, 2
6-8th September 1999, Bratislava, Slovakia

I1 I2 I3 I4
I1 I2 I3 I4

M1 M2 M3 M4 M12 M34

C1 C2

ref V Iw Vref Iw
(a) (b)
Fig. 1: (a) A translinear multiplier cell and (b) its switched-current counterpart
transformed as follows:
I1 – I4
I 2 – I 3 = ---------------- ⋅ ( I 2 + I 3 ) . (2)
I1 + I4
As can be seen, the second input signal is the sum-current I w = I 2 + I 3 .
There are several drawbacks associated with this multiplier. As stated in the introduction
this circuit-topology is very vulnerable to device-mismatch. Mismatch describes the effect that
two identical designed devices have random differences in their behavior. In the subthreshold-
operation device mismatch can be modeled by a variation of the current-constant I D0 from its
nominal value [3]. As the mismatch decreases with increasing transistor area, the influence of
mismatch can be reduced by employing large devices. However, to achieve a high accuracy
the devices would have to be prohibitively large in area.
In order to analyze the influence of mismatch equation (1) is reformed again but the cur-
rent constant I D0 is no longer assumed to be equal in all devices:
I1 I3 I2 I4
------------ ⋅ ------------ = ------------ ⋅ ------------ . (3)
I D0, 1 I D0, 3 I D0, 2 I D0, 4
Accordingly, the mismatch of the current constants yields a constant-gain error for the translin-
ear loop. For the differential-signal case the device-mismatch entails a non-linearity error:
( I 1 – I 4)(ε + 1) + ( I 1 + I 4)(ε – 1) I D0, 2 ⋅ I D0, 4
I 2 – I 3 = ( I 2 + I 3 ) ⋅ --------------------------------------------------------------------------------- with ε = -----------------------------
- .(4)
( I 1 + I 4)(ε + 1) + ( I 1 – I 4)(ε – 1) I D0, 1 ⋅ I D0, 3
Further limitations of this multiplier topology are due to the finite output resistance of
the transistors, the body effect and the voltage-dependency of the slope-factor n . These limita-
tions are common for all translinear subthreshold MOS circuits and discussed elsewhere,
see [2], [5].
The idea for the dynamic approach is adapted from the current-copier-cell [6], where two
devices are dynamically replaced by one device. The functional principle of the proposed mul-
tiplier is depicted in Fig. 1b. In the first clock cycle the transistors M12 and M34 perform the
function of the outer transistors M1 and M4. When equilibrium is reached the input currents I1
and I4 equal the drain-currents of M12 and M34 respectively and the voltages across the capac-
itors C1 and C2 have an adequate value with respect to the common source voltage Vref. In the
2nd Electronic Circuits and Systems Conference ECS’99, 3
6-8th September 1999, Bratislava, Slovakia

Charge-injection-
compensation

30µm
M12 M34

Buffer

Fig. 2: Circuit diagram and layout of the proposed multiplier

second clock cycle all switches are toggled and the gate nodes are disconnected from the rest
of the circuit. Thus, the voltages across the capacitors remain constant and store the input sig-
nal. The transistors M12 and M34 are connected to accomplish the function of the inner tran-
sistors M2 and M3. The second input signal is applied as current Iw into the common source
node whereas the difference of the drain-currents of M12 and M34 represents the adequate
output value.
This circuit operating in discrete time performs the same functionality as its time-contin-
uous counterpart without being sensitive to device-mismatch: As the function of the transistors
M1/M2 and M3/M4 are accomplished by the same devices M12 and M34 respectively there is
no mismatch between the transistors M1-M2 and M3-M4. With I D0, 1 = I D0, 2 and
I D0, 3 = I D0, 4 the error term ε of equation (3) becomes unity. Thus, this dynamic multiplier
is inherently insensitive to device mismatch.

III Actual Circuit Implementation

The functional principle of the dynamic multiplier is shown in Fig. 1b. The main inaccu-
racies of an implementation are caused by the parasitic capacitances of MOS-transistors. From
the first to the second clock cycle the drain and source voltages of M12 and M34 are changing.
According to the capacitive divider formed by the transistor‘s overlap capacitances and the
storing capacitors C1 and C2 the voltages across these capacitors change. As these voltages are
storing the information the signal becomes corrupted. In our implementation the storing nodes
are decoupled by means of source-followers.
A second problem is the clock-feedthrough of the switches connected with the storing
capacitors. When these transistors switch off they release their channel charge. Thus, a part of
the channel charge flows onto the storage-capacitors and corrupts the stored signal. To over-
come this problem a compensation technique known from dynamic current mirrors is
employed [7].
The complete circuit diagram is shown in Fig. 2. The translinear elements have a rather
high W/L-ratio of W/L=10 because the subthreshold operation of the transistors for tail cur-
rents up to 20 nA has to be assured. The storage capacitors are implemented as gate-substrate
capacitors. The source-follower and the transistors for the charge-injection compensation are
marked in the circuit diagram. All switches are minimum-sized devices. This circuit was
implemented using a 0.6 µm digital standard technology. As the layout in Fig. 2 illustrates, the
2nd Electronic Circuits and Systems Conference ECS’99, 4
6-8th September 1999, Bratislava, Slovakia

0.8 I 2 – I 3 I1 – I4 I2 + I3
---------------- = ---------------- ⋅ ---------------- 1.0 0.002 w=1.0
I1 + I4 I1 + I4 I1 + I4 w= 0.75
w= .5









0.4  y w x w=0 0.001

y–x⋅w
y

w=0.25
0 w=0.1 0 w=0.75

-0.4 -0.001 w=0.1

w=0.5
-0.8 -0.002 w=0.25

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
x x
Fig. 3: Simulated multiplication result and multiplication error.

circuit is approximately as small as a basic digital standard cell ( 30 ⋅ 31µm 2 ).

A simulation result with no device-mismatch present is provided in Fig. 3. A small resid-
ual error of some 0.2% due to bulk-effect and finite output resistance of the transistors
remains. By means of Monte-Carlo-simulations the maximum error was determined to be
smaller than 1.5%. The main error is caused by the device mismatch of the switch-compensa-
tion transistor pair.

IV Conclusion
In this paper an accurate translinear two-quadrant-multiplier is presented. It can process
up to 50.000 multiplications per second and dissipates less than 100nW of power. If the signal
is stored up to 20ms the residual error is always less than 1.5% which equals an accuracy of
5 bit. For the derivation of this maximum error the possible mismatch of all devices was taken
into account.
Acknowledgment
This work was supported by the Deutsche Forschungsgemeinschaft (DFG), Sonderfor-
schungsbereich SFB358, project A7.
References
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