2010 International Symposium on Electronic System Design

DESIGN OF A COFFEE VENDING MACHINE USING SINGLE ELECTRON DEVICES

(An example of sequential circuit design)

Biplab Roy (1), and Biswarup Mukherjee (2)

Dept. Of Electronics and Communication Institute of Technology and Marine Engineering, West Bengal, India (1) e-mail: biplabroy@ieee.org, (2)e-mail: biswarup80@gmail.com

Abstract In this paper we propose an implementation technique for sequential circuit using single electron tunneling technology (SET-s) with the example of designing of a coffee vending machine with the goal of getting low power and faster operation. We implement the proposed design based on single electron encoded logic (SEEL).The circuit is tested and compared with the existing CMOS technology. Keywords- SED; coulomb blockade; SEEL

II.

SET JUNCTION

I.

INTRODUCTION

It is well known that in designing a sequential circuit [1], one has to go through the steps- i) drawing state transition graph ii) sate assignment iii) combinational logic synthesis iv) The circuit realization using a specific technology. The technology has so far been the CMOS one for low power operation. But it is expected to be limited in further power and/or area reduction. To overcome that recently various device architectures have been proposed with Single electron tunneling devices (SET-s) as the most studied one for future low power devices. Single electron devices work on the principle of Coulomb Blockade [2] to transfer a single electron charge and provide an alternative way to realize digital logic. The SET devices have got the advantages of fast and low power operation because they use only one electron to do logic and arithmetic operations. Single electron transistors and memories have already been proposed [3, 4] though the replacement of the CMOS Components have not yet been possible. In this paper, we design a coffee vending machine as an example to implement sequential circuit using single electron devices to achieve low power and faster operation. The example is taken because of its critical power requirement

Single electron tunneling devices are now really considered as elements for future devices because of their small size, high speed, and low power consumption. The devices work on the principle of tunneling phenomena .The most important one being the Single Electron Transistor is a three terminal device. From the constructional point of view it can be seen as electron island that has two separate junctions for electron entrance & exit of a single electron with two gates attached to it. One gate tunes the voltage of the whole system whereas another controls the number of electrons coming in and out of the island one at a time. The conduction process is solely based on Coulomb-blockade principle The device is made operational by overcoming the critical voltage Vc of a tunnel junction given by [5]. Vc=q/[2(Ce+Cj)] (1)

where Cj is the capacitance of tunnel junction and Ce is the equivalent capacitance viewed from the junctions perspective and q is the electron charge. The tunneling event (flow of an electron through a tunnel junction) being a stochastic process takes time (also called switching delay) Td given by [5] Td = [-ln(Perror)qe Rt]/[|Vj| -Vc] (2)

where qe=1.6x10-19 C, and Rt= the resistance of the junction and requires the energy Es given by Es=e[|Vj| -Vc] meV (3)

For circuit design using SET devices, two different architecture is used. One being the CMOS/SET hybrid architecture provides high voltage gain & driving ability whereas sacrificing low power feature of SETs partially. The
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978-0-7695-4294-2/10 $26.00 2010 IEEE DOI 10.1109/ISED.2010.16

other is the SET only architecture. Here we proceed with the second one where the charge transport through the junction is essentially considered to be of one electron. III. SEEL(SINGLE ELECTRON ENCODED LOGIC)
Vi V0

It is the digital logic, where 1 is represented by one electron charge (the presence of one electron) and 0 being the absence of the electron. So here, current being the flow of only one electron, the power consumption can be expected to be low. In this architecture, the threshold logic scheme is reported [6, 7] where a generic threshold logic gate is the main building component and is shown in fig 1(b). In this gate, the critical voltage Vc acts as the threshold. If the voltage across the tunnel junction is made higher than this, one electron can tunnel through the junction to/from the output terminal, thus representing 0/1. the voltage of point x is increased by the input voltage Vp weighted by their input capacitors Cp and similarly the voltage of point y is controlled by the Vn inputs thus decreasing the junction voltage with the direction taken as shown. And Vb sets the initial condition. The symbol of this Threshold-Logic-Gate(LTG) is shown in fig.1(a) ,where x1,x2 . . . .xn are the inputs, 1, 2 . . . . . . n are the weights of the corresponding inputs and denotes the threshold unit value. Using this scheme, with the weights set properly any two dimensional logic can be implemented and with mare than one such gates acting together can implement more complex functions. It has been reported [7] that the gate shown in fig 1(b) alone does not work well due to loading effect. To get better performance, buffer is generally connected with it and one buffer again implemented with SET devices is shown in fig. 1(c) (and its symbol in fig. 1(d)) which can also act as a stand alone inverter.

(d)

(c)
Figure 1. (a) Symbol of threshold logic gate (b) circuit of threshold logic gate (c) SET -buffer / inverter (d) symbol of SET -buffer / inverter

IV.

DESIGN OF A COFFEE VENDORING MACHINE

A coffee vending machine can be designed with the help of several BDD devices which in our case are SED-s. For that we start with the statement:To get a cup of coffee out of the machine, one should first press Reset button (which is not the must). Then he/she should put in either Rs 1 or Rs 2 or Rs 5 or Rs 10 coins to make a total of Rs 5 which is the cost of a cup of coffee. If one gives extra amount he/she will get back the balance(here it is Rs1 / Rs 5) together with the coffee with the option of resetting the machine any time. With this statement we draw the state diagram:-

Figure 2. state diagram

(a)

(b)

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Now except the case of input D=coin unit of 10 & actions to be taken for Reset button, the cases for other three types of inputs are considered & they are tabulated in the State table (Table I): (The cases for i/p D & Reset button are considered separately in the final design & also will be explained there. In the State table the input combinations other than those given in the table are considered that they will not occur). The successive procedure of (i)getting state transition table (ii) drawing K-maps leads to the expressions for the inputs of the flip-flops used (here we have used D FF-s) to get the internal states as given in equations (4 - 8)
TABLE I.
PS
C

STATE TABLE
NS
A

I/P-s
B

O/P-s
C0

S0 S0 S0 S0 S1 S1 S1 S2 S2 S2 S3 S3 S3 S4 S4 S4 S5 S6 S7

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0

0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0

S0 S1 S2 S5 S1 S2 S3 S2 S3 S4 S3 S4 S5 S4 S5 S6 S0 S0 S0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

R1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

S0=0, S1=1, S2=2 S3=3, S4=4, S5=, S6=6, S7=7

D0 = Q2 (C +Q0 AC) +Q0CA(Q2 +Q ) = D01 + D02 + D03 + D04 1 D2 = CQ2 +Q2Q1Q0 + BQ2Q +Q2QQ0 AC = D21 + D22 + D23 + D24 1 1 C0 =Q2QQ0 +Q2QQ0 + D=C01 +C02 +C03 1 1
R1 = Q2QQ0 1

(4) (6) (7) (8)

D1 = BQ2 + Q2Q1 AB + Q1Q0 AC + Q2Q1Q0 AC = D11 + D12 + D13 + D14 (5)

And we have Return coin of 5 unit (R5) = D for the same reason that if one gives a coin of 10 unit then he should get a coin of 5 unit as return. After getting the expressions for all those internal variables & the o/p variables in terms of the inputs as well as internal state , we proceed to get SEEL gate circuits for D0, D1 ,D2 internal input lines for the three D-FFs used and also the three output lines of the controller (C0,R1,R5). For that, the individual components of D0, D1, D2 as given in equations (4),(5) and (6) are implemented first and then they are OR-ed to get the D-s (the corresponding gates are shown in figure 3(a-l & q)) as proposed in [8]. Similarly the C0 and R1 (as given in equations (7) & (8)) are implemented (shown in figure 3(m-p)).

Figure 3. (a-q) LTG-s(Linear-Threshold-Gates)U for the combinational expressions(parts of D0,D1,D2, C0,R1) (r) ve edge triggered D-F/F (s) +ve edge triggered D-F/F.

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V.

EXPLANATION

VII. DELAY AND POWER ESTIMATION The maximum time delay & the maximum switching energy of all the gates and the flip-flops are listed in table VI. A. Delay From the table VI and noting that the critical path starts from the ve edge of the clock where the inputs are picked up and ends on making coffee out output line on we get a total maximum delay=0.68ln(Perror) Assuming Perror=the probability of non-occurrence of a tunnel event=10-8, this becomes=12.53ns [10] B. PowerConsumption From table VI and noting that the maximum power consumption will be when the system state changes from state 1 to state 6 , and assuming a clock frequency of 50 MHz, we calculate the maximum power consumption =524.82 x 10-3x 1.6x10-19 x 50 x 106 =4.2pW. CALCULATION PROCEDURE FOR THE VIII. SAMPLE COMPONENT VALUES OF A BUFFERED LTG Taking the case of realizing the Boolean function Y=C.Q2 which is written as: Y=AND (C,Q2) =sgn {C+Q2 -1.5} =sgn(C+1-Q2 -1.5) =sgn(C-Q2-0.5) As the gate is a buffered one, so the LTG without the buffer has to be first realized with the expression: Y=NAND (C.Q2) =sgn (-C+Q2+0.5) Comparing this with the equations (7) & (19) of ref. [7] we get =-0.5 unit and CnC1p= CpC1n (9)

As here we have considered that the external inputs (taken as As, Bs, Cs Ds) are asynchronous which can occur any time, we first pickup the inputs in the ve edge of our system clock with the ve edge triggered D-FF (which is also implemented by SEEL architecture and is shown in fig. 3(s)). After getting the inputs, they are processed by the combinational circuits to get the inputs of the internal state D-FFs . And then at the +ve edge of our system clock, the corresponding state transition is made with the +ve edge triggered D-FFs (implemented using SEEL architecture and is shown in fig.3(r)).The RS line(as shown in fig.3(r)) can be used any time to reset the system such that it starts again from state 0. The component values of the buffers used as shown in fig.1(c) are calculated [9] and given in the table II. These values are same for all the buffers used in this paper.
TABLE II.
Vs 16mV

( ALL NOTATIONS ARE AS IN FIG. A(3))

Cg 0.5C C1 0.1C C2 0.5C C3 0.5C C4 0.1C Cb 4.25C Cl 9C

The component values of the threshold gates used to implement the combinational expressions as well as for the D flip-flops are given in the table V. In our logic circuit we have used C (the unit capacitor) =1aF=10-18 F giving logic1=16mv and logic0=0mV. The switching time-delay (calculated using equation (1) and with the procedure given in [7]) and the switching energy (calculated using equation (3) and with the procedure given in [7]) for all the gates and the flip-flops are tabulated in table VI. VI. RESULTS The final circuit was formed using the figs.3 (a-s) and was tested for several sequence of inputs using well established SIMON simulator and it was found working satisfactorily. Some of the results are tabulated in table III.
TABLE III. Seq. No. 1 RESULTS OF SIMULATION USING SIMON I/P sequence As Bs As As Bs Bs Bs Cs Ds O/P-s
C0 R1 R5

which represents a weight of 1 unit Again as we have taken [0.1e/C] to represent the logic 1(=16mV with C=1aF), so we have: = (-0.5). Cn C1p .(0.1e/C) Taking Cn =10C ,C1p =0.5C and Vb=16mV(logic 1) and using equations (9) & (20) of ref. [7] we get Cb =11C and Cp =11.5C which gives C1n =0.43C[from equation (9)] And using equation (10) of ref. [7] we get C0 =9.57C IX. COMPARISON Here we present a comparison (table IV) between SED implementation and CMOS implementation of the whole circuit and taking the same critical path.
TABLE IV. parameters

0 0 0 1 0 0 1 1 1

0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 1

COMPARISON TABLE
Using SED-s (as calculated in column VII) 12.53ns 4.2pW Using conv. CMOS devices (Typical) 300ns 6.7mW

2 3 4

Switching delay time Total dynamic power dissipation

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X.

DISCUSSION

We have presented a method to design a sequential circuit design based on single electron logic systems using Binary Decision Diagram . We have taken the coffee vending machine as an example to show the details of the design procedure. The results show significant time and power saving over the conventional CMOS circuits.
TABLE V.

Here we have ignored the electron energy quantization inside the conductors , the time taken by an electron to tunnel through a barrier and the co-tunneling events. We have also ignored the operational error due to thermal agitation.

COMPONENT VALUES FOR THE THRESHOLD LOGIC GATES (ALL NOTATIONS ARE AS GIVEN IN FIG A(1 & 2)
Tlg Of fig a b c d e f g h i j k l m n o p q Tkg1 Tlg2 Tlg3 Tlg4 Tlg5 Tlg1 Tlg2 Tlg3 Tlg4 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -1.5 -1.5 -0.5 -0.5 -1.5 -2.5 -1.5 -1.5 -1.5 -0.5 -0.5 0 0 1 1 0.5 1 1 0 0 Cj 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C 0.1C C1p 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 1C 1C 0.5 1C 0.5C 1C C2p 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C 0.5C C3p 0.5C 0.5C 0.5C 0.5C 0.5C Fig r 0.5C Fig s 0.5C C1n 0.43C 0.37C 0.37C 0.37C 0.43C 0.37C 0.37C 0.35C 0.43C 0.4C 0.4C 0.34C 0.4C 0.4C 0.4C 0.5C 0.5C 0.4C 0.5C 0.4C 0.5C 0.4C 0.4C C2n 0.37C 0.35C 0.4C 0.34C 0.4C 0.4C 0.4C 0.5C 0.5C 0.5C 0.5C C3n 0.34C 0.5C 0.5C C4n 0.5C Cb 11C 12C 12C 12C 11C 12C 12.5C 13C 11C 11.5C 12C 13.5C 12C 12C 12C 10.5C 10.5C 12.2C 11.7C 13.2C 13.1C 10.5C 13.2C 1301C 12.2C 11.7C Co 9.57C 9.53C 9.53C 9.53C 9.57C 9.53C 9.26C 9.3C 9.57C 9.6C 9.2C 8.98C 9.2C 9.2C 9.2C 8.5C 8C 8.6C 9C 8C 8.6C 10C 8C 8.6C 8.6C 9C

TABLE VI.

MAXIMUM TIME DELAY & THE MAXIMUM SWITCHING ENERGY OF ALL THE GATES AND THE FLIP-FLOPS Gate/ FF
Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19

Delay time(max)*[ln(Perror)] ns
0.062 0.072 0.072 0.072 0.062 0.072 0.072 0.084 0.062 0.075 0.094 0.043 0.094 0.094 0.094 0.061 0.061 0.21 0.16

Switching energy(max) (meV)

11.48 12.46 12.46 12.46 11.48 12.46 11.94 12.8 11.48 11.96 11.88 12.78 11.88 11.88 11.88 10.8 10.79 64.78 63.8

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REFERENCES
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