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8, AUGUST 2010

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An Effective Control Technique for Medium-Voltage High-Power Induction Motor Fed by Cascaded Neutral-Point-Clamped Inverter
Baoming Ge, Fang Zheng Peng, Fellow, IEEE, Anbal T. de Almeida, Senior Member, IEEE, and Haitham Abu-Rub, Senior Member, IEEE

AbstractFor a cascaded neutral-point-clamped (NPC) inverter applied to the medium-voltage high-power induction-motor (IM) drives, an effective control technique is proposed in this paper. The novel sinusoidal pulsewidth modulation (PWM) pulserotation-control approach, for a wide range of output voltage, provides a simple way to implement vector control for IM when the cascaded NPC inverter is employed. The proposed method presents great benets to the cascaded NPC inverter. The output voltages and power of all inverter modules and the two seriescapacitor dc voltages of each inverter module are perfectly balanced. Moreover, a low switch frequency of all inverter modules supports a synthesized high-frequency PWM phase voltage. The internal voltage drop of the inverter, due to the cascade structure of many insulated-gate bipolar transistordiode modules series connection, is analyzed, which causes the distorted phase voltages and currents at low speeds when the frequency and the output voltage are low. The current closed-loop control compensates the distortion of phase voltages and currents. A rotor-ux-oriented vector control is combined with back-electromotive-force-based model reference adaptive system speed estimation, which results in a speed closed-loop control. The voltage sensors together with the lters of changeable parameters ensure the precision of speed estimation for the whole frequency range. The experimental tests are carried out through an 800-kW 4160-V IM drive fed by the 1-MVA 6000-V 17-level cascaded NPC inverter. The results verify the proposed scheme. Index TermsCascaded multilevel (CML) inverters, mediumvoltage (MV) drives, speed estimation, vector control.
Fig. 1. IM drive based on the cascaded NPC inverter. (a) Cascaded NPC inverter-based IM drive system. (b) NPC inverter module.

I. I NTRODUCTION EDIUM-VOLTAGE ADJUSTABLE-SPEED-DRIVE (MV-ASD) systems offer signicant advantages in a wide range of industrial applications such as fan, pump, and many improved process control systems with higher
Manuscript received January 16, 2009; revised April 12, 2009 and May 26, 2009; accepted May 31, 2009. Date of publication July 17, 2009; date of current version July 14, 2010. B. Ge is with the School of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China, and also with the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI 48824 USA (e-mail: gebaoming@tsinghua.org.cn). F. Z. Peng is with the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI 48824 USA (e-mail: fzpeng@egr.msu.edu). A. T. de Almeida is with the Department of Electrical and Computer Engineering, University of Coimbra, 3030-290 Coimbra, Portugal (e-mail: adealmeida@isr.uc.pt). H. Abu-Rub is with the Department of Electrical and Computer Engineering, Texas A&M University at Qatar, Doha 23874, Qatar (e-mail: haitham. abu-rub@qatar.tamu.edu). Digital Object Identier 10.1109/TIE.2009.2026761

efciencies combined with energy savings. The inductionmotor (IM) drives present an attractive solution because they are cheapest and rugged. The voltage-source-inverter technology has increasingly become a focus in research and applications of MV-ASD systems recently and mainly presents two types of solutions: 1) cascaded multilevel (CML) inverter topology and 2) three-level neutral-point-clamped (NPC) inverter. One aspect of CML inverter apart from the three-level NPC inverter is to utilize small inverter bridges with relatively low voltage to synthesize and reach high voltage, thus, is more suitable for high-voltage, high-power applications [1][13]. The cascaded H-bridge inverter is the bestselling product in the MV-ASD market worldwide [10], but its main drawback is the need of excessive number of transformer windings. To alleviate this problem, a hybrid inverter of cascade and NPC structures, the cascaded NPC inverter, was introduced and developed [14]. For the cascaded H-bridge and NPC inverters, a variety of modulation strategies have been reported, with the most popular being carrier-based pulsewidth modulation (PWM) [6], [15], [16], space-vector modulation (SVM) [17][22], and step

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TABLE I S WITCHING S TATES , O UTPUT VOLTAGES , AND C APACITORS U SED

modulations [6], [23]. Most carrier-based modulation schemes for the NPC inverters derive from the carrier-disposition strategy including phase opposition disposition (POD), alternative POD, and phase disposition (PD) [24]. The PD strategy is well accepted as achieving the lowest line-to-line harmonic voltage distortion. Some modications based on the PD and the SVM are generally required to maintain balanced dc voltages across the series capacitors for NPC inverters, or improve the switching even utilization using redundant switching states [15], [21], [25][28]. The PD-based modulation also was developed for cascaded H-bridge inverter [6], but the phase-shifted carrier PWM is the most common strategy for the cascaded H-bridge inverters [29], since it automatically balances the number of switching transitions between the cells. However, for threephase system, it is now known to be spectrally suboptimal compared with the PD and the centered space-vector PWM (CSVPWM) [30]. Reference [18] used the PD modulator to achieve the CSVPWM by the addition of an offset time signal to the inverter gating signals, where a single carrier replaced multicarrier in its implementation. Reference [30] solved the uneven switching load for a ve-level ying-capacitor converter by the state-machine-based decoder. The conventional PD or CSVPWM is used to select the target switched voltage for each phase, and then a nite state machine distributes the switching pulses among the cells on a cyclical basis. The various modulation strategies aforementioned can be referenced for the cascaded NPC inverters, although a paucity of literature introduces the details. The power-balance control among all the bridge modules and the voltage-balance control between the series capacitors in each NPC bridge module are crucial for the cascaded NPC inverter in practical uses. The state-machine-based scheme in [30] and the pulse-rotation scheme in [6] are hopeful references to solve these problems. However, the state machine of the M-level cascaded NPC inverter is more complex, which will be a limitation to actual implementation. The pulse-rotation scheme in [6] only presented its operation of cascaded H-bridge inverter at low modulation indexes. It still needs further research on how to fulll pulse rotation of cascaded NPC inverter at its whole M-level range. Another issue about the CML conguration is the internal voltage drop from the cascaded series connection of the insulated-gate bipolar transistor (IGBT)diode modules, which becomes substantially high at low speeds when the output voltage is relatively low. The internal voltage drop causes severe

voltage and current distortions at low speeds when the voltage is low. This paper proposes an effective control technique for the MV IMs fed by a cascaded NPC inverter. Pulse-rotation control of cascaded NPC inverter at all M-level ranges guarantees the power natural balance among all NPC bridge modules, particularly the voltage natural balance between the series capacitors in each NPC module. The control system compensates the internal voltage drop and voltage/current distortion and fullls a speedsensorless vector control all over the speed range including very low frequency. The proposed control scheme is applied to control a developed 1-MVA 6000-V 17-level cascaded NPC inverter to drive an 800-kW 4160-V IM. The experimental results verify the proposed scheme of speed-sensorless vector control for IMs fed by the cascaded NPC inverter. II. C ASCADED NPC I NVERTER -BASED IM D RIVE S YSTEM Fig. 1(a) shows the system conguration of the 6000-V/ 1-MVA CML inverter feeding a three-phase IM. Each phase has four cascaded NPC inverter modules, and each module with 1200 V dc, as shown in Fig. 1(b), is capable of producing ve different voltage levels, therefore, generating 17 levels in each phase-to-neutral and 33 levels in phase-to-phase voltage. For each NPC module, three control signals are used to control four 1200-V intelligent power modules (IPMs) (PM200DSA120, each has two IGBTs). Three control signals named as K1, K2, and K3 produce the eight switching signals Sa1, Sa2, Sb1, Sb2, Sa1 , Sa2 , Sb1 , and Sb2 , as shown in Table I. The eight switching signals are sent to the IPMs through the eight isolated drive circuits. Low level of switching signals will make the switch on. Table I shows the output voltages and their switching states, along with which capacitor is used when applicable. The two series-capacitor voltages should be balanced during operation, namely, the average voltages across the two capacitors should be maintained the same, VC1 = VC2 . In addition, the voltage and power of all NPC modules must be well balanced. III. SPWM T ECHNIQUE FOR C ASCADED NPC I NVERTER A. Single Carrier-Based Duty-Cycle Calculation For a 17-level cascaded NPC inverter, the conventional PD strategy needs 16 level-shift carriers, which is quite a hardware

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Fig. 2.

Nine-level modulation.

Fig. 3.

Calculation of duty cycle.

burden. Single-carrier concept overcomes this problem [18]. However, the reference [18] used it in the CSVPWM, instead of sinusoidal PWM (SPWM). This paper will use a single-carrier to produce the needed SPWM signals by chopping the reference signal into the single-carrier range according to the magnitude. To illustrate its basic principle and to make it simpler and less busy in the gure, Fig. 2 shows an example with the use of eight shifted carriers and the use of a single-carrier to generate a nine-level SPWM signal, respectively. The reference is divided into 14 sections to compare with the single carrier. Fig. 3 is used as a general case to calculate the duty cycle, where M denotes modulation index, Tc is the period of the carrier, t1 and t2 are two adjacent time instants corresponding to the maximum and minimum values of the carrier wave, respectively, and Q denotes the Qth level, where 1 Q 8. Then, the duty cycle, ton , is calculated as ton = 4Tc |M sin t1 | + |M sin t2 | Q1 . 8 (1)

B. Pulse Decode Equation (1) will produce an SPWM pulse sequence x, as shown in Fig. 4. It should be decoded into different levels and distributed among the four modules of one phase leg, thus, the multilevel PWM voltage is achieved in Fig. 4. For this purpose, ve bits of binary variables a, b, c, d, and e for a 17-level inverter are dened, where a = 0 presents the positive halfcycle of the reference and a = 1 as the negative half; b = 0 denotes the positive slope of the reference and b = 1 as the

negative slope; and c, d, and e represent level number from 000 to 111, where the reference locates. Therefore, ve binary variables can represent a total of 32 sections of reference for a whole cycle, as shown in Fig. 4. The pulse variable x together with the other ve variables results in a total of 64 switching states. A true-value table between the 64 switching states and the four sets of control signals Kmn , where the subscript m denotes the mth module (m = 1, 2, 3, and 4), and the subscript n denotes the nth control signal (n = 1, 2, and 3), can be obtained. The balance utilization of the two series-capacitors in each NPC module should be taken into account. The a-phase leg in Fig. 1 is used as an example to illustrate the principle of pulse decode. The output voltage of a cascaded inverter is zero when the switching state abcdex is 000000, 010000, 100000, and 110000 as shown in Fig. 4. From Table I, the four sets of control signals should be Km1 Km2 Km3 = 110. The output voltage of the cascaded inverter is Vdc /8 when the switching state abcdex is 000001, 000010, 010010, and 010001 as shown in Fig. 4, where Vdc denotes total dc voltage of one phase leg. From Table I, the four sets of control signals should be K11 K12 K13 = 101, K21 K22 K23 = 110, K31 K32 K33 = 110, K41 K42 K43 = 110, for the cases of 000001 and 010010, where the capacitor C2 of module A1 supports this voltage (VC2 = Vdc /8) and the other modules output zero voltage. Alternately, K11 K12 K13 = 011, K21 K22 K23 = 110, K31 K32 K33 = 110, K41 K42 K43 = 110, for the cases of 010001 and 000010, where the capacitor C1 of module A1 supports this voltage (VC1 = Vdc /8) and the other modules output zero voltage. The output voltage of the cascaded inverter is Vdc /8 when the switching state abcdex is 110001, 110010, 100010, and 100001 as shown in Fig. 4. In the consideration of symmetrical utilization, K11 K12 K13 = 010, K21 K22 K23 = 110, K31 K32 K33 = 110, K41 K42 K43 = 110, for the cases of 110001 and 100010, where the capacitor C1 of module A1 supports this voltage (VC1 = Vdc /8) and the other modules output zero voltage. K11 K12 K13 = 000, K21 K22 K23 = 110, K31 K32 K33 = 110, and K41 K42 K43 = 110, for the cases of 100001 and 110010, where the capacitor C2 of module A1 supports this voltage (VC2 = Vdc /8) and the other modules output zero voltage. The output voltage of the cascaded inverter is Vdc /4 when the switching state abcdex is 000011, 000100, 010011, and 010100 as shown in Fig. 4, where the capacitors C1 and C2 of module A1 support it (VC1 + VC2 = Vdc /4) and the other modules output zero voltage, thus K11 K12 K13 = 100, K21 K22 K23 = 110, K31 K32 K33 = 110, K41 K42 K43 = 110. Symmetrically, the output voltage of the cascaded inverter is Vdc /4 when the switching state abcdex is 110011, 110100, 100011, and 100100 as shown in Fig. 4, where the capacitors C1 and C2 of module A1 support this voltage (VC1 VC2 = Vdc /4) and the other modules output zero voltage. Thus, K11 K12 K13 = 001, K21 K22 K23 = 110, K31 K32 K33 = 110, K41 K42 K43 = 110. The output voltage of the cascaded inverter is 3Vdc /8 when the switching state abcdex is 000101, 000110, 010101, and 010110, as shown in Fig. 4. K11 K12 K13 = 100, K21 K22 K23 = 101, K31 K32 K33 = 110, K41 K42 K43 = 110, for the cases of 000101 and 010110, where the two capacitors of module A1 provide Vdc /4 and the capacitor C2 of module A2 provides

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Fig. 4. Pulse-decode principle.

Vdc /8, and the other modules output zero voltage. Alternately, K11 K12 K13 = 100, K21 K22 K23 = 011, K31 K32 K33 = 110, K41 K42 K43 = 110, for the cases of 000110 and 010101, where the two capacitors of module A1 provide Vdc /4 and the capacitor C1 of module A2 provides Vdc /8, and the other modules output zero voltage. In the same way, a true-value table between 64 switching states and four sets of control signals, where the capacitors used is symmetrical for the positive and negative half-cycles, can be listed. From the true-value table, the deduced logical functions are summarized as K11 = ac + abce + abcd + ac(bd + bd)e + bcdex + bcd(aex + aex) K12 = bcdx + bcde K13 = ad + acd + acd(ex + ex) + acdex K21 = ac + cd + acd(be + be) + acdex + abcdex + abcdex K22 = cd + bcdx + bcde K23 = ac + cdx(ae + ae) + acdex K31 = c + abce + abcd + ace(bd + bd) + bcd(aex + aex) + bcdex K32 = c + cd(bx + be) K33 = acd + acd(ex + ex) + acdex K41 = c + cd + acd(be + be) + acdex + acd(bex + bex) K42 = c + cd + bcdx + bcde K43 = acd(ex + ex) + acdex where the symbol + denotes the logic OR. The produced signals of a, b, c, d, e, and the SPWM pulse sequence x will be decoded into the four sets of control signals, which controls four modules to achieve the desired multilevel output voltage. The utilization of capacitors C1 and C2 will exchange in the same module, if the variable b is reversed.

Fig. 5.

Principle of pulse rotation.

C. Pulse Rotation Pulse rotation is needed for further balancing of the capacitor voltages and module powers. Fig. 5 shows its principle, where Amn denotes the receiver of control signals in the module m of a-phase and locates at the rotor. The rotor rotates at a frequency nc = 0.25/Tc to synchronize with the pulse x. Kmn locates at the stator, and the variable b is sent to logical functions of the stator through a switch. The switch makes b reverse every four pulses, where the reverse function results in the exchange utilization of capacitors C1 and C2 in the same module. The symbol denotes the delivery of values. Fig. 5 shows that K1n A1n , K2n A2n , K3n A3n , K4n A4n . The rotor rotates 90 anticlockwise after the rst pulse of x, thus, there are K1n A4n , K2n A1n , K3n A2n , K4n A3n . After the second pulse, K1n A3n , K2n A4n , K3n A1n , K4n A2n , and so on. One rotating cycle will take four pulses. Fig. 6 shows an example to explain the capacitor utilization at the proposed pulse rotation for a-phase, where the PWM pulses locate within level 2 and the symbol denotes the instant of rotation beginning; van denotes phaseneutral voltage. All capacitors are used by turn at every pulse coming. The modules A1, A2, A3, and A4 will be rotated for utilization in each pulse; also, each series capacitor used in each module will be rotated every four pulses. These ensure the series capacitor voltage balance and power balance of all modules. Fig. 7 shows a block diagram to implement the proposed SPWM control for the cascaded NPC inverter. The DSP outputs

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Fig. 8. Output-voltage pulse of the inverter with internal voltage drop.

Fig. 6.

Example for capacitor utilization at pulse rotation.

Fig. 9. Experimental result.

eight diodes, thus, the actual a-phase voltage is van = 8VDG 8VDD (3)

instead of zero. Similarly, during the negative half-cycle of the motor current, the phase voltage becomes
Fig. 7. Block diagram to implement SPWM.

1 van = Vdc + 9VDG + 7VDD 8 van = 8VDG + 8VDD

(4) (5)

18 binary signals of three phases to a complex programmable logic device (CPLD), where a1 to x1 correspond to a-phase, a2 to x2 to b-phase, and a3 to x3 to c-phase. The logical functions are rstly executed when there is a new input signal in the CPLD. Then, the CPLD will output 36 control signals to the gate-drive boards of the 17-level cascaded NPC inverter after pulse rotation. IV. C ONTROL S YSTEM FOR IM D RIVE F ED BY CML I NVERTER A. Analysis of the Cascaded NPC Inverter Due to the series connection of the IGBTdiode modules, an internal voltage drop of a CML inverter becomes signicant when the output voltage is low at low speeds. Assuming that a positive a-phase current is going to the motor when the inverter is to produce a low output of Vdc /8 in the a-phase, a capacitor in one module of the a-phase presses a positive voltage (Vdc /8) to the IM through the IGBTs and diodes. The a-phase motor current has to go through nine IGBTs and seven diodes. Each IGBT has a voltage drop VDG , and each diode has a drop VDD . Therefore, during the positive half-cycle of the motor current, the actual a-phase voltage becomes van = 1 Vdc 9VDG 7VDD . 8 (2)

when the inverter is to produce a Vdc /8 and zero voltage, respectively. Equations (2)(5) can be illustrated in Fig. 8. A squarewave voltage with a magnitude of the internal voltage drop is superimposed to the output phase voltage. Assuming the motor is running at a phase voltage of 24-V phase-to-neutral voltage, and both IGBT and diode voltage drops are 2.0 V. The total internal voltage would amount to 32 V, which is even larger than the expected phase voltage. This 32-V square wave is superimposed to the motor phase voltage, thus, causing severe voltage and current distortion. Fig. 9 shows an experimental result of the phase voltage and current at 7.4 Hz, where the given phase voltage is 24 V for this purpose of test. It is obvious that the phase voltage and current are distorted. B. Current Compensation To compensate the distortion of the phase currents, a feedback-control method with feedforward is employed to fulll a current closed-loop control. The desired a-phase voltage is
t va = va0

+ kP e + kI
0

edt

(6)

When the inverter is expected to produce a zero output voltage, a positive motor current goes through eight IGBTs and

va0 = Ls

di a dt

(7)

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Fig. 10. Speed-sensorless vector-control-based IM drive.

Fig. 11. Practical hardware in experiments. (a) Cascaded NPC inverter. (b) Control board. (c) Voltage-sensing circuit.

where kP and kI are the proportional and integral gains, respectively, e is the error between the actual current ia and the desired phase current i , and Ls is the stator inductance. The a transfer function of the current closed-loop control system is Ia (s) = s3 Ls Tr s +s2 (kP Tr s +Ls )+s(kI Tr s +kP )+kI Ia (s) s3 Ls Tr s +s2 (Rs Tr s +Ls +kP Tr s ) + s(kI Tr s +Rs +kP )+kI ] with =1 L2 m , Lr Ls Tr = Lr Rr
1

respectively. i and i are -axis components of the stator current vector in stator frame, and the superscript symbol denotes the desired value. ia , ib , and ic are three phase currents, and va , vb , vc are three phase voltages. Te denotes the motor torque. V. E XPERIMENTAL R ESULTS An 800-kW 4160-V IM is fed by the developed cascade NPC inverter shown in Fig. 11(a), and the CPLD XC95288 cooperates with the DSP TMS320LF2407 to implement the proposed control technique, as shown in Fig. 11(b). The parameters of the motor and the converter are listed in the Appendix. The ux-oriented vector control, the current closed-loop control, speed estimation, the speed tracking, and the SPWM pulses are produced in the DSP, and the pulse decode and pulse rotation are fullled in the CPLD. The line voltage contains plenty of harmonics due to the PWM inverter, which will inuence the precision of speed identication, therefore, a rst-order lowpass lter is used to detect the fundamental components of the stator voltages. Moreover, the stator voltage is extremely small at low speed and extremely large at high speed. A voltagesensing method with constant voltage ratio is not suitable for both sides, and the adjustable output range is expectant. For this purpose, the optical signal from the DSP-based board controls three switches ON / OFF states in the designed voltagesensing circuit, which will change the voltage-sensing circuit for different frequency ranges. In particular, three switches will turn on when the frequency is over 6 Hz and turn off below 6 Hz. The input voltage of the voltage sensor is limited under 250 V. Fig. 11(c) gives the prototype of the voltage-sensing circuit. Fig. 12 shows the experimental seven-level voltages versus the binary variables a, b, c, d, e, and x, where the high level

(8)

where Lr , Rr , Lm , Rs , and s are the rotor inductance and resistance, the magnetizing inductance, the stator resistance, and speed slip, respectively. Tr is the rotor-circuit time constant. C. Speed-Sensorless Vector Control Fig. 10 shows the rotor-ux-oriented vector control for IM drives, where Gc is a speed regulator with the proportional and integral type. The current closed-loop control implements the current compensation to force the actual currents track the desired currents. e and s are respective synchronous and slip angular frequencies. r and r are desired and estimated rotor speed, respectively, and r is calculated using the back-EMF-based model reference adaptive system (MRAS) speed estimation in [31]. r , ir , and ir denote the d-axis qs dr ds component of the rotor-ux-linkage vector and the dq-axis components of the stator-current vector, in the rotor-ux frame,

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Fig. 12. Seven-level output voltage and binary variables.

Fig. 14. Results at 0.124 Hz. (a) After compensation. (b) Before compensation.

Fig. 13. Pulse rotation in the cascaded NPC inverter. (a) Three-level phaseneutral and module voltages. (b) Nine-level phaseneutral and module voltages.

of variable -a presents a negative part of output voltages, while its low level for a positive part of output voltages. The high level of variable -b presents a negative slope of output voltages, while its low level for a positive slope. The code cde represents a level number, for example, 000 is level 1, and 001 is level 2, and so on. The curve x in Fig. 12 presents an SPWM sequence, which is distributed to the different level areas in order to get the phaseneutral voltage van on the basis of the binary variables a, b, c, d, and e. The duty cycle of the SPWM is calculated by using (1) in the DSP. Fig. 13 shows the phaseneutral voltage and the module output voltage. The pulse voltage vC1 is from one of four modules in c-phase. The phaseneutral voltage waveform is composed of the sum of the pulse voltages from the four modules. While the effective switching frequency of the phase-neutral voltage is 2 kHz, the switching frequency of each module is limited to 500 Hz, because of pulse rotation.

Fig. 15. Results at 1 Hz. (a) After compensation. (b) Before compensation.

Figs. 14(a) and 15(a) present the current waveforms at 0.124 Hz and 1 Hz, respectively, where the currentcompensation method is used. The current waveforms before

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Fig. 16. Motor drive running at 120 r/min. (a) Dynamic state. (b) Steady state.

Fig. 17. Speed-sensorless IM drive runs below 6 Hz. (a) Starting response from standstill. (b) Steady state at 0.93 Hz.

compensation are shown in Figs. 14(b) and 15(b) for comparison with those of the compensated results. It can be seen that the current compensation greatly improves the current waveforms of the motor and ensures that the current waveforms are sinusoidal. Fig. 16 shows the experimental speed responses to track a given speed of 120 r/min when the speed sensor is employed in the vector-control-based motor-drive system. Fig. 16(a) gives the dynamic responses including the rotor speed and currents of the three phases, and Fig. 16(b) is its steady-state responses. It can be seen that the designed motor drive runs smoothly and steadily. In the following experiments, the rotor speed is estimated, instead of the sensor, and the speed-sensorless vector control is tested in the developed IM drive fed by cascaded NPC inverter. Fig. 17 shows the experimental speed responses when the motor runs below 6 Hz, where Fig. 17(a) shows a speed starting response tracking a given speed of 155 r/min, and Fig. 17(b) is a steady response at 0.93 Hz. It can be seen that the estimated speed is identical to the actual speed, even if it is below 1 Hz. The voltage-sensing circuit change will adjust the range of the measured voltage, which will improve the voltage-sensing precision. Also, the control parameters should be changed due to the ratio change of the voltage sensing. Fig. 18 shows the experimental results when the desired speed is in a trapezoid waveform, where the motor drive starts from standstill, passes through 6 Hz, operates in 403 r/min (13.4 Hz) for 25 s, decelerates, passes through 6 Hz, and then stops. Fig. 19 shows the steady responses in the output of voltage sensor, the estimated speed, the actual speed, and the phase current when the desired motor speed is 348 r/min (11.57 Hz).

Fig. 18.

Motor drive operates in speed of trapezoid waveform.

Fig. 19.

Motor drive operates in speed of 348 r/min.

We nd that the output of the voltage sensor will change a lot when its circuit is switched, as shown in Fig. 18, but the estimated speed still can match the actual speed perfectly. The

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2) Parameters of Experimental Cascaded NPC Inverter Cascaded NPC inverter rating 1 MVA/6000 V. 8210 F/800 V. Capacitor bank C1 /C2 Four IPMs for one module, IPM Type PM200DSA120. Type of clamped diodes MEE250-12DA. R EFERENCES
[1] G. Mondal, K. Sivakumar, R. Ramchand, K. Gopakumar, and E. Levi, A dual seven-level inverter supply for an open-end winding induction motor drive, IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 16651673, May 2009. [2] M. A. Perez, P. Cortes, and J. Rodriguez, Predictive control algorithm technique for multilevel asymmetric cascaded H-bridge inverters, IEEE Trans. Ind. Electron., vol. 55, no. 12, pp. 43544361, Dec. 2008. [3] P. Lezana, J. Rodriguez, and D. A. Oyarzun, Cascaded multilevel inverter with regeneration capability and reduced number of switches, IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 10591066, Mar. 2008. [4] D. Krug, S. Bernet, S. S. Fazel, K. Jalili, and M. Malinowski, Comparison of 2.3-kV medium-voltage multilevel converters for industrial medium-voltage drives, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 29792992, Dec. 2007. [5] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, Multilevel voltage-source-converter topologies for industrial medium-voltage drives, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 29302945, Dec. 2007. [6] L. M. Tolbert, F. Z. Peng, T. Cunnyngham, and J. N. Chiasson, Charge balance control schemes for cascade multilevel converter in hybrid electric vehicles, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 10581064, Oct. 2002. [7] O. Lopez, J. Alvarez, J. Doval-Gandoy, and F. D. Freijedo, Multilevel multiphase space vector PWM algorithm, IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 19331942, May 2008. [8] M. Rotella, G. Penailillo, J. Pereda, and J. Dixon, PWM method to eliminate power sources in a nonredundant 27-level inverter for machine drive applications, IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 194 201, Jan. 2009. [9] J. I. Leon, R. Portillo, S. Vazquez, J. J. Padilla, L. G. Franquelo, and J. M. Carrasco, Simple unied approach to develop a time-domain modulation strategy for single-phase multilevel converters, IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 32393248, Sep. 2008. [10] P. W. Hammond, Enhancing the reliability of modular medium-voltage drives, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 948954, Oct. 2002. [11] J. I. Leon, S. Vazquez, A. J. Watson, L. G. Franquelo, P. W. Wheeler, and J. M. Carrasco, Feed-forward space vector modulation for single-phase multilevel cascaded converters with any DC voltage ratio, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 315325, Feb. 2009. [12] Y. Cheng, C. Qian, M. L. Crow, S. Pekarek, and S. Atcity, A comparison of diode-clamped and cascaded multilevel converters for a STATCOM with energy storage, IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1512 1521, Oct. 2006. [13] J. A. Barrena, L. Marroyo, M. . R. Vidal, and J. R. T. Apraiz, Individual voltage balancing strategy for PWM cascaded H-bridge converterbased STATCOM, IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 2129, Jan. 2008. [14] A. Joseph, J. Wang, Z. Pan, L. Chen, and F. Z. Peng, A 24-pulse rectier cascaded multilevel inverter with minimum number of transformer windings, in Conf. Rec. 40th IEEE Ind. Appl. Soc. Annu. Meeting, Oct. 2005, vol. 1, pp. 115120. [15] J. Zaragoza, J. Pou, S. Ceballos, E. Robles, P. Ibanez, and J. L. Villate, A comprehensive study of a hybrid modulation technique for the neutralpoint-clamped converter, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 294304, Feb. 2009. [16] B. P. McGrath and D. G. Holmes, Multicarrier PWM strategies for multilevel inverters, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 858 867, Aug. 2002. [17] B. P. McGrath, D. G. Holmes, and T. A. Lipo, Optimized space vector switching sequences for multi-level inverters, in Proc. IEEE Appl. Power. Electron. Conf. 16th Annu. Meeting, Anaheim, CA, Mar. 2001, vol. 2, pp. 11231129. [18] R. S. Kanchan, M. R. Baiju, K. K. Mohapatra, P. P. Ouseph, and K. Gopakumar, Space vector PWM signal generation for multilevel inverters using only the sampled amplitudes of reference phase voltages, Proc. Inst. Elect. Eng.Elect. Power Appl., vol. 152, no. 2, pp. 297309, Mar. 2005.

Fig. 20. Output voltage and current waveforms of cascaded NPC inverter.

drive works very well without speed sensor and the estimated speed presents perfect precision. The voltage-sensing circuit change will affect the speed-control dynamics, but has no effect on steady state, as shown in Fig. 18. The dynamic effect on the speed control can be minimized by changing the control parameters correspondingly. Fig. 20 shows the phase voltage and current waveforms from the driven motor operating at 60 Hz. Multilevel output voltages and sine-wave currents are observed. VI. C ONCLUSION This paper has presented an effective control technique for MV high-power IM drives fed by a cascaded NPC inverter developed. The proposed pulse-rotation method, using single carrier instead of multicarriers, together with pulse decode, provided an effective pulse-control method for the cascaded NPC inverter. It ensured the voltage and power balance of all modules and the voltage balance of series capacitors in each module, which worked well for a whole range of output voltage. A high-frequency PWM phase voltage is achieved through low switching frequency of each module. The proposed method has simplied the voltage modulation and has made the hardware burden decrease. The internal voltage drop of the inverter, due to many IGBTdiode in series, results in the voltage and current distortion at low speeds. The current compensation method was proposed to overcome this disadvantage using a current closedloop control. On the basis of the novel SPWM technique, a rotor-ux-oriented vector control was combined with backEMF-based MRAS speed estimation. The experimental results have veried the proposed control technique for MV highpower IM fed by the cascaded NPC inverter.

A PPENDIX 1) Parameters of Experimental IM Three-phase, rated power Rated frequency Poles Rated voltage Rated speed Rated current 800 kW. 60 Hz. 4. 4160 V. 1778 r/min. 128 A.

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[19] M. A. S. Aneesh, A. Gopinath, and M. R. Baiju, A simple space vector PWM generation scheme for any general n-level inverter, IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 16491656, May 2009. [20] A. Gopinath, M. A. S. Aneesh, and M. R. Baiju, Fractal based space vector PWM for multilevel invertersa novel approach, IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 12301237, Apr. 2009. [21] M. Saeedifard, R. Iravani, and J. Pou, A space vector modulation strategy for a back-to-back ve-level HVDC converter system, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 452466, Feb. 2009. [22] J. I. Leon, S. Vazquez, R. Portillo, L. G. Franquelo, J. M. Carrasco, P. W. Wheeler, and A. J. Watson, Three-dimensional feedforward space vector modulation applied to multilevel diode-clamped converters, IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 101109, Jan. 2009. [23] Y. Liu, H. Hong, and A. Q. Huang, Real-time calculation of switching angles minimizing THD for multilevel inverters with step modulation, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 285293, Feb. 2009. [24] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, A new multilevel PWM method: A theoretical analysis, IEEE Trans. Power Electron., vol. 7, no. 3, pp. 497505, Jul. 1992. [25] J. Holtz and N. Oikonomou, Neutral point potential balancing algorithm at low modulation index for three-level inverter medium voltage drives, IEEE Trans. Ind. Appl., vol. 43, no. 3, pp. 761768, May 2007. [26] A. Videt, P. L. Moigne, N. Idir, P. Baudesson, and X. Cimetiere, A new carrier-based PWM providing common-mode-current reduction and DC-bus balancing for three-level inverters, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 30013011, Dec. 2007. [27] H. du Toit Mouton, Natural balancing of three-level neutral-pointclamped PWM inverters, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 10171025, Oct. 2002. [28] J. Zaragoza, J. Pou, S. Ceballos, E. Robles, C. Jaen, and M. Corbalan, Voltage-balance compensator for a carrier-based modulation in the neutral-point-clamped converter, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 305314, Feb. 2009. [29] R. Gupta, A. Ghosh, and A. Joshi, Switching characterization of cascaded multilevel-inverter-controlled systems, IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 10471058, Mar. 2008. [30] B. P. McGrath, T. Meynard, G. Gateau, and D. G. Holmes, Optimal modulation of ying capacitor and stacked multicell converters using a state machine decoder, IEEE Trans. Power Electron., vol. 22, no. 2, pp. 508516, Mar. 2007. [31] F. Z. Peng and T. Fukao, Robust speed identication for speed-sensorless vector control of induction motors, IEEE Trans. Ind. Appl., vol. 30, no. 5, pp. 12341240, Sep. 1994.

Fang Zheng Peng (M92SM96F05) received the B.S. degree in electrical engineering from Wuhan University, Wuhan, China, in 1983 and the M.S. and Ph.D. degrees in electrical engineering from Nagaoka University of Technology, Nagaoka, Japan, in 1987 and 1990, respectively. From 1990 to 1992, he was with Toyo Electric Manufacturing Company, Ltd., Tokyo, Japan, as a Research Scientist and was engaged in research and development of active power lters, exible ac transmission systems (FACTS) applications, and motor drives. From 1992 to 1994, he was with Tokyo Institute of Technology as a Research Assistant Professor and initiated a multilevel inverter program for FACTS applications and a speed-sensorless vector-control project. From 1994 to 2000, he was with Oak Ridge National Laboratory (ORNL), Oak Ridge, TN, as a Research Assistant Professor. From 1994 to 1997, he was with the University of Tennessee, Knoxville, as a Staff Member, and, from 1997 to 2000, he was the Lead (Principal) Scientist with the Power Electronics and Electric Machinery Research Center at ORNL. Since 2000, he has been with the Michigan State University, East Lansing, as an Associate Professor and is currently a Full Professor of the Department of Electrical and Computer Engineering. He is the holder of over ten patents and two of them have been used extensively in industry. Dr. Peng is the recipient of many awards including the 1996 First Prize Paper Award and the 1995 Second Prize Paper Award of Industrial Power Converter Committee in IEEE/IAS Annual Meeting, the 1996 Advanced Technology Award of the Inventors Clubs of America, Inc., the International Hall of Fame, the 1991 First Prize Paper Award in IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS, and the 1990 Best Paper Award in the transactions of the IEE of Japan, the Promotion Award of Electrical Academy. He has served the IEEE Power Electronics Society in many capacities such as Chair of Technical Committee for Rectiers and Inverters, an Associate Editor for the IEEE T RANSACTIONS ON P OWER E LECTRONICS, Region 1-6 Liaison, Member-atLarge, etc.

Anbal T. de Almeida (M85SM03) received the Ph.D. degree in electrical engineering from the Imperial College, University of London, London, U.K., 1977. He is currently a Professor with the Department of Electrical and Computer Engineering, University of Coimbra, Coimbra, Portugal, where he has been the Director of the Institute of Systems and Robotics, since 1993. He is a consultant with the European Commission Framework Programmes. He is the coauthor of six books and more than 150 papers in international journals, meetings, and conferences. He has coordinated several European and national research projects.

Baoming Ge was born in Shanxi, China, 1971. He received the Ph.D. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2000. He was a Postdoctoral Researcher with the Department of Electrical Engineering, Tsinghua University, Beijing, China, from 2000 to 2002, was a Visiting Scholar with the Department of Electrical and Computer Engineering, University of Coimbra, Coimbra, Portugal, from 2004 to 2005, and was a Visiting Professor with the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, from 2007 to 2008. He is currently with the School of Electrical Engineering, Beijing Jiaotong University, Beijing, China, as a Professor. His research interests include permanent-magnet synchronous, switched-reluctance, and induction motors, real-time control of electrical machines, power electronics systems, nonlinear control theories, and applications to electric drives.

Haitham Abu-Rub (M99SM07) received the M.Sc. degree in electrical engineering from Gdynia Marine Academy, Gdynia, Poland, in 1990 and the Ph.D. degree from Gdansk University of Technology, Gdansk, Poland, in 1995. He was with Birzeit University, Palestine, where he held positions as a Professor Assistant and as Professor Associate for eight years and had been appointed as the Chairman of Electrical Engineering Department for four years. He is currently a Senior Associate Professor with the Texas A&M University at Qatar, Doha, Qatar. His main research interests are electrical-machine drives and power electronics. Dr. Abu-Rub is the recipient of many international prestigious awards such as the American Fulbright Scholarship (at Texas A&M University), the German Alexander von Humboldt Fellowship (at Wuppertal University, Wuppertal, Germany), the German DAAD Scholarship (at Bochum University, Bochum, Germany), the British Royal Society Scholarship (at Southampton University, Southampton, U.K.), etc.