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MicroLab-I3S
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1.1.
1.2.
Introduction
Logic gates and flip-flops are the basic elements used to built digital hardware. Small circuits can simply be designed by putting these elements together in a clever way. As soon as the digital hardware gets somehow more complex, such an ad-hoc approach as described is not feasible any more. The need for a structured approach becomes clear. The finite state machine data-path model (FSM-D) is a general purpose architectural model, which supports the structured approach in designing digital hardware on a medium scale complexity.
1.3.
Architecture
1.3.1. FSM-D Structure
The FSM-D model is composed of two basic blocks, the finite state machine (FSM) and the data-path. These two basic blocks work in close collaboration to execute the task or algorithm assigned to the FSM-D circuit. Finite state machines as well as datapaths are very distinct hardware structures, each with its own characteristic and thus each with its preferred type of tasks. Typically a finite state machine can handle control tasks very efficiently. On the other hand a data-path is a preferred candidate to execute calculations and to move or store data. The FSM-D model benefits from these very different characteristics by assigning each of its constituent blocks some preferred type of tasks.
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The Moore machine is slightly restricted in functionality as compared to the Mealy machine. The Moore machine outputs are only dependent on the state and not anymore directly on its inputs. The Moore machine is the most often used implementation type of an FSM in digital circuit as a direct dependency of the outputs to the inputs is often not necessary.
The Medwedjew machine is able to do exactly the same function as a Moore machine. The only difference between them is that a Medwedjew machine does have hazard-free outputs which cannot be guaranteed by any of the other two FSMs. Hazard-free signals have to be guaranteed for signals used as asynchronous set/reset inputs or clocks at flip-flops.
buses, multiplexers, de-multiplexers functional units, like comparators, adders, barrel shifters, etc. memory elements, like flip-flops, registers, register-files, etc.
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The art of data-path design is to develop and to find an optimal structure of the datapath to perform the desired data-path functionality. Besides the functionality the design goal is either to use as few as possible data-path elements or to have a fast as possible data-path structure. Depending on the designers needs, area and/or speed optimization should be achieved.
Figure 5: Typical data-path elements: bus elements (top), functional unit (bottom left), memory element (bottom right).
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Memory elements used in the data-path are slightly different from the ones used in the control-path. Besides the clock and possibly asynchronous set/reset control inputs, the data-path memory elements have in addition a so called enable input. This enable input gives the finite state machine the possibility to control the data-paths memory behavior. Normally at every active clock a register stores the new input value. Now with an active enable signal, the register stores a new value which offers full control of the data-path by the control-path. Figure 6 illustrates the behavior of a memory element with an additional enable input.
Figure 6: Memory elements in the data-path have an additional enable input signal in order to be fully controllable by the FSM.
1.4.
The structured design approaches definitely do have their advantages. On the other hand, the designer has to be aware that the structured approach may limit the solution space. This is due to the fact that a structured approach is like a guide to the designer following an existing road and thus normally prevents the designer from leaving the road and detecting or inventing new solutions.
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To discuss the design steps in detail, a tutorial design example shall be introduced. The only reason to introduce the following design example is to have a vehicle to demonstrate and validate the design steps on a real but small design. Thereupon the discussion on which sub-task should be implemented by each one of the two blocks (FSM or data-path) can be discussed on a concrete example. The algorithm to be implemented with the FSM-D architectural model is that of a black jack player. The digital circuit should be able to play the black jack game. The goal of the game is to get as close as possible to 21 points by asking for cards and adding up their points. If the player exceeds 21 points he has lost the game. The player can ask for as many cards as he wants to have. The cards may have the following points: boy (10), lady (10), king (10), 2, 3, 4, 5, 6, 7, 8, 9, 10 and Ace (11). If the player does have an Ace (11 points) in his card pile he can choose if he wants to count the Ace as 11 points or just 1 point. We have to tell our digital black jack player how risky he should play the game. He should ask for new cards as long as his summed-up points are below 16. He should initially count 11 points for an Ace. If he should suddenly exceed 21 points, this rule gives him a second chance by replacing the 11 points for the Ace by 1 point.
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The BlackJack player will ask for several cards and sum them up. An adder followed by a register to store the result is necessary. Lets call the summed and stored result regAdd and its enable signal enaAdd. To accumulate the card values, a feedback path from the result register to one of the adders inputs is needed.
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To decide when to stop asking for cards, the control-path needs to know the summed card values but only if value boundaries have been crossed. The data-path thus needs to provide the information if more than 16 points have been accumulated cmp16 or if already more than 21 points have been accumalated cmp21. As soon as enough points are accumulated, the BlackJack player will show his score, thus an output register is necessary to block or pass the score to the outside world.
Figure 11: Designing the data-path: comparing the accumulated card values and showing end result.
The data-path sometimes has to change an Ace (11 points) to 1 point. This might be done by subtracting 10 points from the accumulated card values. Instead of subtracting 10 points we also can add -10 points using the already available adder. As there is no access to the adder for a third input to add -10 points, a multiplexer can help. By selecting the multiplexers path, either the cardValue or -10 can be loaded into the first register.
Figure 12: Designing the data-path: a multiplexer at the input is used to subtract the constant 10. This figure shows the final data-path for the BlackJack player.
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Clock signal, active on rising edge: clk Asynchronous reset signal, active low: rst 4 bit data bus input for the card points: cardValue(3:0) 5 bit data bus output for the sore points: score(4:0) information signals for card value comparison, active high: cmp11 (1 if Ace present), cmp16 (1 if more than 16 points), cmp21 (1 if more than 21 points) multiplexer input selection signal: sel (0 for selection of -10, 1 for selection of cardValue) data-path register enable signals, active high: enaLoad, enaAdd, enaScore
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All interfaces are now defined. Starting with the overall interface in design step 2 and continuing with the interfaces of the two sub-blocks namely data-path in design step 4 and FSM in design step 5, we now have the completed hierarchical FSM-D architecture design (see Figure 15).
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state name finished lost newCard sel enaLoad enaAdd enaScore finished lost newCard sel enaLoad enaAdd enaScore finished lost newCard sel enaLoad enaAdd enaScore
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state name
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Figure 16: FSM skeleton state and A4 paper with numerous copied skeleton states.
Figure 17: Timing of FSM-D architectural models using Moore type FSM. The letters in brackets define the signal source, data-path (D) or control-path (FSM).
For a single clock cycle schema, a FSM-D architectural model follows the timing illustrated in Figure 17. When designing state diagrams, much care has to be taken in the timing of the signals between the FSM and the data-path. Basically we have to distinguish between the following two situations: An artificial state LoadReg in Figure 17 is supposed to ask the data-path to load a register (register is in data-path) and thus issues a register enable signal (enable is a FSM output). The new value in the register will be available in the next state CheckVal. A signal inform generated in the data-path
In contrast to Moore type finite state machines, the output values in Mealy type machines are not only defined by the states but also by the state transitions. To show this situation, in Mealy machine diagrams, input conditions as well as output values need to be attached to the transition arrows.
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used to inform the FSM about some operations using the registers contents will not be available in the LoadReg state but only in the next state CheckVal. Thus the finite-state machine can use the inform signal as a condition only when leaving the CheckVal state. A different situation is illustrated in state OpenData. In OpenData the FSM signals the data-path with the signal select (select is a FSM output) the data-path to send some data on a data bus which will be done immediately as long as pure combinatorial logic is responsible for the necessary operation as is the case when using multiplexers or other combinatorial logic elements. In this case the data on the data bus may already be used when leaving the state OpenData. Tutorial Example: In our BlackJack tutorial example the FSM skeleton state is defined by a placeholder for its name and the seven signal output names. Figure 18 illustrates the interface step graphically. It is up to the reader of this text to design the complete state diagram of the BlackJack player.
cmp11 <= 1 when (regLoad = 001011) else 0; cmp16 <= 1 when (regAdd > 010000) else 0; cmp21 <= 1 when (regAdd > 010101) else 0; process(clk,rst) begin if (rst = 0) then regLoad <= 00000; regAdd <= 00000; score <= 00000; elsif (clkevent and clk=1) then if (enaAdd = 1) then regAdd <= regAdd + 1; end if; end if; end process;
FSM: The Moore type finite state machine is coded in two VHDL processes. A first process describes the transitions between the states. In a second process the output values are assigned for each state. In both processes a large case statement is used for the numerous states (see Figure 19).
state
s[k+1] i[k] transition logic state register output logic o[k]
s[k]
process(clk,rst) begin if (rst = 0) then state <= StartState; elsif (clkevent and clk=0) then case state is when StartState => state <= CallCard; when CallCard => if (cardReady = 1) then state <= LoadCard; end if; when others => state <= IllegalState; -- used for VHDL analysis -- null used for synthesis end case; end if; end process;
process(state) begin case state is when StartState => outvec <= 000--00; when CallCard => outvec <= 001--00; when others => outvec <= UUUUUUU; -- used for VHDL analysis -- null used for synthesis end case; end process; finished <= outvec(6); lost <= outvec(5); newCard <=outvec(4); ...
Figure 20: Moore type finite-state machine and its VHDL coding.
Figure 21: Test-cycle. Stimuli are always applied at the beginning of a test-cycle, response is always captured after the active clock edge at the same offset time relative to the beginning of a test-cycle.
Tutorial Example: The VHDL code of a test-bench has an entity without any input or output signals, like a laboratory where no signals will be wired through the labs door. The structure of the VHDL test-bench for our BlackJack player may look as the skeleton sample shown in Figure 21. Be aware, that the automatic response verification is now implemented in our sample test-bench. As the time is quite short, it is the designers duty to verify the correct DUT response visually.
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use IEEE.std_logic_1164.all entity tb_BlackJack is end tb_BlackJack; architecture skeleton of tb_BlackJack is begin signal sync,clock,start,newCard : std_logic; signal cardReady,finished,lost, : std_logic; signal cardValue: std_logic_vector(3 downto 0); signal score: std_logic_vector(4 downto 0); component BlackJack port(clock,start,newCard,cardReady: in std_logic; newCard,finished,lost: out std_logic; cardValue: in std_logic_vector(3 downto 0); score: in std_logic_vector(4 downto 0); end component; begin DUT: BlackJack port map (clock,start,newCard,cardReady, newCard,finished,lost,cardValue,score); ClockGenerator: process begin clock <= 0, 1 after 20 ns, 0 after 70 ns; sync <= 1, 0 after 1 ns; wait for 100 ns; end process; TestPatternGenerator: process begin start <= 0 -- test cycle 1 wait for 100 ns; start <= 1; -- test cycle 2 wait until (syncevent and sync=1 and newCard=1); cardValue <= 10101; -- test cycle cardReady <= 1; wait until (syncevent and sync=1 and newCard=0); cardValue <= UUUUU; -- test cycle cardReady <= 0; wait until (syncevent and sync=1 and newCard=1); ... wait; end process; end skeleton; configuration tb_cfg of tb_BlackJack is for skeleton end for; end configuration tb_cfg; Figure 22: VHDL test-bench. A test-bench is composed of three elements: deviceunder-test, pattern and signal generator, logic analyzer
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A simulation of the BlackJack player, based on the test-bench methodology is visualized in Figure 23. The visualization of internal VHDL signals like data-path registers and especially the state of the finite state machine are very helpful.
1.5.
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1.6.
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