A project report On

VHDL Implementation and Synthesis of

Data Encryption Algorithm
Submitted in partial fulfillment of the requirements for the award of the degree of

Bachelor of Technology in Electronics and Communications BY B.Navya sree (08651A0453) K.V.K.N.Gupta (08651A0422) M.B.Santhosh kumar (08651A0409)
Under the esteemed guidance of

Sri.S.Naveen Kumar
M.Tech,MISTE

Senior Assistant Professor, Department of ECE, Adams Engg College, Paloncha.

Department of Electronics & Communication Engineering Adams Engineering College Jawaharlal Nehru Technological University Paloncha 507115(A.P.)
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Adams Engineering College Jawaharlal Nehru Technological University Paloncha 507115 Andhra Pradesh, India

CERTIFICATE
This is to certify that project work entitled VHDL Implementation and synthesis of Data Encryption Algorithm is being submitted for the partial fulfillment of Bachelor of Technology in Electronics and Communication Engineering to Adams Engineering College affiliated to JNTUH, is bonafied work done by B.Navya sree(08651A0453),K.V.K.N.Gupta(08651A0422), M.B.Santhosh Kumar (08651A0409),during the academic year 2010-2011 under our guidance and supervision, and, it has been found worthy of acceptance according to the requirement of the university.

Internal Guide Sri.S.Naveen Kumar M.Tech,MISTE Senior Assistant Professor Department of ECE, Adams engineering college, Paloncha.

Head of the Department Sri.A.VenkateswarluMTech,MISTE,MIEEE Senior Assistant Professor, Department of ECE, Adams engineering college, Paloncha.

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ACKNOWLEDGEMENTS
The Satisfaction that accomplishes the successful completion of any task would be incomplete without the mention of the people who make it possible and whose constant guidance and encouragement crown all the efforts with success.

It is my privilege and pleasure to express my profound sense of respect , gratitude and indebtedness to my guide Sri.S.Naveen Kumar, Senior Assistant Professor, Department of ECE Adams Engineering College, Paloncha ,For his constant guidance, inspiration ,and constant encouragement throughout this research work.

I wish to express my deep gratitude to Sri.A.Venkateswarlu, Senior Assistant Professor, Head of the Department of ECE, Adams engineering College, Paloncha, for his cooperation and encouragement, in addition to providing necessary facilities throughout the project work. I Sincerely extend my thanks to Prof.N.Nageswar Rao ,Principal, Adams engineering college, Paloncha. I would like to thank all the staff and all my friends for hair good wishes, their helping hand and constructive criticism, which held the successful completion of this project. I would like to express deep gratitude to Adams engineering College, Paloncha for providing the opportunity to carry out this endure.

Finally, I thank all those who directly and indirectly helped me in this regard I apologize for not listing everyone here.

B.Navya sree, K.V.K.N.Gupta, M.B.Santhosh Kumar

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DECLARATION

We, B.Navya sree (08651A0453) , K.V.K.N.Gupta (08651A0422), M.B.Santhosh kumar (08651A0409), hereby submit that the Project Report entitled VHDL Implementation and Synthesis of Data Encryption Algorithm, under the valuable guidance of Sri.S.Naveen Kumar
M.Tech,MISTE.,

Senior Assistant Professor, Department of Electronics & Communication

Engineering, in partial fulfillment of the requirement for the award of the Degree of Master of Technology in Electronics and Communication Engineering, and this is a record of bonafide work carried out by me and the results embodied in this Project Report have not been submitted to any other University or Institute for the award of any other degree or diploma.

B.Navya sree, K.V.K.N.Gupta, M.B.Santhosh kumar.

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Abstract VHDL IMPLEMENTATION AND SYNTHESIS OF DATA ENCRYPTION ALGORITHM

Encryption is the process of converting information into an encrypted form, so that it is intelligible only to someone who knows how to decrypt it to obtain the original message. It is commonly used in connection with electronic data, whether stored on a computer or transmitted over an unsecured network such as the Internet. Encryption tools (usually in the form of computer programs or software) are widely available and can be used to secure: Stored data, from single files to entire hard disks; Computer code such as computer operating systems; Information transmitted over the Internet, including emails and internet telephony (Voice over Internet Protocol or VOIP); Entire communications infrastructures, such as wireless networks (including mobile telephony). Encryption is increasingly used to protect digital information, from personal details held on a computer to financial details transmitted over the Internet. Encryption has many benefits but can also be used to conceal criminal activity. Encryption involves taking an original message or plaintext and converting it into cipher text using an encryption algorithm and an encryption key. Computers store electronic data in binary form, as sequences of bits (1s and 0s). Modern algorithms are mathematical functions that act on these data with keys that are themselves sequences of 1s and 0s. Keys are generally stored in computer files that are themselves encrypted and can be accessed only with a passphrase (similar to a password but longer). A form of encryption techniques used in this project uses an LFSR (Linear Feedback Shift Register) to generate the random KEY, which is then XORed with the incoming DataStream to generate the encrypted data. Similar LFSR is used at the receiver to form decryption logic. The objective of this project is to implement the data encryption logic. The source code is written using VHDL, simulated in Xilinx ISE environment and then synthesized using Xilinx Synthesis tools.

TABLE OF CONTENTS
ACKNOWLEDGEMENTS

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DECLARATION ABSTRACT CONTENTS LIST OF FIGURES LIST OF TABLES LIST OF ABBREVIATIONS

Chapter 1 1 INTRODUCTION 1.1 1.2 1.3 1.4 1.5 Aim of the thesis Digital system design process History Literature survey Organization of thesis

(1 - 5) 2 2 3 3 4 5

Chapter 2 2 INTRODUCTION TO VLSI AND TOOLS 2.1 2.2 2.3 2.4 Typical IC design flow Logic Synthesis Active HDL Overflow Standards supported by Xilinx-HDL 2.4.1 VHDL 2.4.2 Verilog 2.4.3 EDIF 2.4.4 VITAL 2.4.5 Waves . 2.5 Xilinx-HDL macro language
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(6 - 22) 7 8 9 11 12 12 12 12 12 12 13

2.6 2.7

Entity declaration Architecture body 2.7.1 Structural style of modeling 2.7.2 Data flow style of modeling 2.7.3 Behavioral style of modeling 2.7.4 Mixed style of modeling

15 15 15 16 16 17 17 17 18 19 19 19 20 20 21 21 22

2.8 2.9 2.10 2.11

Model Analysis Simulation Process statement Conditional statement 2.11.1 IF statement 2.11.2 Case statement 2.11.3 Loop statements

2.12

XILINX 2.12.1 Design entry 2.12.2 Implementation 2.12.3 Device download and Program file formatting

Chapter 3 3 DATA ENCRYPTION ALGORITHM 3.1 3.2 3.3 3.4 Encryption Decryption Basic block diagram of Encryption and decryption Types of Encryption 3.4.1 3.4.2 3.5 3.6 3.7 3.8 3.9 Symmetric Encryption Asymmetric Encryption

(23 - 33) 24 24 25 25 26 26 27 27 28 30 30 30
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Encryption Key Encryption Algorithm Operation of cipher Applications of Encryption Linear feedback shift register

3.10

Types of Lfsr

32

Chapter 4 4 DESIGN AND ARCHITECTURE 4.1 4.2 4.3 Linear feedback shift register Encryption Decryption

(34 - 37) 35 35 36 37

Chapter 5 5 EXPERIMENTAL RESULTS AND ANALYSIS 5.1 Simulation results for Data Encryption Algorithm. 5.1.1 5.1.2 5.1.3 5.2 Simulation results of LFSR Simulation results of Encryption Simulation results of Decryption

(38 - 48) 39 39 39 39 40 40 40 43 46

Synthesis Reports and net list of Data Encryption Algorithm 5.2.1 5.2.2 5.2.3 Synthesis Reports and net list of LFSR Synthesis Reports and net list of Encryption Synthesis Reports and net list of Decryption.

Chapter 6 6 CONCLUSIONS 6.1 6.2 6.3 Encryption today Scope of Future Work Survey

(49 -51 ) 50 50 50 51

References Appendix A Appendix B Appendix C Appendix D VHDL Source code of LFSR VHDL Source code of Encryptions VHDL Source code of Dcryptions Glossaires

52 53 54 55 57

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List of Figures
Figure No.
1.2 2.1 2.2 2.2.1 2.3 3.1 3.3

Name of the figures

Digital system design process Typical IC design flow Micron Technology Flowchart of Logic synthesis Flowchart of a VHDL Functional description of Encryption procedure Basic block diagram of Encryption and decryption

page no.
3 8 9 10 11 24 25

3.6.2 3.9 3.10(a, b) 3.10(c, d) 4.1 4.2 4.3 5.1.1 5.1.2 5.1.3 5.2.1(a, b) 5.2.1(c, d) 5.2.2(a, b) 5.2.2(c, d) 5.2.3(a, b) 5.2.3(c, d)

Concept of encryption engine Representation of primitive polynomial Illustrate a External LFSR Illustrate a Internal LFSR Representation of LFSR Representation of Encryption Representation of Decryption Simulation results of LFSR Simulation results of Encryption Simulation results of Decryption View of LFSR Rtl net list View of LFSR Technological net list View of Encryption Rtl net list View of Encryption technological netlist View of Decryption Rtl net list View of Decryption technological netlist

28 31 33 33 35 36 37 39 39 40 42 43 45 45 47 48

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List of Tables
Table No. 3.6.1 3.6.3 4.1 4.2 4.3 Name of the table The four primitive feedback polynomial The mappings of T1 and T2 I/ O ports description of LFSR I/O ports description of Encryption I/O ports description of Decryption page no., 28 29 35 36 37

List of Abbreviations
CMOS CPLD DSM EDIF FPGA GUI ISO ISE IEEE LFSR MSI RTL SM SSI VDSM VLSI VHSIC VHDL XST Complementary Metal Oxide Semiconductor Complex Programmable Logic Device Deep sub micron technology Electronic Design Interchange Format Field-Programmable Gate Array Graphical user interface Independent Sales Organizations Integrated Software Environment Institute of Electrical and Electronics Engineers Linear feedback shift register Medium Scale Integration Register transfer level Sub micron technology Small Scale Integration Very deep Sub micron technology Very Large Scale Integration Very high speed integrated chip VHSIC hardware description language Xilinx Synthesis Technology

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