Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Outcome
After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output timing diagram (waveform) for single and combination of latches and flip-flops Troubleshoot basic flip-flops circuits
FKEKK
Terminology
Multivibrator A class of digital circuits in which the output is connected back to the input (i.e. it is fed back to the input, commonly referred to as feedback) to produce either two stable states, one stable state, or no stable states, depending on the configuration. Bistable Having two stable states. Latches and flip-flops are bistable multivibrators Latch An asynchronous bistable multivibrator, used for storing 1 bit Flip-Flop A synchronous bistable multivibrator, used for storing 1 bit
Teminology (continue..)
Asynchronous
There is no fixed timing relationship
Synchronous
There is a fixed timing relationship, usually through the use of a clock pulse
Edge-triggered Flip-Flop
A type of flip-flop in which the input data are entered and appear on the output on the same clock edge, either the positive or negative edge
FKEKK
Introduction (continue..)
FKEKK
Introduction (continue..)
Multivibrator any digital circuit employing feedback. Sequential/Multivibrator devices are categorized as; Bistable Two stable states, SET and RESET Latches and flip-flops Monostable Has one stable state Timer Astable No stable state Oscillator (to generate periodic pulse waveforms for timing purposes. )
Fig: inverter with feedback
7
Latches
Latches are bistable multivibrator A two stable states digital circuit that produces HIGH or LOW depending on the input For gated (enabled) latches, the output are controlled by the enable (EN) input It is level triggered, means that any input changes during the EN is active, the output will be affected The operation will be observed by examining the timing diagram
FKEKK
Latches (continue..)
Four types; S-R latch S-R latch
Gated D latch
Truth table
10
FKEKK
11
Truth table
12
FKEKK
13
Truth table
14
FKEKK
15
Gated D latch
Logic circuit Symbol
Truth table
16
FKEKK
17
NAND gate
Negative-OR gate
18
FKEKK
Change both S and R to 1, therefore both Q and Q are still the same as previous value
19
Change both S and R to 1, therefore both Q and Q are still the same as previous value
20
FKEKK
10
This state should be avoided since the changing state from invalid is unpredictable. Prove it!!!
21
22
FKEKK
11
Latch applications
SR and D latches are among the simplest and least expensive types of memory elements used in logic circuits.
Edge-Triggered Flip-Flops
Flip-flops are synchronous bistable multivibrator. Synchronous means the output changes state only occur at a triggering point called clock Edge-triggered can be either positive (rising) edge or negative (falling) edge of the clock Edge triggered flip-flops change state either at positive or negative clock Clock input for flip-flops
24
FKEKK
12
D flip-flops
J-K flip-flops
T flip-flops
25
26
FKEKK
13
27
Edge-Triggered D Flip-Flop
Positive-edge D FF
28
FKEKK
14
29
30
FKEKK
15
31
Edge-Triggered T Flip-Flop
Positive-edge T FF
32
FKEKK
16
33
34
FKEKK
17
Qo
Q1
35
36
FKEKK
18
CLK Q tPLH
Set-up Time Minimum time interval for the signal to retain the value before clock pulse is triggered
D CLK ts 37
Maximum Clock Frequency Highest rate at which a flip-flop can respond to the input signal
fmax
38
FKEKK
19
39
Flip-Flop Applications
40
FKEKK
20
41
42
FKEKK
21
Exercises
(a) What is the difference between latch and flip-flop operation? (b) List 3 applications of flip-flops. Explain briefly each of the application of the flipflops. (c) Give the definition and describe the propagation delay time in flip-flop operating characteristics.
43
Exercises (Continue)
(d) For negative edge triggered J-K flip-flop with preset (/PRE) and (/ CLR) inputs, determine the Q output for the input shown in the timing diagram in Figure Q1(d). Assume Q starts with 1 and the input J and K always 1.
44
FKEKK
22